CN104113336A - Digital-to-analog converter test method, test system and controller - Google Patents
Digital-to-analog converter test method, test system and controller Download PDFInfo
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Abstract
The invention provides a digital-to-analog converter test method, a test system and a controller. The test system comprises the controller which is used for controlling generation of control parameters required for testing a digital-to-analog converter to be tested and outputting the control parameters; a test motherboard which is used for receiving the control parameters and periodically reading test vector fragments in the control parameters in a cycle way according to control fields in the control parameters and periodically outputting the test vector fragments in the required rate; a test daughter-board which is used for receiving the continuous and periodical test vector fragments and testing the digital-to-analog converter to be tested so that analog output is generated by the digital-to-analog converter; and an analysis display instrument which is used for receiving analog output, analyzing characteristics of the digital-to-analog converter to be tested and displaying the characteristics. The test vectors can be rapidly configured via the scheme, a test of static and frequency domain parameters of the digital-to-analog converter can be completed and test efficiency and reliability can be enhanced. Meanwhile, test cost is low, and requirements for flexible function expansion and modification can be rapidly met on the basis of great software and hardware frameworks.
Description
Technical field
The present invention relates to mixed signal chip test technical field, refer to especially a kind of method of testing, test macro and controller of digital to analog converter.
Background technology
Digital to analog converter, as the bridge between digital signal and analog signal, is an important component part in holonomic system signal chains, is widely used in for a long time the fields such as guided missile, satellite, Aero-Space, communication, consumer electronics, observing and controlling always.Especially in the fields such as military affairs, communication, high performance digital to analog converter is being played the part of vital role, and therefore, academia and industrial circle have all dropped into huge energy and constantly pursued higher performance in recent years.
Along with improving constantly of chip integration, performance index, to testing scheme, at aspect requirements such as precision, reliability, efficiency, also corresponding when the river rises the boat goes up for it, and test has become the link that in very lagre scale integrated circuit (VLSIC) (VLSI) processes of research & development, cost is the highest, difficulty is maximum.And high performance mixed signal chip taking high-speed A/D converter, analog to digital converter as representative is particularly harsh to the requirement of measuring technology, often representing highest level in the industry.For this testing requirement, the company of many specialties (as Teradyne, Advantest) has released corresponding automated test device (Automated Testing Equipment in the industry, ATE), by ATE, designer can obtain the performance index of chip fast, defect and the deficiency of finding in time chip, this is conducive to accelerate the iteration speed of chip design.
Conventionally, ATE be one by the computer-controlled aggregate that comprises the equipment such as High Precision Multimeter, analyzer, high-speed, high precision analog input card, its high modularization, often can match different modules according to the actual requirements.ATE can provide high accuracy, high stability, jamproof test environment, and its test result has good accuracy and confidence level.In addition, due to its supermatic testing scheme, for large batch of testing requirement, ATE also can provide very high testing efficiency.
But the price of ATE equipment is but very high, for the testing requirement of the chips such as high-speed A/D converter, corresponding ATE equipment price is often more than the magnitude of 1,000,000 dollars, and this is burdensome for colleges and universities, medium-sized and small enterprises.Even employ Feng Ce factory, its test spending also should not be underestimated.Especially for R&D institutions such as colleges and universities, its testing requirement often small lot, flexible and changeable, obviously, use the testing scheme of ATE not only with high costs, and be difficult to meet the demand such as Function Extension, amendment flexibly.
Summary of the invention
The technical problem to be solved in the present invention is to provide a kind of method of testing, test macro and controller of digital to analog converter, and in solution prior art, digital to analog converter testing cost is high, and tester is difficult to meet the problem of the demand such as Function Extension, amendment flexibly.
For solving the problems of the technologies described above, embodiments of the invention provide a kind of method of testing of digital to analog converter, comprise the steps:
Control and produce the needed control parameter of test digital to analog converter to be measured output;
Receive described control parameter, and read the test vector fragment in described control parameter according to the control field periodic cycle in described control parameter;
Periodically output of speed by described test vector fragment with demand;
The described test vector fragment that receives consecutive periods is tested digital to analog converter to be measured, makes described digital to analog converter produce simulation output;
Receive described simulation output, and then analyze the characteristic of described digital to analog converter to be measured and show.
Above-mentioned method of testing, wherein, export described control parameter and also comprise before:
Described control parameter is packaged into any number according to bag.
Above-mentioned method of testing, wherein, reads described test vector fragment and also comprises before:
Receive described packet and decode, obtaining described control parameter;
Preserve the described control parameter that decoding obtains.
Above-mentioned method of testing, wherein, the output logic clock of described test vector fragment and the sampling clock homology of described digital to analog converter to be measured.
The present invention also provides a kind of test macro of digital to analog converter, comprising:
Controller, produces the needed control parameter of test digital to analog converter to be measured output for controlling;
Test motherboard, for receiving described control parameter, and reads the test vector fragment in described control parameter according to the control field periodic cycle in described control parameter, the periodically output of speed by described test vector fragment with demand;
Test daughter board, tests digital to analog converter to be measured for the described test vector fragment that receives consecutive periods, makes described digital to analog converter produce simulation output;
Analyze display instrument, for receiving described simulation output, and then analyze the characteristic of described digital to analog converter to be measured and show.
Above-mentioned test macro, wherein, described controller comprises:
Package module, for will be described be packaged into any number according to bag by described control parameter before the output of control parameter.
Above-mentioned test macro, wherein, described test motherboard comprises:
Receipt decoding module, for receiving described packet and decoding, obtains described control parameter;
Preserve module, the described control parameter obtaining for preserving decoding;
Output module, for the periodically output of speed with demand by described control parameter test vector fragment.
Above-mentioned test macro, wherein, also comprises:
Synchronised clock, for the clock signal of the digital to analog converter input homology to be measured to described test motherboard and described test daughter board.
Above-mentioned test macro, wherein, described synchronised clock receives by Serial Peripheral Interface (SPI) the configuration-direct field that described controller sends.
Above-mentioned test macro, wherein, described controller comprises:
Handover module, for dynamic characteristic configuration interface and the static characteristic configuration interface of the output of the type of waveform of switch test vector, excitation and time-out, described digital to analog converter.
Above-mentioned test macro, wherein, described controller also comprises:
Configuration integrate module, for configuring the parameter of described test vector, and then generates required test vector.
Above-mentioned test macro, wherein, described controller also comprises:
Display module, for showing the waveform of described test vector fragment according to the configuration result of the switching result of described handover module and described configuration module.
Above-mentioned test macro, wherein, described controller comprises:
Indicating module, is used to indicate the connection status between operating state and described controller, described test motherboard, described test daughter board and the described analyzer of described controller.
The present invention also provides a kind of controller, and wherein, described controller is used for controlling producing tests the needed control parameter of digital to analog converter to be measured output.
Above-mentioned controller, wherein, described controller comprises:
Configuration integrate module, for the parameter of configuration testing vector, and then generates required test vector;
Handover module, for switching dynamic characteristic configuration interface and the static characteristic configuration interface of the output of waveform, excitation of described test vector and time-out, described digital to analog converter;
Package module: for will be described the control parameter of described configuration module and the generation of described handover module be packaged into any number according to bag before the output of control parameter.
The beneficial effect of technique scheme of the present invention is as follows:
In such scheme, described test macro can rapid configuration test vector, complete the static state of digital to analog converter and the test of frequency domain parameter, improve testing efficiency and reliability, testing cost is low simultaneously, based on good software and hardware architecture, can meet fast the demand such as Function Extension, amendment flexibly, and in the course of work, can monitor the operating state of test macro.
Brief description of the drawings
Fig. 1 is the test system structure schematic diagram of the embodiment of the present invention;
Fig. 2 is the test macro schematic diagram of the embodiment of the present invention;
Fig. 3 is picture and text interactive interface schematic diagram in the embodiment of the present invention;
" producer-consumer " Design Mode schematic diagram that Fig. 4 adopts for picture and text interactive interface in the embodiment of the present invention;
Fig. 5 A is the interlock switch schematic diagram of waveform generator panel in the embodiment of the present invention;
Fig. 5 B is waveform generator main panel schematic diagram in the embodiment of the present invention;
Fig. 5 C realizes the schematic flow sheet that waveform generator switches in the embodiment of the present invention;
Fig. 6 is " the alone family customized event type " schematic diagram defining in the embodiment of the present invention;
Fig. 7 A is data pack protocol schematic diagram in the embodiment of the present invention;
Fig. 7 B is the schematic flow sheet of in the embodiment of the present invention, test vector being cut apart, encapsulate, packed;
Fig. 8 is the hardware platform structural representation of reception, handle packet in the embodiment of the present invention;
Fig. 9 tests the schematic diagram of motherboard to test daughter board transmission test vector in the embodiment of the present invention.
Embodiment
For making the technical problem to be solved in the present invention, technical scheme and advantage clearer, be described in detail below in conjunction with the accompanying drawings and the specific embodiments.
The present invention is directed in existing technology digital to analog converter testing cost high, and tester is difficult to meet the problem of the demand such as Function Extension, amendment flexibly, a kind of test macro of digital to analog converter is provided, as shown in Figure 1, comprising:
Controller, produces the needed control parameter of test digital to analog converter to be measured output for controlling;
Test motherboard, for receiving described control parameter, and reads the test vector fragment in described control parameter according to the control field periodic cycle in described control parameter, the periodically output of speed by described test vector fragment with demand;
Test daughter board, tests digital to analog converter to be measured for the described test vector fragment that receives consecutive periods, makes described digital to analog converter produce simulation output;
Analyze display instrument, for receiving described simulation output, and then analyze the characteristic of described digital to analog converter to be measured and show.
Analysis display instrument in the embodiment of the present invention can be Laboratory Instruments, as oscilloscope, spectrum analyzer etc., can analyze the dynamic characteristic of digital to analog converter to be measured; Also can be the instruments such as universal instrument, Matlab, can analyze the static characteristic of digital to analog converter to be measured, can certainly can reach for other instrument and equipment of technical purpose, differ one for example at this.
Wherein, described controller comprises: package module, and for will be described described control parameter be packaged into any number according to bag before the output of control parameter.
Further, described test motherboard comprises: receipt decoding module, for receiving described packet and decoding, obtains described control parameter; Preserve module, the described control parameter obtaining for preserving decoding; Output module, for the periodically output of speed with demand by described control parameter test vector fragment.
For the phase difference accumulation of avoiding causing because clock is non-homogeneous, the described test macro that the embodiment of the present invention provides, wherein, also comprise: synchronised clock, for the clock signal of the digital to analog converter input homology to be measured to described test motherboard and described test daughter board; Described synchronised clock receives by Serial Peripheral Interface (SPI) (SPI) the configuration-direct field that described controller sends.
Parameter is controlled in configuration for the convenience of the user, the described test macro that the embodiment of the present invention provides, wherein, described controller comprises: handover module, for dynamic characteristic configuration interface and the static characteristic configuration interface of the output of the type of waveform of switch test vector, excitation and time-out, described digital to analog converter; Also comprise: configuration integrate module, for configuring the parameter of described test vector, and then generates required test vector.
For convenience of the test vector of observing after configuration, the described test macro that the embodiment of the present invention provides, wherein, described controller also comprises: display module, and for show the waveform of described test vector fragment according to the configuration result of the switching result of described handover module and described configuration module.
Monitor for the convenience of the user the operating state of test macro, the described test macro that the embodiment of the present invention provides, wherein, described controller comprises: indicating module, is used to indicate the connection status between operating state and described controller, described test motherboard, described test daughter board and the described analyzer of described controller.
Illustrate for example the course of work of described test macro below, as shown in Figures 2 and 3 shown in.
Configuration excitation: first configure required test vector (Wave data), sample rate control field, mode of operation control field, clock configuration-direct etc. by graphical interaction interface (GUI) by described controller, and be packaged into several packets, by the communication interface between computer and hardware platform (as USB) by Packet Generation to hardware platform;
Buffer memory excitation: the test motherboard that can edit gate array (FPGA) based on scene receives packet decoding, the test vector (Wave data) obtaining is by shared multiport memory (two-port RAM) array being stored in FPGA, and various control fields also will be saved in corresponding registers;
Output drive: FPGA control logic will read the test vector fragment being stored in array ram according to the various control fields in register (as sample rate, beginning/time-out, monocycle/multicycle) periodic cycle, and periodically export with the speed of demand, to produce continuous test vector waveform, to impose on the test daughter board that contains digital to analog converter to be measured;
Analysis result: the simulation output of digital to analog converter to be measured is connected to Laboratory Instruments (as oscilloscope, spectrum analyzer etc.), can analyzes and obtain its dynamic characteristic; Utilize the instrument such as universal instrument, Matlab to calculate its static characteristic by analysis meter.
The functional module of described controller is corresponding with image conversion interactive interface, as shown in Figure 3, wherein, in graphical interaction interface, the switching of test vector waveform is provided, test vector parameter configuration, the demonstration directly perceived of test vector waveform (shows with the oscillogram type control Waveform Graph in LabVIEW, the can visually see quantity of waveform shape and data point of user), test vector is saved to file, the switching of excitation output/time-out, the setting of sample rate, static Static characteristic/dynamically the pattern of Dynamic characteristic is switched, the instruction of USB device connection status, the interactive elements such as test platform operating state instruction, also provide for the element such as test vector is automatically upgraded, observed transmission byte number, scan pattern, scan cycle time and step-length arrange.
As shown in Figure 4, adopt " producer-consumer " Design Mode in LabVIEW by the graphical interaction interface entirety of described controller control; Wherein, the dynamic event of for example, dishing out in VI event that " producer " triggers while being cycled to used in real-time detection user with interface alternation (: button click, input data, the operation such as close window) and software execute process (for example: carry out initialization, start waveform generator, refresh testing vector data, to USB device transmission packet), and the data/order of answering is in contrast pressed into message queue, passed to " consumer " circulation by message queue; In the running of " producer " circulation, " consumer " circulates also in executed in parallel, and it is order reading out data/order from message queue, carrys out the operation response corresponding to different data/command execution by conditional branching structure.
As shown in Figure 3, support polytype test vector by the graphical interaction interface of described controller control; Test vector type comprises: sine wave, square wave, double-tone, sawtooth waveforms, swept-frequency signal, amplitude-modulated wave AM, frequency-modulated wave FM, self-defining formula (formula ripple) and file import; The waveform of every type is corresponding a waveform generator independently all, switch to corresponding waveform generator by clicking different buttons, waveform generator can be quantized into a string discrete test vector data point by continuous analog waveform according to configuration parameter; The switching of waveform generator adopts interlock switch (mutual exclusion switch), this switch can utilize a radio button (Radio Button) control to comprise residence in program has the button that waveform generator is corresponding to realize, such design can ensure that synchronization only has at most a button in effective status, while pressing certain button, button in effective status will automatically be upspring and be become invalidly before, and this effect is consistent with the operating experience of true instrument; In the time needing to expand/add new test vector type, only need additionally write a corresponding waveform generator, and in the branched structure relevant to waveform switch, add a branch, without revising original program on a large scale, that is: in the time that needs are expanded new test vector type, only need write respective waveforms generator, and its index be joined in the conditional branching structure of main program.
As shown in Figure 5A, in the graphical interaction interface by described controller control, use interlock switch, conditional branching structure to realize the switching of different test vector types.The test vector that is respectively every type designs an independently waveform generator, as shown in Fig. 3 and Fig. 5 B, in the graphical interfaces of waveform generator, be provided with the input frames such as " amplitude (Amplitude) ", " frequency (Frequency) ", " phase place (Phase) ", " direct current biasing (Offset) ", " sample frequency (SampleRate) ", " sampling number (Samples) ", as the configuration parameter of test vector.Wherein, the frame line of Radio Button is invisible for being set to.All waveform generators also adopt " producer-consumer " Design Mode, detect user's operation and make appropriate response.As shown in Figure 5 C, conditional branching structure wherein can judge and start any waveform generator according to the output valve of interlock switch, when starting new waveform generator, old waveform generator can be removed from sub-panel.In the time that needs add new waveform generator kind, only need in interlock switch, add a new button, in conditional branching structure, add a Ge Xin branch.
As shown in Figure 3, being organized together by the sub-panel technology (SubPanel) in LabVIEW by the main program of the graphical interaction interface of described controller control and various waveform generator (is in graphical interaction interface, sub-panel technology (SubPanel) in use LabVIEW dynamically shows the graphical interfaces of various waveform generators), although they are all an independently program separately, but utilize this technology can make its graphical interfaces according to the stacking demonstration of predetermined relative position relation, the graphical interfaces that is waveform generator will be presented in a certain fixed area (sub-panel) at main interface, minimize to realize interfacial area, operation visualize.While switching generator by clicking the button of different test vector types, old generator panel will be replaced by the up-to-date generator panel of choosing.
In graphical interaction interface by described controller control, use the tag types control (Tab Control) in LabVIEW that the control set for testing digital to analog converter static characteristic, dynamic characteristic is placed on respectively to two Shipping Options Pages (Tab), synchronization only can show the two one of.
In graphical interaction interface by described controller control, the data that " spatially need to share; need in time multiplexing " for some and field (such as the test vector data point, sample rate field, the User Defined event that generate), store with global variable, thus the data of realization/field sharing and the demand of multiple repeated reference between main program and waveform generator.
As shown in Figure 6, in the graphical interaction interface by described controller control, when the scheme of use " alone family customized event " avoids adding multiple User Defined event, necessary " event registration the is quoted handle " control that repeatedly upgrades operates; This scheme only defines a User Defined event (User Event) in whole program, utilize its event data parameter to distinguish the event of different purposes, its data type is one bunch, comprise " event name (EventName) ", " event data (EventData) " two elements, be respectively used to indicate event purposes and carry the necessary data relevant to event.
As shown in Figure 7 A, follow self-defining data pack protocol by the transfer of data between graphical interaction interface and the hardware platform of described controller control, this agreement indicates the form of packet: a data packet length is 512 bytes, wherein front 32 bytes are as packet header, rear 480 bytes are deposited valid data information, in packet header, define the multiple field of data of description bag, mainly contained " bag beginning flag (verification) ", " device type ", " device numbering ", " packet length ", " bag type ", " packet number ", " data point number ", " data point length ", " data encoding format " etc., in graphical interaction interface, the sub-VI that has designed a Packet Generator by name carries out packing operation, one group of continuous test vector point set is by divided, be packaged into transmission successively in some packets, for other instructions, packing/the transmission method of control command is identical therewith, as shown in Figure 7 B, the Wave data being stored in global variable transmits taking data point (16bit word) as the data flow of unit, then divided and shaping, then transmit taking field (480Bytes) as the clip stream of unit, then packed by packetization module Packet Generator, then transmit taking packet (32 byte packet header+480 byte inclusion) as the data packet stream of unit, by usb communication layer, packet is issued to hardware, as shown in Figure 8, in FPGA, corresponding asynchronous first-in first-out storage organization (FIFO) and de-packetizer are designed, the former is for data cached bag, after the complete complete data packet of buffer memory, de-packetizer will be from FIFO read data packet, and carry out and separate package operation according to the data pack protocol of definition, the test vector data and the control command etc. that obtain will be distributed to different late-class circuit modules rightly.
Support multiple interfaces by the physical layer communication between graphical interaction interface and the hardware platform of described controller control, as: USB, serial ports, Ethernet (Ethernet) etc., use corresponding protocol processes chip to complete bottom operation, read-write sequence is dispatched by the inner corresponding functional module of FPGA; Taking USB interface as example, as shown in Figure 8, this programme has used the usb protocol process chip of the FT245RL model in the FT245 series of FTDI company to carry out software and hardware communication, in FPGA, design corresponding functional module (FT245_RW module) and controlled read-write sequence, carry out complete packet of buffer memory with FIFO, and designed parse module packet is carried out to decoded operation.Wherein, usb protocol process chip FT245RL is an independent chip, and FT245_RW(controls read-write sequence module), FIFO_R(cache module), FLOW_CTRL(total control module) and DECODER(parse module) four modules are the module in fpga logic circuit; Between FT245RL and FT245_RW, be connected by some Pin pin, wherein: DATA is data line ports, for transfer of data between the two; RXF is FT245RL chip " read data flag bit ", for informing that FT245_RW read data is ready to; RD is FT245RL chip " read data Enable Pin ", and FT245_RW can start read operation by this enable signal; TXE is that FT245RL chip " is write Data Labels position ", for informing that FT245_RW has carried out the preparation of writing data; WR is that FT245RL chip " is write data enable end ", and FT245_RW can start write operation by this enable signal; In FT245_RW: the EnR being connected with the EnR in FLOW_CTRL and the EnW being connected with the EnW in FLOW_CTRL are respectively total Enable Pin of reading and writing operation, only under the effective prerequisite of EnR, FT245_RW could export effective RD, in like manner, only, under the effective prerequisite of EnW, FT245_RW could export effective WR; DataR and DROK are for the transfer of data between FT245_RW and FIFO_R, and DataR is data line ports, and DROK is " writing data enable end "; In FIFO_R: data[7:0] be connected " write data line end " with DataR, wrreq is connected " writing Enable Pin " with DROK; Q[7:0] be " the read data line end " being connected with the Packet in DECODER, rdreq is " the reading Enable Pin " being connected with the rdreq in DECODER; With the wrusedw[7:0 in FLOW_CTRL] wrusedw[7:0 that is connected] and with rdusedw[9:0 in DECODER] rdusedw[9:0 that is connected] address pointer while representing respectively FIFO to carry out write/read operation; Data[7:0 in DECODER], RAMAddr[10:0] and RAMEn be to late-class circuit and transmit the port of data; Clk in Fig. 8 and rst are input end of clock and reset terminal.
As shown in Figure 9, in this programme, be stored in the two-port RAM array of test motherboard for testing the test vector data flow of digital to analog converter dynamic characteristic, be stored in the single register of test motherboard for the test vector data point (pedestal level) of tested static characteristic; For the former, store a copy of test vector data flow each ram cell mirror image in array, in the time of needs output test vector, control logic (data interlacing logic & data strobe logic) is by the parallel data that read different address place in each RAM, form multidiameter delay data flow, and realize the interweaving of multiplex data stream, frequency multiplication in conjunction with the integrated string of " ping-pong operation " or FPGA pin place transceiver configuration (SerDes structure); For the latter, its implementation is similar, only corresponding test vector (pedestal level) is not to be stored in RAM, but be stored in register, graphical interaction interface sends packet according to the identical time interval to hardware platform by the configuration information of setting according to user, and then upgrades the pedestal level field in single register.
As shown in Figure 9, this programme synchronization only can be carried out the one in dynamic test/static test, interleaved data stream control logic can be according to relevant controlling field, use the corresponding test vector of MUX gating, for the test-types in non-active state, the relative RAM(of reading or read register) operation will be suspended (this design realizes by gated clock).
As shown in Figure 9, this programme uses clock chip to produce two-way homology clock signal, respectively as the clock CLK-Test of test vector output logic and the sampling clock CLK-DAC of digital to analog converter to be measured, with the phase difference accumulation of avoiding introducing because clock is non-homogeneous; The required instruction field of configurable clock generator chip is produced by graphic user interface, is sent to buffer circuit via parse module, finally transfers to clock chip by SPI interface.Wherein, test motherboard transmission test vector to the transmitting portion of testing daughter board is produced by the clock chip AD9516-3 of ADI company with the clock signal that the receiving unit of test daughter board uses.The parallel test vector data point reading in array ram (RAM1, RAM2, RAM3, RAM4) of transmitting portion, and the multichannel data Wei Yi road that interweaves is had to the test and excitation signal of higher rate.Meanwhile, transmitting portion is also used gate logic (MUX) to carry out gating to the static pedestal level of dynamic test vector sum.
For solving the problems of the technologies described above, the embodiment of the present invention also provides a kind of method of testing of digital to analog converter, comprises the steps:
Control and produce the needed control parameter of test digital to analog converter to be measured output;
Receive described control parameter, and read the test vector fragment in described control parameter according to the control field periodic cycle in described control parameter;
Periodically output of speed by described test vector fragment with demand;
The described test vector fragment that receives consecutive periods is tested digital to analog converter to be measured, makes described digital to analog converter produce simulation output;
Receive described simulation output, and then analyze the characteristic of described digital to analog converter to be measured and show.
Wherein, exporting described control parameter also comprises before: described control parameter is packaged into any number according to bag.
Further, reading described test vector fragment also comprises before: receive described packet and decode, obtaining described control parameter; Preserve the described control parameter that decoding obtains.
Wherein, the output logic clock of described test vector fragment and the sampling clock homology of described digital to analog converter to be measured.
Described method of testing testing cost that the embodiment of the present invention provides is low, flexibility ratio is high, can meet the demand such as Function Extension and amendment.
It should be noted that, the described embodiment of realization of above-mentioned test macro is all applicable in the embodiment of this method of testing, also can reach identical technique effect.
For solving the problems of the technologies described above, the embodiment of the present invention also provides a kind of controller, and described controller is used for controlling producing tests the needed control parameter of digital to analog converter to be measured output.
Wherein, described controller comprises: configuration integrate module, for the parameter of configuration testing vector, and then generates required test vector; Handover module, for switching dynamic characteristic configuration interface and the static characteristic configuration interface of the output of waveform, excitation of described test vector and time-out, described digital to analog converter; Package module: for will be described the control parameter of described configuration module and the generation of described handover module be packaged into any number according to bag before the output of control parameter.
The control parameter that the described controller that the embodiment of the present invention provides can rapid configuration be tested digital to analog converter to be measured, improves testing efficiency and reliability, and production cost is low, easy to control, can carry out fast Function Extension.
The above is the preferred embodiment of the present invention; it should be pointed out that for those skilled in the art, do not departing under the prerequisite of principle of the present invention; can also make some improvements and modifications, these improvements and modifications also should be considered as protection scope of the present invention.
Claims (15)
1. a method of testing for digital to analog converter, is characterized in that, comprises the steps:
Control and produce the needed control parameter of test digital to analog converter to be measured output;
Receive described control parameter, and read the test vector fragment in described control parameter according to the control field periodic cycle in described control parameter;
Periodically output of speed by described test vector fragment with demand;
The described test vector fragment that receives consecutive periods is tested digital to analog converter to be measured, makes described digital to analog converter produce simulation output;
Receive described simulation output, and then analyze the characteristic of described digital to analog converter to be measured and show.
2. method of testing according to claim 1, is characterized in that, exports described control parameter and also comprises before:
Described control parameter is packaged into any number according to bag.
3. method of testing according to claim 2, is characterized in that, reads described test vector fragment and also comprises before:
Receive described packet and decode, obtaining described control parameter;
Preserve the described control parameter that decoding obtains.
4. method of testing according to claim 1, is characterized in that, the output logic clock of described test vector fragment and the sampling clock homology of described digital to analog converter to be measured.
5. a test macro for digital to analog converter, is characterized in that, comprising:
Controller, produces the needed control parameter of test digital to analog converter to be measured output for controlling;
Test motherboard, for receiving described control parameter, and reads the test vector fragment in described control parameter according to the control field periodic cycle in described control parameter, the periodically output of speed by described test vector fragment with demand;
Test daughter board, tests digital to analog converter to be measured for the described test vector fragment that receives consecutive periods, makes described digital to analog converter produce simulation output;
Analyze display instrument, for receiving described simulation output, and then analyze the characteristic of described digital to analog converter to be measured and show.
6. test macro according to claim 5, is characterized in that, described controller comprises:
Package module, for will be described be packaged into any number according to bag by described control parameter before the output of control parameter.
7. test macro according to claim 6, is characterized in that, described test motherboard comprises:
Receipt decoding module, for receiving described packet and decoding, obtains described control parameter;
Preserve module, the described control parameter obtaining for preserving decoding;
Output module, for the periodically output of speed with demand by described control parameter test vector fragment.
8. test macro according to claim 5, is characterized in that, also comprises:
Synchronised clock, for the clock signal of the digital to analog converter input homology to be measured to described test motherboard and described test daughter board.
9. test macro according to claim 8, is characterized in that, described synchronised clock receives by Serial Peripheral Interface (SPI) the configuration-direct field that described controller sends.
10. test macro according to claim 5, is characterized in that, described controller comprises:
Handover module, for dynamic characteristic configuration interface and the static characteristic configuration interface of the output of the type of waveform of switch test vector, excitation and time-out, described digital to analog converter.
11. test macros according to claim 10, is characterized in that, described controller also comprises:
Configuration integrate module, for configuring the parameter of described test vector, and then generates required test vector.
12. test macros according to claim 11, is characterized in that, described controller also comprises:
Display module, for showing the waveform of described test vector fragment according to the configuration result of the switching result of described handover module and described configuration module.
13. test macros according to claim 5, is characterized in that, described controller comprises:
Indicating module, is used to indicate the connection status between operating state and described controller, described test motherboard, described test daughter board and the described analyzer of described controller.
14. 1 kinds of controllers, is characterized in that, described controller is used for controlling producing tests the needed control parameter of digital to analog converter to be measured output.
15. controllers according to claim 14, is characterized in that, described controller comprises:
Configuration integrate module, for the parameter of configuration testing vector, and then generates required test vector;
Handover module, for switching dynamic characteristic configuration interface and the static characteristic configuration interface of the output of waveform, excitation of described test vector and time-out, described digital to analog converter;
Package module: for will be described the control parameter of described configuration module and the generation of described handover module be packaged into any number according to bag before the output of control parameter.
Priority Applications (1)
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| CN107786204A (en) * | 2016-08-25 | 2018-03-09 | 成都锐成芯微科技股份有限公司 | Digital analog converter parameter test system and method |
| CN109143034A (en) * | 2018-09-10 | 2019-01-04 | 上海华虹集成电路有限责任公司 | Chip ADC automatic performance test system and method |
| CN109582606A (en) * | 2018-11-19 | 2019-04-05 | 中电科仪器仪表有限公司 | A kind of block read method improving spectrum analyzer scanning speed |
| CN111262584A (en) * | 2020-01-15 | 2020-06-09 | 济南浪潮高新科技投资发展有限公司 | Method and system for automatically correcting unstable DAC channel communication |
| CN111596200A (en) * | 2020-05-25 | 2020-08-28 | 上海岱矽集成电路有限公司 | Integrated circuit tester |
| CN112579495A (en) * | 2020-12-25 | 2021-03-30 | 上海东软载波微电子有限公司 | GPIO controller |
| CN112903613A (en) * | 2021-02-24 | 2021-06-04 | 南昌大学 | Labview-based transient absorption spectrum control system design method |
| CN113433450A (en) * | 2021-08-27 | 2021-09-24 | 南京宏泰半导体科技有限公司 | Mixed signal testing device based on graphical control |
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| CN107786204A (en) * | 2016-08-25 | 2018-03-09 | 成都锐成芯微科技股份有限公司 | Digital analog converter parameter test system and method |
| CN109143034A (en) * | 2018-09-10 | 2019-01-04 | 上海华虹集成电路有限责任公司 | Chip ADC automatic performance test system and method |
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| CN111262584B (en) * | 2020-01-15 | 2024-03-22 | 山东浪潮科学研究院有限公司 | Method and system for automatically correcting communication instability of DAC channel |
| CN111596200A (en) * | 2020-05-25 | 2020-08-28 | 上海岱矽集成电路有限公司 | Integrated circuit tester |
| CN112579495A (en) * | 2020-12-25 | 2021-03-30 | 上海东软载波微电子有限公司 | GPIO controller |
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| CN112903613A (en) * | 2021-02-24 | 2021-06-04 | 南昌大学 | Labview-based transient absorption spectrum control system design method |
| CN113533936A (en) * | 2021-07-13 | 2021-10-22 | 上海矽昌微电子有限公司 | Chip scan chain test method and system |
| CN113433450A (en) * | 2021-08-27 | 2021-09-24 | 南京宏泰半导体科技有限公司 | Mixed signal testing device based on graphical control |
| WO2023024531A1 (en) * | 2021-08-27 | 2023-03-02 | 南京宏泰半导体科技有限公司 | Mixed signal testing apparatus based on graphical control |
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