CN107014419B - Quartz vibrating beam resonant sensor test system based on FPGA + SOPC - Google Patents

Quartz vibrating beam resonant sensor test system based on FPGA + SOPC Download PDF

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CN107014419B
CN107014419B CN201710179010.XA CN201710179010A CN107014419B CN 107014419 B CN107014419 B CN 107014419B CN 201710179010 A CN201710179010 A CN 201710179010A CN 107014419 B CN107014419 B CN 107014419B
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frequency
square wave
measurement
temperature
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CN107014419A (en
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赵玉龙
孙登强
李波
李村
韩超
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Shaanxi Lin Tak inertia Electric Co.,Ltd.
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Xian Jiaotong University
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    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01D—MEASURING NOT SPECIALLY ADAPTED FOR A SPECIFIC VARIABLE; ARRANGEMENTS FOR MEASURING TWO OR MORE VARIABLES NOT COVERED IN A SINGLE OTHER SUBCLASS; TARIFF METERING APPARATUS; MEASURING OR TESTING NOT OTHERWISE PROVIDED FOR
    • G01D18/00—Testing or calibrating apparatus or arrangements provided for in groups G01D1/00 - G01D15/00
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01K—MEASURING TEMPERATURE; MEASURING QUANTITY OF HEAT; THERMALLY-SENSITIVE ELEMENTS NOT OTHERWISE PROVIDED FOR
    • G01K13/00—Thermometers specially adapted for specific purposes

Abstract

According to the quartz vibrating beam resonant sensor testing system based on FPGA + SOPC, a two-way square wave signal to be tested output by a quartz vibrating beam resonant sensor passes through a square wave shaping module to obtain a standard square wave signal to be tested, the standard square wave signal to be tested is input into an equal-precision frequency measuring module in an FPGA unit, and rising edge counting of a reference signal and a signal to be tested is completed; meanwhile, the output of the temperature sensor is communicated with the temperature measurement module in real time through an IIC bus interface, the frequency measurement and temperature measurement circuit based on Verilog HDL is packaged into a self-defined IP core through an SOPC, an SOPC module is further established, and functions of floating point calculation, LCD display, serial port transmission and the like of frequency values and temperature values are realized through an NIOSII controller.

Description

Quartz vibrating beam resonant sensor test system based on FPGA + SOPC
Technical Field
The invention relates to the technical field of testing of quartz vibrating beam resonant sensors, in particular to a quartz vibrating beam resonant sensor testing system based on FPGA and SOPC.
Background
The quartz vibration beam resonant sensor is a high-precision sensor based on the force frequency characteristic between the resonance frequency and the internal axial stress of a piezoelectric quartz crystal vibration beam resonator, is mainly applied to accelerometers, pressure sensors, temperature and humidity sensors and the like, and has the main advantages of easiness in batch production, easiness in excitation and detection, high quality factor, high precision and digital square wave output. The square wave with the output frequency of about 40kHz is a quasi-digital signal, so that the requirement of realizing high-precision, continuous and quick measurement on square wave frequency signals is provided in the test of the quartz vibrating beam resonant sensor. In addition, because the sensitivity of the quartz vibration beam resonator to the temperature is high, most quartz vibration beam resonant sensors are arranged by adopting a differential structure to eliminate the interference of conjugate error factors such as the temperature, and the like, and meanwhile, a temperature monitoring module is required to be integrated in a test system of the sensor to establish a temperature model output by the sensor, so that the precision and the stability of the output of the sensor are improved, and therefore, the requirements of frequency two-way synchronous acquisition and integration easy to expand are provided for the test system.
At present, instruments for testing resonant sensors in laboratories mainly comprise oscilloscopes, desk multimeters, frequency counters and the like. Although the oscilloscope can display the waveform of the signal to be measured, the frequency measurement principle of the oscilloscope is that the frequency value is obtained through the period of the signal in the display panel area, so that the oscilloscope has poor frequency measurement precision which is lower than 10-2An order of magnitude; likewise, the frequency measurement precision of the universal meter can only reach 10-4The magnitude of order can not meet the precision requirement of the quartz vibrating beam resonant sensor; the frequency counter is a special frequency measuring instrument, which measures the frequency according to the number of rising edges of digital signals in the time of gate control signals, the frequency measuring precision is very high, and the relative error is generally less than 10-7However, the three instruments cannot realize two-way synchronous measurement and data recording, and the other way of measurement needs manual switching, so that the test requirements of the differential quartz vibrating beam resonant sensor cannot be met.
The testing equipment has the advantages of high price, large volume and mass, poor portability and multiple redundancy functions. In the development of a special test system of a quartz vibrating beam resonant sensor, the traditional design mostly adopts the schemes of a single chip microcomputer, a CPLD, an FPGA + MCU and the like to construct a small, simple and pure frequency test system, but the problems of low clock frequency of the single chip microcomputer, poor floating point operation capability of the CPLD and the FPGA, generally incapability of embedding a temperature real-time monitoring module, relatively complex circuit design of the FPGA + MCU scheme, and inconvenience for reducing power consumption, volume, development cost and the like cannot be avoided.
Disclosure of Invention
In order to overcome the defects of the prior art, the invention aims to provide the quartz vibrating beam resonant sensor testing system based on the FPGA and the SOPC, which not only can realize the synchronous, high-precision, continuous and quick acquisition of two paths of frequency outputs of the quartz vibrating beam resonant sensor, but also integrates the monitoring function of the ambient temperature, and has the characteristics of small volume, low cost, low power consumption and strong expansion capability.
In order to achieve the purpose, the invention adopts the technical scheme that:
the quartz vibrating beam resonant sensor testing system based on FPGA + SOPC comprises a quartz vibrating beam resonant sensor, wherein a first output of the quartz vibrating beam resonant sensor is connected with a data input end of a square wave shaping module I, a second output of the quartz vibrating beam resonant sensor is connected with a data input end of a square wave shaping module II, clock input ends of the square wave shaping module I and the square wave shaping module II are connected with a first clock output end clk I of a PLL frequency doubling module, a data output end of the square wave shaping module I is connected with a first frequency data input end of a self-defined frequency and temperature measurement IP core based on Verilog HDL, a data output end of the square wave shaping module II is connected with a second frequency data input end of the self-defined frequency and temperature measurement IP core based on Verilog HDL, and a temperature data end of the self-defined frequency and temperature measurement IP core based on Verilog HDL is bidirectionally connected with a temperature sensor through an IIC bus, inside the SOPC, the user-defined frequency and temperature measuring IP core, the NiosII controller, the UART core, the PIO core, the EPCS controller and the SDRAM controller based on the Verilog HDL realize bidirectional connection through an Avalon bus, the data output end of the UART core is connected with an upper computer in a bidirectional way, the data output end of the PIO core is connected with an LCD display screen, the data output end of the EPCS controller is connected with a FLASH memory in a bidirectional way, and the data output end of the SDRAM controller is connected with an SDRAM memory in a bidirectional way;
the clock input end of the NiosII controller is connected with the second clock output end clk II of the PLL frequency doubling module, the clock input end of the SDRAM controller is connected with the third clock output end clk III of the PLL frequency doubling module, and the clock input end of the PLL frequency doubling module is connected with the clock crystal oscillator.
The square wave shaping module I and the square wave shaping module II are built through an FPGA internal digital electronic device, a square wave signal to be detected is connected with the input end of a buffer, the output end of the buffer is connected with the data input end of a D trigger I, the output end of the D trigger I is divided into two paths of signals, one path of signal is connected with an AND gate data input end A after passing through a NOT gate, the other path of signal is connected with a data input end of the D trigger II, the clock input ends of the D trigger I and the D trigger II are connected with a first standard clock output end clk I of a PLL frequency doubling module, the data output end of the D trigger II is connected with an AND gate data input end B, and a signal output by an AND gate.
The self-defined frequency and temperature measurement IP core based on the Verilog HDL comprises two modules of frequency measurement and temperature measurement; the frequency measurement module adopts a two-path equal-precision frequency measurement principle, a preset gating signal start0 generated by frequency multiplication is a square wave signal with lower frequency, and when the preset gating signal passes through a D trigger taking a standard square wave signal tclk to be measured as a clock signal, actual gating signals synchronous with the rising edge of the standard square wave signal to be measured can be generated and are respectively starta and startb, and the periods are respectively tstart a and tstart b; the actual gating signals are respectively used as enabling signals of a signal counter to be detected and a reference signal counter, so that Ttstarta and Ttstartb are respectively integral multiples of the period of the standard square wave signal to be detected;
in order to ensure the synchronism of the acquisition of the output frequency signals of the two quartz vibrating beam resonant sensors, a total gating signal gate is introduced, wherein the gate signal is the OR operation of two actual gating signals starta and startb and represents the actual measurement interval of the two signals; when the two paths of measurement are finished, the gate signal is changed into low level, the counting process is finished, then an effective latch mark signal latch _ flag is generated when the next rising edge of the reference clock signal arrives, and the latch mark signal maintains a reference signal period; when the rising edge of the latch flag signal latch _ flag comes, the count values of the four counters are latched; when the falling edge of the latch _ flag comes, the system generates an interrupt flag signal interrupt, then the NiosII controller processes the interrupt, the value of each counter is read, a clear signal is generated to clear the interrupt and each data register, and a measurement process is finished;
the temperature measurement module adopts the same reference clock signal as the frequency measurement module, an IIC communication protocol is realized through a finite state machine, the reading of the real-time temperature value of the internal register of the temperature sensor is completed, and the synchronization of frequency measurement and temperature measurement is ensured by the characteristic of parallel execution of FPGA instructions;
in order to realize the communication between the user-defined frequency and temperature measurement IP core based on the Verilog HDL and the NiosII controller, a chip selection signal and an address signal are added into the user-defined frequency and temperature measurement IP core based on the Verilog HDL for carrying out corresponding address decoding, so that user logic can be correctly connected to an Avalon bus.
The SOPC realizes software programming control in FPGA based on hardware language, and the specific program flow is as follows: after the system starts to operate, counting and communication are started according to a designed time sequence based on a user-defined frequency and temperature measurement IP core of the Verilog HDL, and after the counting and communication are completed, an interrupt signal is sent to the NiosII controller; when the NiosII controller enters an interrupt processing program, reading the numerical values in each register, setting the Flag signal Flag to be 1, emptying the interrupt signal and the data register, and ending the interrupt processing process; after detecting that the state of Flag is 1, the main program firstly sets Flag to 0, and sequentially carries out the processes of frequency, floating point calculation of temperature value, LCD display and serial port data transmission; at this point, a test procedure is completed, waiting for the next interrupt signal to arrive.
The test method of the quartz vibrating beam resonant sensor test system based on FPGA + SOPC comprises the following steps:
(1) directly inputting an external clock signal output by a clock crystal oscillator, two paths of square wave signals output by a quartz vibrating beam resonant type sensor and a real-time environment temperature signal output by a temperature sensor into an FPGA chip;
(2) after an external clock signal passes through the PLL frequency doubling module, a high-frequency clock signal is provided for the square wave shaping module I and the square wave shaping module II, and the two paths of square wave signals input by the quartz vibrating beam resonant sensor are standardized;
(3) on one hand, the self-defined frequency and temperature measurement IP core based on the Verilog HDL realizes counting and recording of rising edges of two paths of standard square waves to be measured and reference clock signals in an actual gating signal through a two-path equal-precision frequency measurement method, and simultaneously finishes reading and recording of real-time temperature values of an internal register of a temperature sensor through an IIC bus communication protocol;
(4) the NiosII controller reads the internal data of the user-defined frequency measurement and temperature measurement IP core based on the Verilog HDL through an Avalon bus to complete the floating point calculation of two paths of frequency values and real-time temperature values;
(5) the NiosII controller controls the UART and the PIO kernel through software driving to realize interaction with an upper computer and control of an LCD display screen, and display and record of frequency data and temperature data are completed.
The invention has the beneficial effects that: the advantages of parallel execution of FPGA instructions and excellence in sequential circuit processing are combined with the advantages of control of SOPC pipeline and excellence in complex calculation. Meanwhile, on one FPGA chip, the synchronous, high-precision, continuous and quick acquisition of double-channel frequency signals and the synchronous acquisition of real-time temperature signals are realized, the functions of real-time LCD display and serial port communication are integrated, more importantly, the system integrates an NIOSII processor, the system has the capability of realizing the calculation of complex numerical values such as floating point operation and the like, the real-time realization of a sensor calibration algorithm and a compensation algorithm is facilitated, and the precision and the stability of the output of the sensor system are improved. In addition, the system also has the advantages of small volume, low cost, low power consumption, high integration degree and the like.
Drawings
FIG. 1 is a block diagram of a test system according to the present invention.
Fig. 2 is a circuit diagram of a square wave shaping module.
Fig. 3 is a timing diagram of the two-way equal-precision frequency measurement principle.
Fig. 4 is a flowchart of the SOPC software program.
Detailed Description
The present invention will be further described with reference to the following drawings and examples, which include, but are not limited to, the following examples.
As shown in figure 1, the quartz vibration beam resonant sensor test system based on FPGA + SOPC comprises a quartz vibration beam resonant sensor, wherein a first output of the quartz vibration beam resonant sensor is connected with a data input end of a square wave shaping module I, a second output of the quartz vibration beam resonant sensor is connected with a data input end of a square wave shaping module II, clock input ends of the square wave shaping module I and the square wave shaping module II are connected with a first clock output end clk I of a PLL frequency doubling module, a data output end of the square wave shaping module I is connected with a first frequency data input end of a self-defined frequency and temperature measurement IP core based on Verilog HDL, a data output end of the square wave shaping module II is connected with a second frequency data input end of the self-defined frequency and temperature measurement IP core based on Verilog HDL, and a temperature data end of the self-defined frequency and temperature measurement IP core based on Verilog HDL is bidirectionally connected with a temperature sensor through an IIC bus, inside the SOPC, the user-defined frequency and temperature measuring IP core, the NiosII controller, the UART core, the PIO core, the EPCS controller and the SDRAM controller based on the Verilog HDL realize bidirectional connection through an Avalon bus, the data output end of the UART core is connected with an upper computer in a bidirectional way, the data output end of the PIO core is connected with an LCD display screen, the data output end of the EPCS controller is connected with a FLASH memory in a bidirectional way, and the data output end of the SDRAM controller is connected with an SDRAM memory in a bidirectional way;
the clock input end of the NiosII controller is connected with the second clock output end clk II of the PLL frequency doubling module, the clock input end of the SDRAM controller is connected with the third clock output end clk III of the PLL frequency doubling module, and the clock input end of the PLL frequency doubling module is connected with the clock crystal oscillator.
The frequency of two paths of square wave signals output by the quartz vibrating beam resonant sensor is 30 kHz-50 kHz, so that each counter and register in the system select 32 bits; an FPGA chip with the model number of EP4CE15F17C8, a 64Mbit serial FLASH memory, a 256Mbit SDRAM memory, an RS232 serial port, a 480 × 320 resolution color dot matrix liquid crystal display and a 50MHz external clock are selected, and an external power supply chip, a reset chip configuration circuit and the like are also arranged to complete the minimum FPGA system design.
The clock crystal oscillator adopts a 50MHz crystal oscillator, and the PLL frequency doubling module doubles the frequency of a 50MHz external clock signal into three paths: clk I, at a frequency of 200MHz, is the clock signal provided to the square wave shaping module; clk II, at 100MHz, is the clock supplied to the NiosII controller; clk III, at 100MHz, is the clock signal provided to the SDRAM controller.
The square wave shaping module I and the square wave shaping module II are built through an FPGA internal digital electronic device, a circuit is shown in figure 2, a square wave signal to be detected is connected with an input end of a buffer, an output end of the buffer is connected with a data input end of a D trigger I, an output end of the D trigger I is divided into two paths of signals, one path of signals passes through a NOT gate and then is connected with a data input end A of an AND gate, the other path of signals passes through a data input end of the D trigger II and is connected with a data input end of the D trigger II, clock input ends of the D trigger I and the D trigger II are both connected with a first standard clock output end clk I of a PLL frequency doubling module, a data output end of the D trigger II is connected with a data input end B of the AND gate, a signal output by the AND gate is.
The self-defined frequency and temperature measurement IP core based on the Verilog HDL comprises two modules of frequency measurement and temperature measurement; the frequency measurement module adopts a two-way equal-precision frequency measurement principle, as shown in fig. 3, fig. 3 is a signal timing diagram of two-way equal-precision frequency measurement, a preset gating signal start0 is a square wave signal with lower frequency and 0.5 duty ratio, the period of the square wave signal is 20ms, the high level time is 10ms, when the preset gating signal passes through a D trigger taking a to-be-measured signal tclk as a clock, actual gating signals synchronous with the rising edge of the to-be-measured signal can be generated, and are respectively starta and startb, and the periods are respectively tstart a and tstart b; the actual gating signals are respectively used as enabling signals of the signal counter to be measured and the reference signal counter, so that Ttstarta and Ttstartb are respectively integral multiples of the period of the signal to be measured, and the counter is guaranteed to count the signal to be measured without errors.
In order to ensure the synchronism of the acquisition of the output frequency signals of the two quartz vibrating beam resonant sensors, a total gate control signal gate is introduced, the gate signal is the OR operation of two actual gate control signals, and the gate signal represents the actual measurement interval of the two signals; when the two paths of measurement are finished, the gate signal is changed into low level, the counting process is finished, then an effective latch mark signal latch _ flag is generated when the next rising edge of the reference digital signal arrives, and the latch mark signal maintains a reference signal period; when the rising edge of the latch flag signal latch _ flag comes, the count values of the four counters are latched; when the falling edge of the latch _ flag comes, the system generates an interrupt flag signal interrupt, then the NiosII controller processes the interrupt, the value of each counter is read, a clear signal is generated to clear the interrupt and each data register, and a measurement process is finished; therefore, the measurement and transmission of the two signals in the total gating time are synchronous, and the next frequency measurement process is started when the next square wave period of the gating signal is preset, so that the continuity of frequency measurement is ensured.
The temperature measurement module adopts the same reference clock signal as the frequency measurement module, selects a digital temperature sensor with an IIC data interface with the model number of LM75A, and reads the real-time temperature value of the internal register of LM75A by compiling a Verilog HDL digital circuit of a finite state machine with the starting, responding, data reading and writing and termination states, and the synchronization of frequency measurement and temperature measurement is ensured by the parallel execution characteristic of the FPGA instruction.
Through custom module configuration navigation provided by SOPC Builder software, a written frequency measurement and temperature measurement Verilog HDL program file is added into a custom module, meanwhile, communication between a custom frequency measurement and temperature measurement IP core based on Verilog HDL and a NiosII controller is realized, a chip selection signal and an address signal are added into the custom frequency measurement and temperature measurement IP core based on Verilog HDL, corresponding address decoding is carried out, user logic can be correctly connected to an Avalon bus, then a top file is written according to a general interface, and finally analysis and compiling are carried out.
The hardware of the SOPC is configured in SOPC Builder software and comprises self-defined frequency and temperature measuring IP cores, a NiosII controller, an SDRAM controller, an EPCS controller, a UART controller, a PIO kernel, a JTAGUART, a System ID and other IP cores, wherein all the IP cores are interconnected and communicated through an Avalon bus, and all the IP cores automatically allocate base addresses and interrupt numbers and then compile.
The FPGA top-level module is configured in Quartus II software, a PLL frequency doubling module, a square wave shaping module and an instantiated SOPC module are connected according to an electrical relation, pin distribution is carried out, compiling and synthesis are carried out after the pin distribution is finished, sof type files are generated, hardware logic is downloaded into an FPGA chip through a JTAG UART interface, and 4307 logic units are occupied totally and occupy 28% of the total logic units of the FPGA chip in view of compiling results, so that the FPGA chip still has great expandability.
The software design of the SOPC is completed in NiosII IDE software, the NiosII IDE software supports C language programming and can generate a hardware abstract layer and a system head file according to a hardware configuration file of the SOPC, the specific program flow is shown in figure 4, after the system starts to operate, a frequency and temperature measurement IP core starts to count and communicate according to a designed time sequence, and after the system starts to operate, an interrupt signal is sent to a NiosII controller; when the NiosII controller enters an interrupt processing program, reading the numerical values in each register, setting the Flag signal Flag to be 1, emptying the interrupt signal and the data register, and ending the interrupt processing process; after the main program detects that the state of the Flag is 1, firstly, the Flag is set to be 0, and the processes of frequency, floating point calculation of temperature values, LCD display and serial port data sending are sequentially carried out. At this point, a test procedure is completed, waiting for the next interrupt signal to arrive.
The technical indexes of the embodiment are as follows:
● sampling range: two-way, synchronous and continuous, 1 kHz-50 kHz
● sampling frequency: 1 Hz-5000 Hz
● clock frequency: 100MHz
● frequency measurement accuracy: less than or equal to 10-6(sampling frequency 50Hz)
● operating voltage: 5 Vdc.
A quartz vibrating beam resonant sensor testing method based on FPGA + SOPC comprises the following steps:
(1) directly inputting an external clock signal output by a clock crystal oscillator, two paths of square wave signals output by a quartz vibrating beam resonant type sensor and a real-time environment temperature signal output by a temperature sensor into an FPGA chip;
(2) after an external clock signal passes through the PLL frequency doubling module, a high-frequency clock signal is provided for the square wave shaping module I and the square wave shaping module II, and the two paths of square wave signals input by the quartz vibrating beam resonant sensor are standardized;
(3) on one hand, the self-defined frequency and temperature measurement IP core based on the Verilog HDL realizes counting and recording of rising edges of two paths of standard square waves to be measured and reference clock signals in an actual gating signal through a two-path equal-precision frequency measurement method, and simultaneously finishes reading and recording of real-time temperature values of an internal register of a temperature sensor through an IIC bus communication protocol;
(4) the NiosII controller reads the internal data of the user-defined frequency measurement and temperature measurement IP core based on the Verilog HDL through an Avalon bus to complete the floating point calculation of two paths of frequency values and real-time temperature values;
(5) the NiosII controller controls the UART and the PIO kernel through software driving to realize interaction with an upper computer and control of an LCD display screen, and display and record of frequency data and temperature data are completed.

Claims (3)

1. Quartzy beam resonant mode sensor test system that shakes based on FPGA + SOPC shakes, shakes the beam resonant mode sensor including quartzy, its characterized in that: the first output of the quartz vibrating beam resonant sensor is connected with the data input end of a square wave shaping module I, the second output of the quartz vibrating beam resonant sensor is connected with the data input end of a square wave shaping module II, the clock input ends of the square wave shaping module I and the square wave shaping module II are connected with the first clock output end clk I of a PLL frequency doubling module, the data output end of the square wave shaping module I is connected with the first frequency data input end of a user-defined frequency and temperature measurement IP core based on Verilog HDL, the data output end of the square wave shaping module II is connected with the second frequency data input end of the user-defined frequency and temperature measurement IP core based on Verilog HDL, the temperature data end of the user-defined frequency and temperature measurement IP core based on Verilog HDL is bidirectionally connected with a UART (Universal asynchronous receiver) temperature sensor through an IIC (inter-integrated Circuit) bus, and in an SOPC (System on Verilog HDL), the user-defined frequency and temperature measurement IP core based on, The EPCS controller and the SDRAM controller are in bidirectional connection through an Avalon bus, a data output end of a UART core is in bidirectional connection with an upper computer, a data output end of a PIO core is connected with an LCD display screen, a data output end of the EPCS controller is in bidirectional connection with a FLASH memory, and a data output end of the SDRAM controller is in bidirectional connection with an SDRAM memory;
the clock input end of the NiosII controller is connected with a second clock output end clk II of the PLL frequency doubling module, the clock input end of the SDRAM controller is connected with a third clock output end clk III of the PLL frequency doubling module, and the clock input end of the PLL frequency doubling module is connected with a clock crystal oscillator;
the self-defined frequency and temperature measurement IP core based on the Verilog HDL comprises two modules of frequency measurement and temperature measurement; the frequency measurement module adopts a two-path equal-precision frequency measurement principle, a preset gating signal start0 generated by frequency multiplication is a square wave signal with lower frequency, and when the preset gating signal passes through a D trigger taking a standard square wave signal tclk to be measured as a clock signal, actual gating signals synchronous with the rising edge of the standard square wave signal to be measured can be generated and are respectively starta and startb, and the periods are respectively tstart a and tstart b; the actual gating signals are respectively used as enabling signals of a signal counter to be detected and a reference signal counter, so that Ttstarta and Ttstartb are respectively integral multiples of the period of the standard square wave signal to be detected;
in order to ensure the synchronism of the acquisition of the output frequency signals of the two quartz vibrating beam resonant sensors, a total gating signal gate is introduced, wherein the gate signal is the OR operation of two actual gating signals starta and startb and represents the actual measurement interval of the two signals; when the two paths of measurement are finished, the gate signal is changed into low level, the counting process is finished, then an effective latch mark signal latch _ flag is generated when the next rising edge of the reference clock signal arrives, and the latch mark signal maintains a reference signal period; when the rising edge of the latch flag signal latch _ flag comes, the count values of the four counters are latched; when the falling edge of the latch _ flag comes, the system generates an interrupt flag signal interrupt, then the NiosII controller processes the interrupt, the value of each counter is read, a clear signal is generated to clear the interrupt and each data register, and a measurement process is finished;
the temperature measurement module adopts the same reference clock signal as the frequency measurement module, an IIC communication protocol is realized through a finite state machine, the reading of the real-time temperature value of the internal register of the temperature sensor is completed, and the synchronization of frequency measurement and temperature measurement is ensured by the characteristic of parallel execution of FPGA instructions;
in order to realize the communication between the user-defined frequency and temperature measurement IP core based on the Verilog HDL and the NiosII controller, a chip selection signal and an address signal are added into the user-defined frequency and temperature measurement IP core based on the Verilog HDL for carrying out corresponding address decoding, so that user logic can be correctly connected to an Avalon bus;
the SOPC realizes software programming control in FPGA based on hardware language, and the specific program flow is as follows: after the system starts to operate, counting and communication are started according to a designed time sequence based on a user-defined frequency and temperature measurement IP core of the Verilog HDL, and after the counting and communication are completed, an interrupt signal is sent to the NiosII controller; when the NiosII controller enters an interrupt processing program, reading the numerical values in each register, setting the Flag signal Flag to be 1, emptying the interrupt signal and the data register, and ending the interrupt processing process; after detecting that the state of Flag is 1, the main program firstly sets Flag to 0, and sequentially carries out the processes of frequency, floating point calculation of temperature value, LCD display and serial port data transmission; at this point, a test procedure is completed, waiting for the next interrupt signal to arrive.
2. The FPGA + SOPC-based quartz vibrating beam resonant sensor test system as claimed in claim 1, wherein: the square wave shaping module I and the square wave shaping module II are built through an FPGA internal digital electronic device, a square wave signal to be detected is connected with the input end of a buffer, the output end of the buffer is connected with the data input end of a D trigger I, the output end of the D trigger I is divided into two paths of signals, one path of signal is connected with an AND gate data input end A after passing through a NOT gate, the other path of signal is connected with a data input end of the D trigger II, the clock input ends of the D trigger I and the D trigger II are connected with a first standard clock output end clk I of a PLL frequency doubling module, the data output end of the D trigger II is connected with an AND gate data input end B, and a signal output by an AND gate.
3. The test method of the quartz vibrating beam resonant sensor test system based on FPGA + SOPC as claimed in claim 1, characterized by comprising the following steps:
(1) directly inputting an external clock signal output by a clock crystal oscillator, two paths of square wave signals output by a quartz vibrating beam resonant type sensor and a real-time environment temperature signal output by a temperature sensor into an FPGA chip;
(2) after an external clock signal passes through the PLL frequency doubling module, a high-frequency clock signal is provided for the square wave shaping module I and the square wave shaping module II, and the two paths of square wave signals input by the quartz vibrating beam resonant sensor are standardized;
(3) on one hand, the self-defined frequency and temperature measurement IP core based on the Verilog HDL realizes counting and recording of rising edges of two paths of standard square waves to be measured and reference clock signals in an actual gating signal through a two-path equal-precision frequency measurement method, and simultaneously finishes reading and recording of real-time temperature values of an internal register of a temperature sensor through an IIC bus communication protocol;
(4) the NiosII controller reads the internal data of the user-defined frequency measurement and temperature measurement IP core based on the Verilog HDL through an Avalon bus to complete the floating point calculation of two paths of frequency values and real-time temperature values;
(5) the NiosII controller controls the UART and the PIO kernel through software driving to realize interaction with an upper computer and control of an LCD display screen, and display and record of frequency data and temperature data are completed.
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