CN109460382A - A kind of machine carried memory read-write equipment based on SOPC technology - Google Patents
A kind of machine carried memory read-write equipment based on SOPC technology Download PDFInfo
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- CN109460382A CN109460382A CN201811037894.6A CN201811037894A CN109460382A CN 109460382 A CN109460382 A CN 109460382A CN 201811037894 A CN201811037894 A CN 201811037894A CN 109460382 A CN109460382 A CN 109460382A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/76—Architectures of general purpose stored program computers
- G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
- G06F15/7807—System on chip, i.e. computer system on a single chip; System in package, i.e. computer system on one or more chips in a single package
- G06F15/781—On-chip cache; Off-chip memory
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/76—Architectures of general purpose stored program computers
- G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
- G06F15/7867—Architectures of general purpose stored program computers comprising a single central processing unit with reconfigurable architecture
Abstract
The present invention relates to a kind of machine carried memory read-write equipments based on SOPC technology, including building minimum system by the master controller of core of FPGA, using CPLD chip as the logic decoding circuit of core, control connection of the relay array completion to the signal of memory under test port, voltage, ground, FPGA receives the reading and writing data instruction and data file of host computer transmission using serial port circuit and host computer communication, is programmed to being customized of slave computer software using SOPC technology to meet the read-write requirement of different memory.Generalization of the present invention and high degree of automation, need to only change software and the configuration of the read-write to most memories can be completed by not having to change hardware circuit, at low cost, portable good, applied widely.
Description
Technical field
The present invention relates to memory area, specifically a kind of machine carried memory read-write equipment based on SOPC technology.
Background technique
Machine carried memory is many kinds of, because the common programmable device of its particularity is unable to satisfy its read-write operation demand, often
Need the storage read wirte device of other design specialized that could complete the operation to it." observation and control technology " the 32nd published in 2013
The 473-475,480 pages of supplementary issue of volume discloses a kind of grinding for private memory read-write equipment repaired applied to aircraft electrical plate
System, this method include using C8051F040 single-chip microcontroller as control core, are bottom with Read-write Catrol box using all-in-one machine as host computer
Machine, and realize that Read-write Catrol and data are shown using serial ports as communication mode.The device may be implemented to a variety of machine carried memories
Read-write operation, disadvantage is due to function of the MCU and limited capacity, so the scalability of objective chip is not high, can accommodate operation core
The value volume and range of product of piece is limited, and the device can not be operated effectively very fast mainly for slower old-fashioned memory device is read and write
The new-type stored on-board device of read or write speed.For another example Chinese patent 201620658664 (publication date is on March 8th, 2017) is open
A kind of modularization machine carried memory read-write equipment, the device include generating read-write sequence, Ke Yigeng by control core of FPGA
Operation of the fixture completion to different components is changed, and read or write speed is very fast；The disadvantage is that SOPC technology is not used, needed when replacing device
Change pin configuration manually, the type for accommodating memory are limited etc..
Summary of the invention
Technical problem to be solved by the present invention lies in propose a kind of machine carried memory read-write dress based on SOPC technology
It sets, the read-write to stored on-board device can be conveniently realized and wipe operation, and service speed is fast, high reliablity, containment device kind
Class is more.
The technical problems to be solved by the invention are realized using following technical scheme:
A kind of machine carried memory read-write equipment based on SOPC technology, including using fpga chip as the master controller of core,
The master controller be connected with for host computer transmission data serial port circuit, the master controller be connected with reset circuit,
Clock circuit, the first power-switching circuit are respectively used to reset, provide clock signal and conversion electric power, the master controller connection
There are SDRAM circuit, FLASH circuit, CONFIG circuit, jtag circuit to connect for constituting chip minimum system, the master controller
It is connected to UART circuitry and host computer and carries out serial communication, the master controller, which is connected with after the first CPLD control circuit, is connected with the
One relay array is used to switch the voltage and ground of circuit-under-test, and the master controller connects after being connected with the 2nd CPLD control circuit
It is connected to the second relay array and is connected to second relay for switching the signal and power supply of circuit-under-test, the master controller
Device array, first relay array are connected with connector after being connected to second relay array, and the connector is used
In linking objective memory device.
The 2nd CPLD control circuit connects measured device by second relay array and judges measured device
Whether each pin attribute is signal port, if not signal port then determines that port connects using the first CPLD control circuit
Connect voltage or ground.
First power-switching circuit is connected with 24V power circuit and 5V power circuit is used to supply to the master controller
Electricity, the 24V power circuit are connected with second source conversion circuit and are converted to power supply needed for measured device, the second source
Conversion circuit and power ground are connected to first relay array for being supplied to measured device port voltage or ground is connect.
The master controller uses chip model for the fpga chip of EP3C5F256；
The reset circuit is realized using MAX706SESA reset chip cooperation reset switch resets operation；
The clock circuit uses 50Mhz external active crystal oscillator；
First power-switching circuit is completed voltage using LMS1117-3.3/2.5/1.2V device and is converted, described in satisfaction
Master controller power supply requirement；
Memory of the SDRAM circuit as FPGA storage data and program code, using HY57V641620 chip；
The FLASH circuit still maintains data for storing program and data during power down, using model
The FLASH chip of AM29LV800B100EC；
The CONFIG circuit is used to carry out program Solidification to the master controller, completes the corresponding configuration of master controller,
The chip model used is EPCS16；
The jtag circuit carries out in-circuit emulation debugging for drawing debugging port, to the master controller.
The UART circuitry carries out the data interaction of upper and lower computer using RS232 agreement, using model SP3232EEN core
Piece is as serial port level conversion core piece.
The 2nd CPLD control circuit and the first CPLD circuit are divided using the CPLD chip of model MAX7128SQC100
Not complete pair signals/power supply, voltage/ground control decoding function.
The second source conversion circuit is adjusted as Voltage stabilizing module cooperation potentiometer using model LM2567-ADJ and is produced
Raw different voltages meet the power demands of measured device.
The beneficial effects of the present invention are:
(1) it can be written and read the operation such as wiping for a variety of encapsulation, a plurality of types of memories, using SOPC technology in bottom
Machine FPGA implant system can realize the configuration to pin, generalization and high degree of automation automatically under the instruction of host computer；
(2) it is fast and containing high excellent of system reliability to have had both FPGA service speed for the fpga core for using SOPC technology
Point can satisfy compared to the read-write equipment that the processors such as single-chip microcontroller are control core and realize that the read-write wiping to high-speed memory etc. is grasped
Make demand；
(3) with after SOPC technology, because of the extension of memory, the manipulable chip type of FPGA is greatly improved；
(4) the structure user friendly interface of upper and lower computer interaction, it is easy to operate, convenient for promoting the use of；
(5) it because slave computer no longer needs processor, reduces costs, and alterability, portability are stronger.
Detailed description of the invention
Present invention will be further explained below with reference to the attached drawings and examples.
Fig. 1 is circuit block diagram of the invention；
Fig. 2 is logic decoding circuit figure of the invention；
Fig. 3 is the I partial enlarged view of Fig. 2；
Fig. 4 is the II partial enlarged view of Fig. 2；
Fig. 5 is relay switching circuit figure of the invention.
Specific embodiment
In order to be easy to understand the technical means, the creative features, the aims and the efficiencies achieved by the present invention, below it is right
The present invention is further described.
The present invention includes slave computer device and upper computer software two parts.Wherein slave computer circuit printed board includes embedded core
FPGA module and its power supply/clock/reset circuit of heart control processor, SDRAM circuit, FLASH circuit, CONFIG circuit,
Jtag circuit, UART circuitry, logic decoding circuit, signal/power supply switch circuit, voltage/ground switching circuit, chip power conversion
Circuit, connector etc., it is main to complete to the initial configuration of memory pin, the generation of read-write sequence and the finger for receiving host computer
Enable data.Host computer mainly includes user-friendly application software, for assigning instruction to slave computer, transmitting to slave computer
The data of memory are written, receives from the data in the memory that slave computer is read and shows preservation.Upper and lower computer passes through RS-
232 serial ports carry out data communication, are in addition also equipped with fixture for different storage chips and are convenient for being connected with slave computer connector.
Hardware circuit of the invention circuit block diagram as shown in Figure 1:
A kind of machine carried memory read-write equipment based on SOPC technology, including using fpga chip as the master controller 1 of core,
The master controller 1 is connected with for the serial port circuit 11 with host computer transmission data, and the master controller 1 is connected with reset electricity
Road 2, clock circuit 3, the first power-switching circuit 4 are respectively used to reset, provide clock signal and conversion electric power, the main control
Device 1 is connected with SDRAM circuit 7, FLASH circuit 8, CONFIG circuit 9, jtag circuit 10 for constituting chip minimum system, institute
It states master controller 1 and is connected with UART circuitry 11 and host computer progress serial communication, the master controller 1 is connected with the first CPLD control
It is connected with the first relay array 15 after circuit 13 processed and is connected for switching the voltage and ground of circuit-under-test, the master controller 1
It is connected with signal and power supply that the second relay array 16 is used to switch circuit-under-test after having the 2nd CPLD control circuit 14, it is described
Master controller 1 is connected to second relay array 16, and first relay array 15 is connected to second relay
Connector 17 is connected with after array 16, the connector 17 is used for linking objective memory device.
Further, the 2nd CPLD control circuit 14 connects measured device by second relay array 16 and sentences
Whether each pin attribute of disconnected measured device is signal port, if not signal port then controls electricity using the first CPLD
Road 13 determines port connection voltage or ground.
Further, first power-switching circuit 4 is connected with 24V power circuit 5 and 5V power circuit 6 is used for institute
The power supply of master controller 1 is stated, the 24V power circuit 5 is connected with second source conversion circuit 12 and is converted to needed for measured device
Power supply, the second source conversion circuit 12 are connected to first relay array for being supplied to measured device with power ground
Port voltage or ground connection.
Further, it is the fpga chip of EP3C5F256 as control core that the master controller 1, which uses chip model,
II processor of internal build NIOS, it is main to complete to receive host computer instruction and data, Data within the chip is transmitted, target is stored
Each pin of device is configured, and the operation such as read-write sequence is generated；
The reset circuit 2 is realized using MAX706SESA reset chip cooperation reset switch resets operation；The clock
Circuit 3 uses 50Mhz external active crystal oscillator；
First power-switching circuit 4 completes voltage conversion using LMS1117-3.3/2.5/1.2V device, meets
The working power demand of fpga chip；
Memory of the SDRAM circuit 7 as FPGA storage data and program code, using HY57V641620 chip；
The FLASH circuit 8 still maintains data for storing program and data during power down, using model
The FLASH chip of AM29LV800B100EC；
The CONFIG circuit 9 is used to carry out program Solidification to the master controller 1, completes accordingly matching for master controller 1
It sets, the chip model used is EPCS16；
The jtag circuit 10 carries out in-circuit emulation debugging for drawing debugging port, to the master controller 1.
Further, the UART circuitry 11 carries out the data interaction of upper and lower computer using RS232 agreement, using model
SP3232EEN chip is as serial port level conversion core piece.
Further, the 2nd CPLD control circuit 14 and the first CPLD circuit 13 use model
The CPLD chip of MAX7128SQC100 is respectively completed to signal/power supply, voltage/ground control decoding function.
Further, the second source conversion circuit 12 cooperates electricity as Voltage stabilizing module using model LM2567-ADJ
Position meter, which is adjusted, generates the power demands that different voltages meet measured device.
As core of the invention circuit, logic decoding circuit includes two panels CPLD chip, completes and deposits to different target
The reading of reservoir configures, port data exchange.
Logic decoding circuit includes the first CPLD control circuit 13 and the 2nd CPLD control circuit 14, two kinds of circuit structure phases
Together, the switching that first relay array 15 is connect with the second relay array 16 come completing port is controlled by IO respectively.
Logic decoding circuit figure as shown in Figures 2 to 4:
Including the first CPLD chip U14 and the 2nd CPLD chip U15,6 tapes of the first CPLD chip U14 have on 1K
Pull-up resistor, 17 tapes of the first CPLD chip U14 have the pull-up resistor of 1K, 64 tapes of the first CPLD chip U14
There is the pull down resistor of 1K, 6 feet, 17 feet, 64 feet, 75 feet of the first CPLD chip U14 are connected separately with the first CPLD configuration
9 feet, 5 feet, 1 foot, 75 feet of port J13,2 feet of the first CPLD configuration port J13,10 feet ground connection, the first CPLD
4 feet of configuration port J13 meet power supply VCC.
11 feet, 12 feet, 14-16 foot, 18-27 foot, 29-35 foot, the 37-39 foot, 42-52 of the first CPLD chip U14
Foot, 54-60 foot, 62 feet, 63 feet, 65-67 foot, 69-74 foot, 77-83 foot, 85-87 foot, 94 feet, 95 feet be corresponding in turn in
Memory under test port is connected to letter for control selections by No. 64 relay control ports of first relay array 15
Number it is still connected to power supply, when selection is connected to signal, then corresponding relay switch movement connects the port of memory under test
It is connected to corresponding fpga chip port；When selection is connected to power supply, then corresponding relay switch is acted memory under test
Port is connected to second relay array 16, selects to connect port again by the 2nd CPLD chip U15 control
To corresponding power supply or ground.
First relay array 15 and the second relay array 16 respectively include the independence with same circuits structure
No. 64 relay switches, choose wherein describe connection relationship all the way below, relay switching circuit as shown in Figure 5:
The control terminal of relay K1 in first relay array 15 is connected to the control of the first CPLD chip U14
I/O port P/S1 processed, for selecting power supply/signal, the common end of relay K1 is connected with No. 1 port of the connector 17
Output end one end of LCON1, relay K1 are connected with the data I/O port LSIG1 of FPGA；
The control terminal of relay K2 in second relay array 16 is connected to the control of the 2nd CPLD chip U15
I/O port V/G1 processed, for selecting voltage/ground, the common end of relay K2 be connected in first relay array 15 after
The power supply of electric appliance K1 selects output end, and the output end of relay K2 is connected to voltage VCHIP and ground.
The present invention uses the control mode of FPGA+CPLD+ relay array, can meet high low speed demand, compared to using
Single-chip microcontroller is the read-write equipment of core, is supported more preferably the read-write of high speed storing chip, while available pin is more, obtains
For power in the software and hardware program capability and system-on-chip designs of FPGA, pin configuration is also more flexible, can not need change firmly
The read-write adaptation of more multi-memory is completed under the premise of part circuit.
The present invention also needs to carry out the hardware circuit built SOPC configuration, and the present invention uses SOPC technology, that is, programmable chip
Whole system is put on one chip with Programmable Technology, has flexible design method, can cut, expand, rise by upper system
Grade, and it is provided simultaneously with software and hardware program capability.
II processor cores of NIOS are embedded in FPGA, including CPU, on-chip memory, jtag interface, timer, power supply/
Signal control simultaneously mouth line, voltage/ground control simultaneously mouth line, system identifier, the outer FLASH bridge of piece and the outer sdram interface of external interface, piece and
The configuration such as clock, RS-232 interface, Memory connector signal simultaneously mouth line, configuration parameter include:
CPU parameter: standard type CPU core (II/s of Nios), command cache size 4Kbytes, JTAG debugging level are 1 grade；
On-chip memory parameter: Selective type is RAM type, word length 32, size 4Kbytes；
Jtag interface parameter: read-write FIFO depth is 64, while constructing its simulation model, can select difference as needed
Interactive window；
Timer parameter: initialization precision is 1ms, and it is most complete (Full-featured) to be configured to function；
Power supply/signal control simultaneously mouth line and voltage/ground control simultaneously mouth line parameter: being disposed as 8, only output type parallel port
Line；
The outer FLASH bridge of piece and external interface parameter: three-state data bus is set as the outer FLASH bridge of piece, external interface is
Address bus word length 19, data/address bus word length 8, timing is to establish 45ns/ 160ns/ is waited to keep 35ns；
The outer SDRAM parameter of piece: data/address bus word length 32, address bus word length 12,4 BANK use PLL phaselocked loop
85MHz clock is generated as SDRAM clock；
RS-232 serial ports parameter: baud rate 115200bit/s, data bit 8；
Connector signal line parallel port parameter: 2 groups of setting, every group 32, every tri-state attribute.
The present invention controls the read-write operation of memory under test using upper computer software and slave computer cooperation, and upper computer software is complete
At the selection of the functions such as device selection, reading, programming, erasing, data interaction is carried out with slave computer, by data with bin file
Form is transmitted to slave computer and memory is written, and by the reading data of memory and shows and is saved in the form of bin file；
Slave computer software completes configuration of the response host computer instruction completion to pin, generates each device reading, programming, erasing
Etc. timing, transmit the data that read from memory to host computer, receive the data of host computer and memory is written.
The basic principles, main features and advantages of the present invention have been shown and described above.The technology of the industry
Personnel are it should be appreciated that the present invention is not limited to the above embodiments, and what is described in the above embodiment and the description is only the present invention
Principle, without departing from the spirit and scope of the present invention, various changes and improvements may be made to the invention, these variation and
Improvement all fall within the protetion scope of the claimed invention.The claimed scope of the invention is by appended claims and its equivalent
Object defines.
Claims (7)
1. a kind of machine carried memory read-write equipment based on SOPC technology, it is characterised in that: including using fpga chip as core
Master controller (1), the master controller (1) are connected with for the serial port circuit (11) with host computer transmission data, the master control
Device (1) processed is connected with reset circuit (2), clock circuit (3), the first power-switching circuit (4) and is respectively used to reset, provides clock
Signal and conversion electric power, the master controller (1) be connected with SDRAM circuit (7), FLASH circuit (8), CONFIG circuit (9),
Jtag circuit (10) for constituting chip minimum system, the master controller (1) be connected with UART circuitry (11) and host computer into
Row serial communication, the master controller (1) are connected with the first relay array after being connected with the first CPLD control circuit (13)
(15) for switching the voltage and ground of circuit-under-test, the master controller (1) connects after being connected with the 2nd CPLD control circuit (14)
It is connected to the second relay array (16) and is connected to described for switching the signal and power supply of circuit-under-test, the master controller (1)
Second relay array (16), first relay array (15) are connected with after being connected to second relay array (16)
Connector (17), the connector (17) are used for linking objective memory device.
2. a kind of machine carried memory read-write equipment based on SOPC technology according to claim 1, it is characterised in that: described
2nd CPLD control circuit (14) connects measured device by second relay array (16) and judges respectively drawing for measured device
Whether foot attribute is signal port, if not signal port then determines that port connects using the first CPLD control circuit (13)
Connect voltage or ground.
3. a kind of machine carried memory read-write equipment based on SOPC technology according to claim 1, it is characterised in that: described
First power-switching circuit (4) is connected with 24V power circuit (5) and 5V power circuit (6) and is used to supply to the master controller (1)
Electricity, the 24V power circuit (5) is connected with second source conversion circuit (12) and is converted to power supply needed for measured device, described
Second source conversion circuit (12) and power ground are connected to first relay array for being supplied to measured device port electricity
Pressure or ground connection.
4. a kind of machine carried memory read-write equipment based on SOPC technology according to claim 1, it is characterised in that:
The master controller (1) uses chip model for the fpga chip of EP3C5F256；
The reset circuit (2) is realized using MAX706SESA reset chip cooperation reset switch resets operation；
The clock circuit (3) uses 50Mhz external active crystal oscillator；
First power-switching circuit (4) is completed voltage using LMS1117-3.3/2.5/1.2V device and is converted, described in satisfaction
Master controller (1) power supply requirement；
Memory of the SDRAM circuit (7) as FPGA storage data and program code, using HY57V641620 chip；
The FLASH circuit (8) still maintains data for storing program and data during power down, using model
The FLASH chip of AM29LV800B100EC；
The CONFIG circuit (9) is used to carry out program Solidification to the master controller (1), completes the corresponding of master controller (1)
Configuration, the chip model used is EPCS16；
The jtag circuit (10) carries out in-circuit emulation debugging for drawing debugging port, to the master controller (1).
5. a kind of machine carried memory read-write equipment based on SOPC technology according to claim 1, it is characterised in that: described
UART circuitry (11) carries out the data interaction of upper and lower computer using RS232 agreement, using model SP3232EEN chip as string
Mouth electrical level transferring chip.
6. a kind of machine carried memory read-write equipment based on SOPC technology according to claim 2, it is characterised in that: described
2nd CPLD control circuit (14) has been distinguished with the first CPLD circuit (13) using the CPLD chip of model MAX7128SQC100
Pair signals/power supply, voltage/ground control decoding function.
7. a kind of machine carried memory read-write equipment based on SPOC technology according to claim 3, it is characterised in that: described
Second source conversion circuit (12) is adjusted as Voltage stabilizing module cooperation potentiometer using model LM2567-ADJ and generates different electricity
Pressure meets the power demands of measured device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
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| CN201811037894.6A CN109460382A (en) | 2018-09-06 | 2018-09-06 | A kind of machine carried memory read-write equipment based on SOPC technology |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201811037894.6A CN109460382A (en) | 2018-09-06 | 2018-09-06 | A kind of machine carried memory read-write equipment based on SOPC technology |
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| CN101603979A (en) * | 2008-06-11 | 2009-12-16 | 东莞理工学院 | Embedded computer electrometric integrated instrument |
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