CN107807558A - Multibus communication card circuit and control method based on PCI9054 - Google Patents
Multibus communication card circuit and control method based on PCI9054 Download PDFInfo
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- CN107807558A CN107807558A CN201710899682.8A CN201710899682A CN107807558A CN 107807558 A CN107807558 A CN 107807558A CN 201710899682 A CN201710899682 A CN 201710899682A CN 107807558 A CN107807558 A CN 107807558A
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- 238000004891 communication Methods 0.000 title claims abstract description 33
- 238000000034 method Methods 0.000 title claims abstract description 13
- 238000012546 transfer Methods 0.000 claims abstract description 27
- 230000005540 biological transmission Effects 0.000 claims abstract description 23
- 239000013078 crystal Substances 0.000 claims description 3
- 230000005611 electricity Effects 0.000 claims description 3
- 238000013461 design Methods 0.000 abstract description 12
- 238000012360 testing method Methods 0.000 abstract description 3
- 241001269238 Data Species 0.000 abstract 1
- 230000006870 function Effects 0.000 description 10
- 238000011161 development Methods 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 3
- 238000011160 research Methods 0.000 description 3
- 238000012795 verification Methods 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 238000009434 installation Methods 0.000 description 2
- 230000002093 peripheral effect Effects 0.000 description 2
- 230000008569 process Effects 0.000 description 2
- 206010037660 Pyrexia Diseases 0.000 description 1
- 239000002253 acid Substances 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 238000005538 encapsulation Methods 0.000 description 1
- 230000007613 environmental effect Effects 0.000 description 1
- 238000009472 formulation Methods 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
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- 239000000203 mixture Substances 0.000 description 1
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Classifications
-
- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
- G05B19/00—Programme-control systems
- G05B19/02—Programme-control systems electric
- G05B19/04—Programme control other than numerical control, i.e. in sequence controllers or logic controllers
- G05B19/042—Programme control other than numerical control, i.e. in sequence controllers or logic controllers using digital processors
- G05B19/0423—Input/output
-
- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
- G05B2219/00—Program-control systems
- G05B2219/20—Pc systems
- G05B2219/25—Pc structure of the system
- G05B2219/25257—Microcontroller
Abstract
The present invention relates to the multibus communication card circuit based on PCI9054 and control method, including master chip, power circuit, jtag circuit, configuration circuit, reset circuit, clock circuit, eeprom circuit, pci interface circuit, interface, master chip and power circuit, jtag circuit, configuration circuit, reset circuit, clock circuit is connected, eeprom circuit provides configuration information for PCI chips, configuration circuit provides configuration information for master chip fpga chip, board and host computer use DMA transfer command frame and data frame, transmission direction and selected transmission RS232 are determined by parsings of the FPGA to command frame, RS422 channel datas.The invention provides a kind of Multi-bus circuit board solution of the road RS422 buses of the road of pci bus+1 RS232 buses+3, being in communication with each other between pci bus and RS232 buses, RS422 buses can be achieved, and have the advantages that integrated level is high, bus communication mode is optional, reduces board design cost, it can be widely applied in all kinds of bus testing systems.
Description
Technical field
The present invention relates to the Multi-bus circuit board communications field, specifically a kind of multibus communication board based on PCI9054
Card circuit and control method.
Background technology
Pci bus is developed by isa bus, has that transmittability is strong, multibus coexists, independently of CPU and automatic
The features such as identification configuration peripheral hardware, it is widely used at present in industry control test system.
At present, the design about PCI is always one of focus of numerous scholar's research, and wherein the permanent limited public affairs of science and technology are recalled in Hangzhou
The Chinese invention patent of the He Huinong applications of department《A kind of high-speed data communication interface card of pci bus》Publication No.
CN1700148, publication date 20051123, a kind of pci bus board of the alternatives formulation using CPLD+PCI9054 is disclosed,
The Chinese invention patent of Chen Xinglin of Harbin Institute of Technology et al. applications《Suitable for multibus agreement, the letter of more expansion interfaces
Number analog input card》, Publication No. CN104020691A, publication date 20140903, disclose a kind of side using FPGA+DSP
Formula carries out multiple bus communication, but using FPGA as microprocessor, with PCI9054 bus protocol chips, develops one with more total
The research of the communication card of line (1 road RS232 buses, 3 road RS422 buses) is long-term always ignored.
The content of the invention
The technical problems to be solved by the invention are that existing pci bus card can only realize unified bus mostly on the market
Communication, have the road RS422 buses of the road of pci bus+1 RS232 buses+3 multibus communication card research it is ignored for a long time
Present situation, the present invention be directed to current pci bus communication module Development Status, for grasp PCI board card design and its Principle of Communication,
The multibus communication card based on pci interface is developed, on the basis for being entirely to PCI9054 and its pci card development process progress system
On, with PCI9054 positions pci interface protocol chip, controlled with the Series FPGAs of Cyclone III (EP3C5E144C8) position local bus
Device, using " FPGA+PCI9054 " framework, design is a kind of to have the more of 1 road RS232,3 road RS422 transmitting-receiving based on pci interface
Bus communication card, providing the hardware design of the module and software development, (including the host computer test software based on VC++ is with being based on
Verilog board code), and verification experimental verification is carried out to its communication function.
Designed board is based on pci bus, and RS232 buses, RS422 buses are integrated, rather than design is based on
The RS232 bus cards or RS422 bus cards of pci bus, the phase between pci bus and RS232 buses, RS422 buses can be achieved
Mutual communication.
The technical problems to be solved by the invention are realized using following technical scheme：
Multibus communication card circuit based on PCI9054, including master chip, power circuit, jtag circuit, configuration electricity
Road, reset circuit, clock circuit, eeprom circuit, pci interface circuit, the master chip be connected to the power circuit,
Jtag circuit, configuration circuit, reset circuit, clock circuit, PCI circuits, the PCI circuits are connected with eeprom circuit.
The master chip uses Cyclone III Series FPGAs (EP3C5E144C8 chips) as processor.
The power circuit includes the operating voltage circuit for producing 1.2V, 2.5V, 3.3V, 5V, wherein 1.2V operating voltages
There is provided by ASM1117-1.2 elements, 2.5V operating voltages are provided by ASM1117-2.5 elements, 3.3V operating voltages by
ASM1117-3.3 elements are provided, and 5V operating voltages are provided by ASM1117-5 elements.
The clock circuit has source crystal oscillator generation by 50MHz's, and the reset circuit includes a low level and resetted
Chip MAX706SESA, the configuration circuit include series arrangement device EPCS16.
The PCI circuits include PCI9054 chips, and the eeprom circuit provides for the PCI9054 chips matches somebody with somebody confidence
Breath.
The eeprom circuit includes chip 11, and the chip 11 is eeprom chip 93LC56L, the chip ten
One 3 pin are serially connected with resistance 21 after being connected with 4 pin, the resistance 21 is grounded after being serially connected with button seven, the resistance
21 one end away from the button seven are connected with resistance 16, and the resistance 16 is serially connected with button eight and is followed by power vd D,
The 5 pin ground connection of the chip 11,6 pin of the chip 11 are serially connected with resistance 17 and are followed by power vd D, the chip 11
7 pin be serially connected with resistance 18 after be grounded, 8 pin of the chip 11 connection power vd D.
A kind of control method of the multibus communication card circuit based on PCI9054, including step：
S1) host computer starts DMA transfer transmission command frame；
S2) FPGA resolve commands frame；
S3) if order transmission direction is PCI-Local, step S4 is gone to), if order transmission direction is Local-PCI,
Then go to step S7；
S4 data) are sent to FPGA according to command selection passage, host computer；
S5) the FIFO of data deposit PCI board card；
S6) the selected passage of data is sent；
S7) according to command selection passage, by selected channel data deposit PCI FIFO；
S8) judge whether there is data in PCI FIFO, step S9 entered if having), if the return to step S7 without if)；
S9 the data in FIFO) are read.
The beneficial effects of the invention are as follows：The present invention can not only grasp the design of PCI board card and its Principle of Communication with system, and
Have the advantages that integrated level is high, bus communication mode is optional, reduces board design cost, can be widely applied to all kinds of buses
In test system.
Brief description of the drawings
The present invention is further described with reference to the accompanying drawings and examples.
Fig. 1 is the overall schematic diagram of the present invention；
Fig. 2 is the eeprom circuit figure of the present invention；
Fig. 3 is PCI board card of the invention to local bus data transfer flow figure；
Fig. 4 is the data transfer flow of local bus of the invention to pci bus；
Fig. 5 is the control method flow chart of the present invention.
Embodiment
In order that the technical means, the inventive features, the objects and the advantages of the present invention are easy to understand, below it is right
The present invention is expanded on further.
Overall schematic diagram as shown in Figure 1：
Master chip 1 uses Cyclone III Series FPGAs (EP3C5E144C8 chips) chip, the minimum of the master chip 1
System circuit design includes clock circuit 6, reset circuit 7, jtag circuit 3, configuration circuit 4, power circuit 2, the clock electricity
The clock signal on road 6 has source crystal oscillator generation by 50MHz's, and stable clock signal is provided for the master chip 1, described multiple
Position circuit 7 can be resetted by a low level reset chip MAX706SESA, reset circuit 7 when power supply is put into master chip,
Also reset signal can be provided when detecting power supply power-fail or power supply instantaneous short circuit, while has and resetted when rising on the supply voltage
The removing function of signal, the stability that the master chip 1 is run is ensure that, can be in power supply and environmental disturbances or program fleet
In the case of parking position accuracy chip, ensure program reliability of operation.The jtag interface that the jtag circuit 3 connects master chip is used for
Chip program is downloaded and artificial debugging.
The configuration circuit 4 includes EPCS16 chips, and EPCS16 chips are possess 16MbitFlash memory spaces serial
Configuration device, possess including in-system programmable components (ISP), flash memory access interface, save the small-sized integrated of veneer space
Circuit (SOIC) encapsulation etc. advanced features, be to Cyclone fpga chips series Large Copacity and low cost application environment under
Excellent selection, for the master chip 1 provide configuration information.
The power circuit 2 includes the operating voltage circuit for producing 1.2V, 2.5V, 3.3V, 5V, and wherein 1.2V, 2.5V is
FPGA core voltage, phaselocked loop analog voltage, 1.2V operating voltages are provided by ASM1117-1.2 elements, 2.5V operating voltages
There is provided by ASM1117-2.5 elements, the IO voltages that 3.3V operating voltages are FPGA and other devices (such as NLSX4373DR2G,
PCI9054, SP3232EEN etc.) operating voltage, provided by ASM1117-3.3 elements, 5V is part of devices (such as MAX490ESA
Deng) operating voltage, above-mentioned 1.2V, 2.5V, 3.3V and 5V operating voltage are changed by industrial computer PCI slot to be provided.
PCI circuits 8 include PCI9054 chips, and the PCI9054 chips are connected with pci bus socket, eeprom circuit 7
Configuration information is provided for the PCI9054 chips.
Eeprom circuit figure as shown in Figure 2：
The eeprom circuit 7 is eeprom chip 93LC56L including chip 11 U11, the U11 of chip 11, institute
State the U11 of chip 11 3 pin be connected with 4 pin after be serially connected with resistance 21 R21, the R21 of resistance 21 and be serially connected with short circuit
It is grounded after the J7 of block seven, the one end of the R21 of resistance 21 away from the J7 of short-circuit block seven is connected with resistance 16 R16, described
The R16 of resistance 16 is serially connected with the 5 pin ground connection that the J8 of short-circuit block eight is followed by power vd D, the U11 of chip 11, the chip 11
U11 6 pin be serially connected with the R17 of resistance 17 be followed by power vd D, the U11 of chip 11 7 pin be serially connected with the R18 of resistance 18 after
Ground connection, the 8 pin connection power vd D of the U11 of chip 11.When board is upper for the first time electric, the eeprom chip be blank, it is necessary to
3 pin of eeprom chip are dragged down before computer is opened, that is, plug short-circuit block J7, now PCI9054 will not be from EEPROM
Configuration information is read, register configures according to default value, will after computer is normally-open (after PCI9054 storage allocations)
3 pin of eeprom chip are drawn high, that is, plug short-circuit block J8, you can EEPROM is carried out in line writing.
The master chip 1 also leads to RS232 all the way and three road RS422 signals, is connected by DB25 interfaces with peripheral hardware.
The development process of this multibus communication card is described below：
A) SDK PLX_SDK is installed：PLX_SDK is software development kit, and the software kit produces to PLX companies
PCI chips have good compatibility, and provide perfect api function storehouse and debugging acid, facilitate User Exploitation application journey
Sequence；
B) board is inserted into PCI slot, mounting bridge chip drives：All PCI chips of PLX companies are contained in PLX_SDK
Driving, after computer finds PCI board card hardware, the drive installation under selecting PLX_SDK catalogues in hardware installation guiding；
C) programming EEPROM：Both the .hex files editted EEPROM can be write into by fever writes, and PLX_ can be also passed through
The PLXMon that SDK is provided carries out programming online；
D) board test software is developed：The api function storehouse provided using PLX companies, specifically include and find device, opening device
The functions such as part, data transfer and closure member, develop host computer test software；
E) board local bus test software is developed：In CPLD/FPGA device development environments, based on Verilog or VHDL
Language, develop local bus test software；
F) board function is tested：For the board developed, developed host computer is utilized to be tested with board soft
Part, its function is tested.
The control method of this communication card, control method flow chart as shown in Figure 5 is described below：
The control method of multibus communication card circuit based on PCI9054, including step：
S1) host computer starts DMA transfer transmission command frame；
S2) FPGA resolve commands frame；
S3) if order transmission direction is PCI-Local, step S4 is gone to), if order transmission direction is Local-PCI,
Then go to step S7；
S4 data) are sent to FPGA according to command selection passage, host computer；
S5) the FIFO of data deposit PCI board card；
S6) the selected passage of data is sent；
S7) according to command selection passage, by selected channel data deposit PCI FIFO；
S8) judge whether there is data in PCI FIFO, step S9 entered if having), if the return to step S7 without if)；
S9 the data in FIFO) are read.
The step S5) in, FPGA reads pci bus data from PCI9054, and is stored in PCI-Loacal directions FIFO.
The step S6) in, when there is data deposit in FIFO, RS232, the RS422 for just starting to be configured to command frame lead to
Road sends data.
The step S7) in, FPGA reads the number of RS232, RS422 passage collection from the FIFO in Local-PCI directions
According to, then sent to host computer by PCI9054.
PCI9054 chips rapidly can read and write data between memory or internal memory by configuring DMA channel
Without taking cpu resource, hardware resource and time are greatlyd save, it is proposed by the present invention a kind of based on the more of PCI9054
Bus communication board realizes DMA transfer by the DMA channel of the chip of PCI allocation 9054, in DMA transfer, by setting function
PlxPci_DmaTransferUserBuffer (* pDevice, channel, * pDmaParams, Timeout_ms) configured transmission
Related register value is configured, design parameter value is as shown in the table：
| Parameter name | Parameter type | Parameter role |
| *pDevice | PLX_DEVICE_OBJECT | Determine bridge chip device in pci bus |
| channel | U8 | DMA channel |
| *pDmaParams | PLX_DMA_PARAMS | DMA transfer parameter |
| Timeout_ms | U64 | The DMA transfer stand-by period |
The DMA transfer user cache function parameter explanation of table 1
DMA transfer includes two important parameters, is defined using structure：
PLX_DEVICE_OBJECT structures are used to describe selected PLX devices, and design parameter is defined as follows face structure
Shown in annotation.
PLX_DMA_PARAMS structures are used to describe DMA transfer parameter, and design parameter is defined as follows face structure annotation institute
Show.
Transmission in above-mentioned control method on command frame and data is that the mode based on DMA is transmitted, the DMA based on VC
Data transfer flow is as follows：
PCI board card as shown in Figure 3 is to local bus data transfer flow figure, first according to input data digit application user
Spatial cache, then writes input data into caching, then and DMA channel parameter is set, open DMA channel, set DMA transfer to join
Count, DMA channel is closed after DMA transfer user cache, finally discharge user cache, complete the data that PCI board snaps into local bus
Transmission.
Local bus as shown in Figure 4 is to the data transfer flow figure of pci bus, and master chip is according to input digit application use
Family caches, and sets DMA channel parameter, opens DMA channel, sets DMA transfer parameter, DMA transfer user cache, pci bus will
Data read-out in caching, data are delivered into edit box and shown, discharged user cache after finally closing DMA channel, complete locally extremely
The data transfer of pci bus.
One embodiment of the present of invention is described below：
Developed host computer test software, COM Debug Assistant and board function code are utilized, for DMA transfer side
Formula, experimental verification can be carried out to PCI read-write capabilitys.
1. (data that computer is write by pci bus are sent by serial ports) is transmitted in PCI → Local directions：
A) by the FPGA download programs of DMA transfer module into FPGA.
B) COM Debug Assistant is opened, it is 19200 to set baud rate.
C) host computer application program is run, DMA transmission mode is selected in host computer interface, selects transmission direction, selection
Passage 4 (serial ports), input transmission data " 01 02 03 04 " simultaneously click on " opening board " button；
D) " transmission data " button is clicked on, host computer carries out DMA transfer configuration to PCI9054, initiates to pass after the completion of configuration
Defeated, host computer writes to local base address and specifies data (01h 02h 03h 04h), and FPGA receives corresponding data and delivers to string
Mouth debugging assistant interface display.
2. Local → PCI directions transmission (data write by serial ports can be read in computer by pci bus)：
A) by the FPGA download programs of DMA transfer module into FPGA.
B) COM Debug Assistant is opened, it is 19200 to set baud rate, input transmission data " 01 02 03 04 ", often
200ms is cycled through.
C) host computer application program is run, DMA transmission mode is selected in host computer interface, selects transmission direction, selection
Passage 4 (serial ports), click on " opening board " button；
D) " transmission data " button is clicked on, host computer carries out DMA transfer configuration to PCI9054, initiates to pass after the completion of configuration
Defeated, FPGA transmits the data (01h 02h 03h 04h) of specified local base address to host computer and in Application Program Interface
Display.
General principle, principal character and the advantages of the present invention of the present invention has been shown and described above.The technology of the industry
For personnel it should be appreciated that the present invention is not limited to the above embodiments, that described in above-described embodiment and specification is the present invention
Principle, without departing from the spirit and scope of the present invention, various changes and modifications of the present invention are possible, these change and
Improvement all fall within the protetion scope of the claimed invention.The claimed scope of the invention is by appended claims and its equivalent
Thing defines.
Claims (7)
1. the multibus communication card circuit based on PCI9054, including master chip (1), power circuit (2), jtag circuit (3),
Configuration circuit (4), reset circuit (5), clock circuit (6), eeprom circuit (7), pci interface circuit (8), it is characterised in that：
The master chip (1) be connected to the power circuit (2), jtag circuit (3), configuration circuit (4), reset circuit (5), when
Clock circuit (6), PCI circuits (8), the PCI circuits (8) are connected with eeprom circuit (7).
2. the multibus communication card circuit according to claim 1 based on PCI9054, it is characterised in that：The main core
Piece (1) uses Cyclone III Series FPGAs, model EP3C5E144C8.
3. the multibus communication card circuit according to claim 1 based on PCI9054, it is characterised in that：The power supply
Circuit (2) includes the operating voltage circuit for producing 1.2V, 2.5V, 3.3V, 5V, and wherein 1.2V operating voltages are by ASM1117-1.2
Element is provided, and 2.5V operating voltages are provided by ASM1117-2.5 elements, and 3.3V operating voltages are provided by ASM1117-3.3 elements,
5V operating voltages are provided by ASM1117-5 elements.
4. the multibus communication card circuit according to claim 1 based on PCI9054, it is characterised in that：The clock
Circuit (6) has source crystal oscillator generation by 50MHz's, and the reset circuit (5) includes a low level reset chip
MAX706SESA, the configuration circuit (4) include series arrangement device EPCS16.
5. the multibus communication card circuit according to claim 1 based on PCI9054, it is characterised in that：The PCI electricity
Road (8) includes PCI9054 chips, and the eeprom circuit (7) provides configuration information for the PCI9054 chips.
6. the multibus communication card circuit according to claim 5 based on PCI9054, it is characterised in that：It is described
Eeprom circuit (7) includes chip 11 (U11), and the chip 11 (U11) is eeprom chip 93LC56L, the chip
11 (U11) 3 pin are serially connected with resistance 21 (R21) after being connected with 4 pin, the resistance 21 (R21) is serially connected with short circuit
Block seven (J7) is grounded afterwards, and the one end of the resistance 21 (R21) away from the short-circuit block seven (J7) is connected with resistance 16
(R16), the resistance 16 (R16) is serially connected with short-circuit block eight (J8) and is followed by power vd D, and 5 pin of the chip 11 (U11) connect
Ground, 6 pin of the chip 11 (U11) are serially connected with resistance 17 (R17) and are followed by power vd D, and the 7 of the chip 11 (U11)
Pin is serially connected with resistance 18 (R18) and is grounded afterwards, the 8 pin connection power vd D of the chip 11 (U11).
7. the control method of the multibus communication card circuit based on PCI9054, it is characterised in that：Including step：
S1) host computer starts DMA transfer transmission command frame；
S2) FPGA resolve commands frame；
S3) if order transmission direction is PCI-Local, step S4 is gone to), if order transmission direction is Local-PCI, turn
To step S7；
S4 data) are sent to FPGA according to command selection passage, host computer；
S5) the FIFO of data deposit PCI board card；
S6) the selected passage of data is sent；
S7) according to command selection passage, by selected channel data deposit PCI FIFO；
S8) judge whether there is data in PCI FIFO, step S9 entered if having), if the return to step S7 without if)；
S9 the data in FIFO) are read.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710899682.8A CN107807558B (en) | 2017-09-28 | 2017-09-28 | Multi-bus communication board card circuit based on PCI9054 and control method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710899682.8A CN107807558B (en) | 2017-09-28 | 2017-09-28 | Multi-bus communication board card circuit based on PCI9054 and control method |
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| CN107807558B CN107807558B (en) | 2024-03-22 |
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Cited By (3)
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| CN109541994A (en) * | 2018-10-29 | 2019-03-29 | 浙江求是科教设备有限公司 | A kind of real-time acquisition system and its acquisition method of high anti-interference ability |
| CN110597746A (en) * | 2019-09-18 | 2019-12-20 | 上海航天测控通信研究所 | Multichannel DMA control transmission device |
| CN111078613A (en) * | 2019-12-05 | 2020-04-28 | 北京航天福道高技术股份有限公司 | Simple communication board card and use method thereof |
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| CN111078613A (en) * | 2019-12-05 | 2020-04-28 | 北京航天福道高技术股份有限公司 | Simple communication board card and use method thereof |
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|---|---|
| CN107807558B (en) | 2024-03-22 |
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