CN107807558B - Multi-bus communication board card circuit based on PCI9054 and control method - Google Patents
Multi-bus communication board card circuit based on PCI9054 and control method Download PDFInfo
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- G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
- G05B19/00—Programme-control systems
- G05B19/02—Programme-control systems electric
- G05B19/04—Programme control other than numerical control, i.e. in sequence controllers or logic controllers
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
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Abstract
The invention relates to a PCI 9054-based multi-bus communication board card circuit and a control method, wherein the PCI 9054-based multi-bus communication board card circuit comprises a main chip, a power supply circuit, a JTAG circuit, a configuration circuit, a reset circuit, a clock circuit, an EEPROM circuit, a PCI interface circuit and an interface, the main chip is connected with the power supply circuit, the JTAG circuit, the configuration circuit, the reset circuit and the clock circuit, the EEPROM circuit provides configuration information for the PCI chip, the configuration circuit provides configuration information for a main chip FPGA chip, the board card and an upper computer use DMA to transmit command frames and data frames, and the analysis of the command frames by the FPGA determines the transmission direction and selects and transmits RS232 and RS422 channel data. The invention provides a multi-bus board solution of PCI bus+1-path RS232 bus+3-path RS422 bus, which can realize the mutual communication between the PCI bus and the RS232 bus and between the PCI bus and the RS422 bus, has the advantages of high integration level, selectable bus communication mode, board card design cost reduction and the like, and can be widely applied to various bus test systems.
Description
Technical Field
The invention relates to the field of multi-bus board communication, in particular to a PCI 9054-based multi-bus communication board card circuit and a control method.
Background
PCI bus is developed from ISA bus, has the characteristics of strong transmission capability, multi-bus coexistence, independence from CPU and automatic recognition configuration of peripheral equipment, and is widely applied to industrial control test systems at present.
At present, the design of PCI is one of the hot spots of many scholars, wherein the publication number of the chinese invention patent of the hui peasant application of the constant technology limited company in the hangzhou is CN1700148, the publication date is 20051123, a PCI bus board card developed by adopting the scheme of cpld+pci9054 is disclosed, the chinese invention patent of the university of harbine, chen Xinglin et al, the publication number of the chinese invention patent is CN104020691a, the publication date is 20140903, a multi-path bus communication is disclosed by adopting the manner of fpga+dsp, but the research of developing a communication card with multiple buses (1 path RS232 bus, 3 path RS422 bus) by adopting the FPGA as a microprocessor and using the PCI9054 bus protocol chip is long neglected.
Disclosure of Invention
The invention aims at the current situation that the research of multi-bus communication boards with PCI bus+1-path RS232 bus+3-path RS422 bus is ignored for a long time, develops a multi-bus communication card based on a PCI interface for grasping the PCI board design and the communication principle thereof, uses a PCI9054 bit PCI interface protocol chip and a cycle III series FPGA (EP 3C5E144C 8) bit local bus controller on the basis of the whole system development flow of the PCI9054 and the PCI card, adopts an FPGA+PCI9054 architecture, designs a multi-bus communication card with 1-path RS232 and 3-path RS422 transceiving based on the PCI interface, provides hardware design and software development (comprising upper computer test software based on VC++ and board card code based on Verilog) of the module, and performs test verification on the communication function of the module.
The designed board card integrates the RS232 bus and the RS422 bus based on the PCI bus, instead of designing the RS232 bus card or the RS422 bus card based on the PCI bus, the mutual communication between the PCI bus and the RS232 bus and between the PCI bus and the RS422 bus can be realized.
The technical problems to be solved by the invention are realized by adopting the following technical scheme:
the multi-bus communication board card circuit based on PCI9054 comprises a main chip, a power supply circuit, a JTAG circuit, a configuration circuit, a reset circuit, a clock circuit, an EEPROM circuit and a PCI interface circuit, wherein the main chip is respectively connected with the power supply circuit, the JTAG circuit, the configuration circuit, the reset circuit, the clock circuit and the PCI circuit, and the PCI circuit is connected with the EEPROM circuit.
The main chip adopts a Cyclone III series FPGA (EP 3C5E144C8 chip) as a processor.
The power supply circuit includes an operating voltage circuit that generates 1.2V, 2.5V, 3.3V, 5V, where 1.2V operating voltage is provided by ASM1117-1.2 components, 2.5V operating voltage is provided by ASM1117-2.5 components, 3.3V operating voltage is provided by ASM1117-3.3 components, and 5V operating voltage is provided by ASM1117-5 components.
The clock circuit is generated by an active crystal oscillator of 50MHz, the reset circuit comprises a low level reset chip MAX706SESA, and the configuration circuit comprises a serial configuration device EPCS16.
The PCI circuit comprises a PCI9054 chip, and the EEPROM circuit provides configuration information for the PCI9054 chip.
The EEPROM circuit comprises a chip eleven, the chip eleven is an EEPROM chip 93LC56L, 3 pins and 4 pins of the chip eleven are connected and then serially connected with a resistor twenty-one, the resistor twenty-one is serially connected with a key seven and then grounded, one end of the resistor twenty-one, which is far away from the key seven, is connected with a resistor sixteen, which is serially connected with a key eight and then connected with a power supply VDD, 5 pins of the chip eleven are grounded, 6 pins of the chip eleven are serially connected with a resistor seventeen and then connected with a power supply VDD, 7 pins of the chip eleven are serially connected with a resistor eighteen and then grounded, and 8 pins of the chip eleven are connected with the power supply VDD.
A control method of a multi-bus communication board card circuit based on PCI9054 comprises the following steps:
s1) starting DMA transmission by the upper computer to send command frames;
s2) the FPGA analyzes the command frame;
s3) if the command transmission direction is PCI-Local, the step S4) is carried out, and if the command transmission direction is Local-PCI, the step S7 is carried out;
s4) selecting a channel according to the command, and sending data to the FPGA by the upper computer;
s5) storing the data into FIFO of the PCI board card;
s6) sending out the data by the selected channel;
s7) selecting a channel according to the command, and storing the selected channel data into the FIFO of the PCI;
s8) judging whether data exist in the FIFO of the PCI, if so, entering the step S9), and if not, returning to the step S7);
s9) reading the data in the FIFO.
The beneficial effects of the invention are as follows: the invention not only can grasp PCI board card design and communication principle, but also has the advantages of high integration level, selectable bus communication mode, reduced board card design cost, and the like, and can be widely applied to various bus test systems.
Drawings
The invention will be further described with reference to the drawings and examples.
FIG. 1 is a general schematic diagram of the present invention;
FIG. 2 is a circuit diagram of an EEPROM of the present invention;
FIG. 3 is a flow chart of PCI card-to-local bus data transmission according to the present invention;
FIG. 4 is a flow chart of data transmission from the local bus to the PCI bus according to the present invention;
fig. 5 is a flow chart of a control method of the present invention.
Detailed Description
The present invention will be further described in the following to make the technical means, the creation characteristics, the achievement of the purpose and the effect of the present invention easy to understand.
The overall schematic as shown in fig. 1:
the main chip 1 adopts a Cyclone III series FPGA (EP 3C5E144C8 chip) chip, the minimum system circuit design of the main chip 1 comprises a clock circuit 6, a reset circuit 7, a JTAG circuit 3, a configuration circuit 4 and a power supply circuit 2, the clock signal of the clock circuit 6 is generated by a 50MHz active crystal oscillator to provide a stable clock signal for the main chip 1, the reset circuit 7 is a low-level reset chip MAX706SESA, the reset circuit 7 can reset the main chip when a power supply is input, can give a reset signal when the power supply is detected to be powered down or the power supply is instantly shorted, has a release function of the reset signal when the power supply voltage is raised, ensures the running stability of the main chip 1, can accurately reset the chip under the conditions of power supply and environmental interference or program running, and ensures the running reliability of the program. The JTAG circuit 3 is connected with a JTAG interface of the main chip for downloading a chip program and simulating and debugging.
The configuration circuit 4 comprises an EPCS16 chip, the EPCS16 chip is a serial configuration device with a storage space of 16MbitFlash, and has advanced features Including System Programmable (ISP), flash memory access interface, small integrated circuit (SOIC) package with saving of single board space, and the like, which is an excellent choice of a Cyclone FPGA chip series in a high-capacity and low-cost application environment, and provides configuration information for the main chip 1.
The power supply circuit 2 comprises an operating voltage circuit for generating 1.2V, 2.5V, 3.3V and 5V, wherein 1.2V and 2.5V are kernel voltages of the FPGA, phase-locked loop analog voltages, 1.2V operating voltages are provided by ASM1117-1.2 elements, 2.5V operating voltages are provided by ASM1117-2.5 elements, 3.3V operating voltages are IO voltages of the FPGA and operating voltages of other devices (such as NLSX4373DR2G, PCI9054, SP3232EEN and the like), ASM1117-3.3 elements provide operating voltages of 5V and partial devices (such as MAX490ESA and the like), and operating voltages of the 1.2V, 2.5V, 3.3V and 5V are provided by PCI slot conversion of an industrial personal computer.
The PCI circuit 8 comprises a PCI9054 chip, the PCI9054 chip is connected with a PCI bus socket, and the EEPROM circuit 7 provides configuration information for the PCI9054 chip.
EEPROM circuit diagram as shown in fig. 2:
the EEPROM circuit 7 comprises a chip eleven U11, the chip eleven U11 is an EEPROM chip 93LC56L, 3 pins and 4 pins of the chip eleven U11 are connected and then are connected in series with a resistor twenty-first R21, the resistor twenty-first R21 is connected with a short-circuit block seven J7 in series and then is grounded, one end of the resistor twenty-first R21, which is far away from the short-circuit block seven J7, is connected with a resistor sixteen R16, the resistor sixteen R16 is connected with a short-circuit block eight J8 in series and then is connected with a power supply VDD, 5 pins of the chip eleven U11 are grounded, 6 pins of the chip eleven U11 are connected with a resistor seventeen R17 in series and then are connected with a power supply VDD, 7 pins of the chip eleven U11 are connected with a resistor eighteen R18 in series and then are grounded, and 8 pins of the chip eleven U11 are connected with a power supply VDD. When the board card is powered on for the first time, the EEPROM chip is blank, 3 pins of the EEPROM chip are required to be pulled down before a computer is turned on, namely a short circuit block J7 is plugged in, at the moment, the PCI9054 does not read configuration information from the EEPROM, a register is configured according to a default value, after the computer is normally started (after the PCI9054 distributes memory), 3 pins of the EEPROM chip are pulled up, namely a short circuit block J8 is plugged in, and the EEPROM can be burned on line.
And one path of RS232 and three paths of RS422 signals are led out from the main chip 1 and are connected with the peripheral equipment through a DB25 interface.
The following describes the development flow of the multi-bus communication board card:
a) Installing a software development tool PLX_SDK: the PLX_SDK is a software development kit, and the software kit has good compatibility to PCI chips produced by PLX companies, provides a perfect API function library and a debugging tool, and is convenient for users to develop application programs;
b) Inserting the board card into the PCI slot, and installing the bridge chip driver: the PLX_SDK contains all PCI chip drivers of PLX company, and after the computer searches the PCI board card hardware, the driver installation under the PLX_SDK is selected in the hardware installation guide;
c) Programming EEPROM: the edited hex file can be written into the EEPROM through a writer, and the programming can be performed on line through PLXMON provided by PLX_SDK;
d) Developing board card test software: the method specifically comprises the steps of searching functions such as devices, opening the devices, transmitting data, closing the devices and the like by using an API function library provided by PLX company, and developing upper computer test software;
e) Developing board local bus test software: developing local bus test software based on Verilog or VHDL language in a CPLD/FPGA device development environment;
f) Testing the board function: aiming at the developed board card, the functions of the developed upper computer and board card testing software are tested.
The following describes a control method of the communication board card, such as a control method flowchart shown in fig. 5:
the control method of the multi-bus communication board card circuit based on PCI9054 comprises the following steps:
s1) starting DMA transmission by the upper computer to send command frames;
s2) the FPGA analyzes the command frame;
s3) if the command transmission direction is PCI-Local, the step S4) is carried out, and if the command transmission direction is Local-PCI, the step S7 is carried out;
s4) selecting a channel according to the command, and sending data to the FPGA by the upper computer;
s5) storing the data into FIFO of the PCI board card;
s6) sending out the data by the selected channel;
s7) selecting a channel according to the command, and storing the selected channel data into the FIFO of the PCI;
s8) judging whether data exist in the FIFO of the PCI, if so, entering the step S9), and if not, returning to the step S7);
s9) reading the data in the FIFO.
In the step S5), the FPGA reads PCI bus data from the PCI9054 and stores the PCI bus data in the PCI-loocal direction FIFO.
In the step S6), when data is stored in the FIFO, data transmission to the RS232 and RS422 channels configured by the command frame is started.
In the step S7), the FPGA reads the data collected by the RS232 and RS422 channels from the FIFO in the Local-PCI direction, and sends the data to the upper computer through the PCI 9054.
The PCI9054 chip can rapidly read and write data between memories or the memories by configuring a DMA channel without occupying CPU resources, so that hardware resources and time are greatly saved, and the multi-bus communication board card based on the PCI9054 realizes DMA transmission by configuring the DMA channel of the PCI9054 chip, and in the DMA transmission, a related register value is configured by setting a function PlxPci_DmaTransferUserBuffer (pDevice, channel) transmission parameter, and specific parameter values are shown in the following table:
| parameter name | Parameter type | Parameter effects |
| *pDevice | PLX_DEVICE_OBJECT | Determining PCI bus upper bridge chip device |
| channel | U8 | DMA channel |
| *pDmaParams | PLX_DMA_PARAMS | DMA transfer parameters |
| Timeout_ms | U64 | DMA transfer latency |
TABLE 1 DMA transfer user cache function parameter specification
DMA transfer includes two important parameters, defined by the structure:
the PLX_DEVICE_OBJECT structure is used to describe the selected PLX DEVICE, and the specific parameter definitions are shown in the following structure notes.
The plx_dma_params structure is used to describe DMA transfer parameters, the specific parameter definitions are shown in the following structure notation.
In the control method, the command frame and the data are transmitted in a mode based on DMA, and the DMA data transmission flow based on VC is as follows:
as shown in fig. 3, the flow chart of data transmission from the PCI board card to the local bus applies for the user buffer space according to the number of input data bits, then writes the input data into the buffer, then sets DMA channel parameters, opens the DMA channel, sets DMA transmission parameters, closes the DMA channel after the DMA transmits the user buffer, and finally releases the user buffer to complete the data transmission from the PCI board card to the local bus.
As shown in the data transmission flow chart from the local bus to the PCI bus in fig. 4, the main chip applies for the user buffer according to the input bit number, sets the DMA channel parameter, opens the DMA channel, sets the DMA transmission parameter, DMA transmits the user buffer, the PCI bus reads out the data in the buffer, sends the data to the edit box for display, and finally releases the user buffer after closing the DMA channel to complete the data transmission from the local bus to the PCI bus.
One embodiment of the invention is set forth below:
the PCI read-write function can be experimentally verified by using developed upper computer test software, serial port debugging assistant and board card function codes according to a DMA transmission mode.
(1) PCI- & gtlocal direction transmission (data written by a computer through a PCI bus is sent out through a serial port):
a) And downloading the FPGA program of the DMA transmission module into the FPGA.
b) And opening a serial port debugging assistant, and setting the baud rate to 19200.
c) Running an upper computer application program, selecting a DMA transmission mode in an upper computer interface, selecting a transmission direction, selecting a channel 4 (serial port), inputting transmission data 01 02 03 04 and clicking a button for opening a board card;
d) Clicking a data transmission button, performing DMA transmission configuration on PCI9054 by the upper computer, initiating transmission after the configuration is completed, writing specified data (01 h 02h 03h 04 h) into a local base address by the upper computer, receiving corresponding data by the FPGA, and sending the corresponding data to a serial port debugging assistant interface for display.
(2) Local→pci direction transfer (data written through serial port can be read into computer through PCI bus):
a) And downloading the FPGA program of the DMA transmission module into the FPGA.
b) The serial port debugging assistant is turned on, the baud rate is set to 19200, transmission data of 01 02 03 04 is input, and the serial port debugging assistant is sent in a circulating mode every 200 ms.
c) Running an upper computer application program, selecting a DMA transmission mode in an upper computer interface, selecting a transmission direction, selecting a channel 4 (serial port), and clicking an 'open board card' button;
d) Clicking a data transmission button, performing DMA transmission configuration on PCI9054 by the upper computer, initiating transmission after the configuration is completed, and transmitting data (01 h 02h 03h 04 h) of a specified local base address to the upper computer by the FPGA and displaying the data in an application program interface.
The foregoing has shown and described the basic principles, principal features and advantages of the invention. It will be understood by those skilled in the art that the present invention is not limited to the embodiments described above, and that the above embodiments and descriptions are merely illustrative of the principles of the present invention, and various changes and modifications may be made without departing from the spirit and scope of the invention, which is defined in the appended claims. The scope of the invention is defined by the appended claims and equivalents thereof.
Claims (3)
1. The multi-bus communication board card circuit based on PCI9054 comprises a main chip (1), a power supply circuit (2), a JTAG circuit (3), a configuration circuit (4), a reset circuit (5), a clock circuit (6), an EEPROM circuit (7) and a PCI interface circuit (8), and is characterized in that: the main chip (1) is respectively connected with the power supply circuit (2), the JTAG circuit (3), the configuration circuit (4), the reset circuit (5), the clock circuit (6) and the PCI interface circuit (8), and the PCI interface circuit (8) is connected with the EEPROM circuit (7); the clock circuit (6) is generated by a 50MHz active crystal oscillator, the reset circuit (5) comprises a low-level reset chip MAX706SESA, and the configuration circuit (4) comprises a serial configuration device EPCS16; the PCI interface circuit (8) comprises a PCI9054 chip, and the EEPROM circuit (7) provides configuration information for the PCI9054 chip; the EEPROM circuit (7) comprises a chip eleven (U11), wherein the chip eleven (U11) is an EEPROM chip 93LC56L, 3 pins and 4 pins of the chip eleven (U11) are connected and then connected with a resistor twenty-first (R21) in series, the resistor twenty-first (R21) is connected with a short-circuit block seven (J7) in series and then grounded, one end of the resistor twenty-first (R21) away from the short-circuit block seven (J7) is connected with a resistor sixteen (R16), the resistor sixteen (R16) is connected with a short-circuit block eight (J8) in series and then connected with a power supply VDD, 5 pins of the chip eleven (U11) are grounded, 6 pins of the chip eleven (U11) are connected with a resistor seventeen (R17) in series and then connected with the power supply VDD, 7 pins of the chip eleven (U11) are connected with a resistor eighteen (R18) in series and then grounded, and 8 pins of the chip eleven (U11) are connected with the power supply VDD;
PCI9054 chip reads and writes data between memories or memories quickly by configuring DMA channel without occupying CPU resource, and realizes DMA transmission by configuring DMA channel of PCI9054 chip, in DMA transmission, setting function
Plxpci_dmatransfer userbuffer (pDevice, channel, ×pdmapara ms, timeout_ms) transmission parameter configuration related register values;
the control method of the multi-bus communication board card circuit based on PCI9054 comprises the following steps:
s1) starting DMA transmission by the upper computer to send command frames;
s2) the FPGA analyzes the command frame;
s3) if the command transmission direction is PCI-Local, the step S4) is carried out, and if the command transmission direction is Local-PCI, the step S7 is carried out;
s4) selecting a channel according to the command, and sending data to the FPGA by the upper computer;
s5) storing the data into FIFO of the PCI board card;
s6) sending out the data by the selected channel;
s7) selecting a channel according to the command, and storing the selected channel data into the FIFO of the PCI;
s8) judging whether data exist in the FIFO of the PCI, if so, entering the step S9), and if not, returning to the step S7);
s9) reading data in the FIFO;
DMA transfer includes two important parameters, defined by the structure: the PLX_DEVICE_OBJECT structure is used to describe the selected PLX DEVICE, and specific parameter definitions are shown in the following structure notes;
the plx_dma_params structure is used to describe DMA transfer parameters, the specific parameter definitions are shown in the following structure notes;
in the control method, the command frame and the data are transmitted in a mode based on DMA, and the DMA data transmission flow based on VC is as follows:
the PCI board card applies for a user buffer memory space according to the number of input data bits, then writes the input data into a buffer memory, sets DMA channel parameters, opens a DMA channel, sets the DMA transmission parameters, closes the DMA channel after the DMA transmits the user buffer memory, and finally releases the user buffer memory to finish the data transmission from the PCI board card to the local bus;
and the PCI bus reads out data in the buffer memory, sends the data to an editing frame for display, and finally releases the user buffer memory after closing the DMA channel to finish the data transmission from the local PCI bus.
2. The PCI9054 based multi-bus communication board card circuit of claim 1, wherein: the main chip (1) adopts a Cyclone III series FPGA, and the model is EP3C5E144C8.
3. The PCI9054 based multi-bus communication board card circuit of claim 1, wherein: the power supply circuit (2) includes an operating voltage circuit that generates 1.2V, 2.5V, 3.3V, 5V, wherein 1.2V operating voltage is provided by ASM1117-1.2 element, 2.5V operating voltage is provided by ASM1117-2.5 element, 3.3V operating voltage is provided by ASM1117-3.3 element, and 5V operating voltage is provided by ASM1117-5 element.
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| CN110597746A (en) * | 2019-09-18 | 2019-12-20 | 上海航天测控通信研究所 | Multichannel DMA control transmission device |
| CN111078613A (en) * | 2019-12-05 | 2020-04-28 | 北京航天福道高技术股份有限公司 | Simple communication board card and use method thereof |
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| CN103678220A (en) * | 2013-12-23 | 2014-03-26 | 中国航空工业集团公司第六三一研究所 | Design method for extending LBE bus from PCI bus |
| CN106951388A (en) * | 2017-03-16 | 2017-07-14 | 湖南博匠信息科技有限公司 | A kind of DMA data transfer method and system based on PCIe |
| CN207318999U (en) * | 2017-09-28 | 2018-05-04 | 国营芜湖机械厂 | Multibus communication card circuit based on PCI9054 |
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| US20090100304A1 (en) * | 2007-10-12 | 2009-04-16 | Ping Li | Hardware and Software Co-test Method for FPGA |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103678220A (en) * | 2013-12-23 | 2014-03-26 | 中国航空工业集团公司第六三一研究所 | Design method for extending LBE bus from PCI bus |
| CN106951388A (en) * | 2017-03-16 | 2017-07-14 | 湖南博匠信息科技有限公司 | A kind of DMA data transfer method and system based on PCIe |
| CN207318999U (en) * | 2017-09-28 | 2018-05-04 | 国营芜湖机械厂 | Multibus communication card circuit based on PCI9054 |
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