CN105590548A - Creative electronic perpetual calendar - Google Patents

Abstract

The invention discloses a creative electronic perpetual calendar. The creative electronic perpetual calendar is composed of six modules, i.e., a master control module, a clock module, a storage module, a keyboard interface module, a display module and an alarm module. A master control chip employs a 52 series AT89S52 single-chip microcomputer, a clock chip is a high-performance low-loss real-time clock chip DS1302 with an RAM, and the storage module employs a serial EEPROM storage chip AT24C02. The single-chip microcomputer is utilized for control, the DS1302 is taken as a real-time clock chip, three-wire interfaces SCLK, I/O and RST<-> synchronously communicate with the single-chip microcomputer, and a power-off storage circuit, a display circuit, a keyboard circuit and an alarm circuit are externally arranged, such that a basic electronic perpetual calendar system is formed, and if any other functions are to be added, what is needed is to externally expand the circuits based on this.

Description

A kind of intention electronic calendar

A kind of intention electronic calendar of the present invention belongs to electronic device field.

Along with the fast development of current world economy and the arriving of information age, various small intelligent household appliances appear in the middle of our life successively. Calendar is the articles for daily use that people are indispensable. But general calendar is all articles for use made of paper, uses inconvenience, and the life-span is not long. Electronic calendar adopts smart electronics control and Display Technique, has improved the defect of calendar made of paper. The present invention, taking AT89S52 single-chip microcomputer as core, forms single chip machine controlling circuit, and AT89C52 is that 8 of low-voltage, the high-performance CMOSs of a kind of band 8K byte flash programmable and erasable read-only storage (PEROM) is controller. This device adopts ATMEL nonvolatile storage manufacturing technology to manufacture, with 80C51 and 80C52 instruction set and the output pin compatibility mutually of industrial standard. In conjunction with DS1302 clock chip and 24C02FLASH memory, automatic adjustment and the power down protection of deadline, full detail liquid crystal display. Time, date are adjusted and are realized by three buttons, and can arrange quarter-bell switch. Calendar can show solar calendar and lunar calendar year, month, day and week, time, minute, second. Showing when synodic month, the leap month of whether indicating.

Along with continuous progress and the development of science and technology, the use of single-chip microcomputer has been penetrated into the every field in the middle of our daily life, is almost difficult to find which field not use the trace of single-chip microcomputer. The guider of guided missile, the control of various instrument on aircraft, the network communication of computer and transfer of data, real-time control and the data processing of industrial automation process, widely used various intellective IC card, the safe-guard system of civilian limousine, the control of video recorder, video camera, automatic washing machine, and program control toy, electronic pet etc., these all be unable to do without single-chip microcomputer. The robot, intelligence instrument, medicine equipment of automation field are said nothing of.

Electronic calendar belong to small intelligent domestic electronic appliances. Utilize single-chip microcomputer to control, real-time timepiece chip clocks, and additional power down memory circuit and display circuit can be realized adjustment and the demonstration of time. Electronic calendar both can be widely used in family, also can be applicable to the hall of the relevant industries such as bank, post and telecommunications, hotel, restaurant, hospital, school, enterprise, shop, and the place such as unit meeting room, entrance guard. Thereby this invention has considerable realistic meaning and practical value.

Because the kind of present electronic calendar is on the market many, it is vital therefore selecting on earth which type of invention in invention. Correctly selection invention just can make product hommization more, and can reduce the difficulty of exploitation, shorten the cycle of exploitation, reduce cost of product etc., therefore will generally be accepted by people, and can quickly product be introduced to the market to the value that realizes himself.

Electronic calendar invention based on AT89S52 single-chip microcomputer

Do not use clock chip, and directly realize electronic calendar invention with AT89S52 single-chip microcomputer. AT89S52 is a kind of low-voltage with 8K byte flicker programmable and erasable read-only storage, and high-performance CMOS 8-bit microprocessor, is commonly called as single-chip microcomputer. The erasable read-only memory of single-chip microcomputer can be repeatedly erasable more than 1000 times. Due to multi-functional 8 bit CPUs and flash memory are combined in one single chip, the AT89S52 of ATMEL is a kind of efficient microcontroller, for a lot of embedded control systems provide a kind of flexibility high and inexpensive invention.

If adopt single-chip microcomputer timing, utilize its an every 50ms of 16 bit timing device/counter to produce an interrupt signal, produce after interrupting 20 times one second signal, then according to time system relation successively to point, time, day, week, the moon, year carry. So just realize directly and realized electronic calendar invention with single-chip microcomputer.

Realize electronic calendar invention with single-chip microcomputer, need not external other chips, take full advantage of the resource of single-chip microcomputer. But precision is not high enough, error is larger, loses all data after power down, and software programming is more complicated.

In the device forming taking single-chip microcomputer as core, often need a real-time clock and calendar, to give markers when some in real time logouts are occurred to, real-time timepiece chip just can play this effect. The clock chip of multiplex parallel interface of past, as MC146818, DS12887 etc. They can meet the requirement of SCM system to real-time clock completely, but these chips and interface microcontroller complexity, take address, data/address bus wiring is many, chip volume takes up room greatly, and various chips many, serial line interface in recent years are applied more and more many in SCM system, the real-time timepiece chip of serial line interface also occurred much, and DS1302 is a better and low-cost serial line interface real-time timepiece chip of combination property. Adopt and use it as the data record recording in TT&C system, its software and hardware invention is simple, time interocclusal record accurate, both avoided continuous recording large workload, avoid again the blindness of time recording, give continuously the normal operation of long measurement, control system and check and all carried out very large convenience, can be widely used in the TT&C system of long-time continuous. In Measurement and Control System, particularly, in the TT&C system of long-time unattended duty, often need to record the time of some data that acquire a special sense and appearance thereof. Traditional data record mode is every time sampling or timing sampling, there is no concrete time interocclusal record, therefore can only record data and time that cannot its appearance of accurate recording; If adopt single-chip microcomputer timing, need to adopt counter on the one hand, take hardware resource, need on the other hand to arrange interruption, inquiry etc., expend equally the resource of single-chip microcomputer, and some TT&C system may not allow. In system, adopt DS1302 can address this problem well

Utilize single-chip microcomputer to control, adopt DS1302 as real-time timepiece chip, its three-wire interface SCLK, I/O, with single-chip microcomputer carry out synchronous communication, additional power down memory circuit, display circuit, keyboard circuit and quarter-bell circuit, form a basic electronic calendar system, if also will add other functions, at this basic upper outside despreading circuit.

Due in the time that system is invented, need to consider following some factor: low in energy consumption, accuracy is high, software programming is simpler, manufacturing process is easy, the volume of chip is little, be easy to carry, and chip cost is low etc., and DS1302 chip has plurality of advantages recited above.

The present invention is taking AT89S52 single-chip microcomputer as core; form single chip machine controlling circuit; in conjunction with DS1302 clock chip and 24C02FLASH memory; show solar calendar year, month, day, week, time, minute, second and lunar calendar year, month, day; in the time showing between lunar time; the leap month of whether indicating, complete automatic adjustment and power down protection to them simultaneously, full detail with liquid crystal display out. Input interface is realized by three buttons, can adjust date and time with these three buttons, and can arrange the time of the switch of quarter-bell and quarter-bell. Alarm is realized by buzzer. Software control procedure is realized all functions. Circuitry use+5V voltage-stabilized power supply, can steady operation. The invention of its software and hardware is simple, time interocclusal record accurate, can be widely used in system that long-time continuous shows.

According to the requirement of system invention function, tentatively determine invention system by main control module, clock module, memory module, keyboard interface module, display module and quarter-bell module totally 6 modules form, Circuits System structure. Main control chip uses 52 series A T89S52 single-chip microcomputers, clock chip uses a kind of high-performance that U.S. DALLAS company releases, low-power consumption, real-time timepiece chip DS1302 with RAM, the Low-Power CMOS serial EEPROM storage chip AT24C02 that memory module adopts American ATMEL to produce. DS1302, as main timing chip, can accomplish accurate timing. The more important thing is, DS1302 can be at the standby of very little electric current (2.5～5.5V power supply, in the time of 2.5V, power consumption is less than 300nA) lower continue timing, and the multiple charging current of selection able to programme charges at a slow speed to back-up source, can ensure back-up source not power consumption substantially.

System core part---single chip computer AT 89S52

AT89S52 is a low-power consumption, 8 single-chip microcomputers of high-performance CMOS, sheet includes the Flash read-only program memory of erasable 1000 times repeatedly of 8kBytesISP (In-systemprogrammable), device adopts high density, the nonvolatile storage technologies manufacture of atmel corp, compatibility standard MCS-51 instruction system and 80C51 pin configuration, core Embedded general 8 central processing units and ISPFlash memory cell, the AT89S52 of powerful microcomputer can be many embedded Control application systems provides the solution invention of high performance-price ratio.

AT89S52 has following main performance

8KB reprogrammable Flash memory (can stand the write/erase cycle of 1000 times)

Full quiescent operation: 0Hz～24MHz

Three grades of program storages are maintained secrecy

128 × 8 byte inner RAM

Article 32, programmable I/O line

2 16 bit timing device/counters

6 interrupt sources

Serial-port able to programme

On-chip clock oscillator

The pin of AT89S52 and function

The pin explanation of AT89S52 single-chip microcomputer.

(1) main power source pin

VCC power end

2. GND earth terminal

(2) external crystal pins XTAL1 and XTAL2

XTAL1 connects a pin of external crystal. In single-chip microcomputer inside, it is the input that forms the inverting amplifier of sheet internal oscillator. In the time adopting external oscillator, the signal of this pin reception oscillator, the input of generator while both this signal directly being received to inside.

2. XTAL2 connects another pin of external crystal. In single-chip microcomputer inside, it is the output of the inverting amplifier of above-mentioned oscillator. While adopting external oscillator, this pin should suspend and not connect.

(3) control or with other power supply multiplexing pins RST, ALE/

The RESET input. In the time that oscillator moves, on this pin, occur that the high level of two machine cycles will make monolithic processor resetting.

2. ALE/ is in the time of access external memory, and ALE(address latch allows) output for the low byte of latch address. Even not access external memory, still periodically there is positive pulse signal taking constant frequency (this frequency is as 1/6 of oscillator frequency) in ALE end. Therefore, it can be used as the externally clock of output, or for timing object. But be noted that: in the time of access external data memory, will skip an ALE pulse. During to Flash memory program, this pin is also for inputting programming pulse ().

3. program storage permission () output is the read strobe signal of external program memory. When AT89S52/LV52 is during by external program memory instruction fetch (or constant), twice of each machine cycle effective (both having exported 2 pulses). But during this period, in the time of access external data memory, this twice effective signal will not occur.

4./VPP external reference allows end. Make CPU only access external program memory (address is 0000H～FFFFH), end must keep low level (receiving GND end). In the time that end keeps high level (connecing VSS end), CPU carries out the program in internal program memory.

(4) I/O pin P0.0～P0.7, P1.0～P1.7, P2.0～P2.7 and P3.0～P3.7

P0 port (P0.0～P0.7) P0 is a two-way I/O port of 8 open-drain types. As the delivery outlet used time, every potential energy drives 8 TTL inputs in the mode of Absorption Current, during to port write 1, can be used as again high impedance input.

2. P1 port (P1.0～P1.7) P1 is 8 two-way I/O ports with internal pull-up resistor. The output buffer of P1 can drive (absorbing or output current mode) 4 TTL inputs. During to port write 1, by inner pull-up resistor, port is moved to high potential, at this moment can be used as input port. While doing input port, because there is inner pull-up resistor, those pins that dragged down by external signal can be exported an electric current.

3. P2 port (P2.0～P2.7) P2 is 8 two-way I/O ports with internal pull-up resistor. The output buffer of P2 can drive (absorbing or output current mode) 4 TTL inputs. During to port write 1, by inner pull-up resistor, port is moved to high potential, at this moment can be used as input port. When P2 does input port use, because there is inner pull-up resistor, those pins that dragged down by external signal can be exported an electric current.

4. P3 port (P3.0～P3.7) P3 mouth pin is 8 two-way I/O mouths with internal pull-up resistor, can receive 4 TTL gate currents of output. When P3 mouth writes after " 1 ", they are drawn on inside as high level, and as input. As input, be low level because outside is drop-down, P3 mouth is by output current, and this is due to the cause of above drawing. P3 mouth also can be used as some specific functions of AT89S52.

Port pinout dual-purpose function

P3.0RXD(serial input mouth)

P3.1TXD(serial delivery outlet)

P3.2(external interrupt 0)

P3.3(external interrupt 1)

The outside input of P3.4T0(timer 0)

The outside input of P3.5T1(timer 1)

P3.6(external data memory write gate)

P3.7(external data memory read gate)

DS1302 clock circuit

DS1302 chip is introduced

Low-power Clock Chip DS1302 can carry out timing, and have the several functions such as leap year compensation year, month, day, hour, min, second. DS1302, for data record, on the record of the data point particularly some being acquired a special sense, can realize data and the time record simultaneously that occurs these data. Searching of the analysis of this record to for a long time continuous TT&C system result and the reason to abnormal data appearance is significant.

Adopt DS1302 as the data record recording in TT&C system, its software and hardware invention is simple, time interocclusal record accurate, both avoided continuous recording large workload, avoid again the blindness of time recording, give continuously the normal operation of long measurement, control system and check and all carried out very large convenience, can be widely used in the TT&C system of long-time continuous. In Measurement and Control System, particularly, in the TT&C system of long-time unattended duty, often need to record the time of some data that acquire a special sense and appearance thereof. Record and analyze the data of these Special Significance, the performance evaluation to TT&C system and normal operation have great importance. Traditional data record mode is every time sampling or timing sampling, there is no concrete time interocclusal record, therefore can only record data and time that cannot its appearance of accurate recording; If adopt single-chip microcomputer timing, need to adopt counter on the one hand, take hardware resource, need on the other hand to arrange interruption, inquiry etc., expend equally the resource of single-chip microcomputer, and some TT&C system may not allow. In system, adopt DS1302 can address this problem well.

The Performance Characteristics of DS1302

Real-time clock, can to second, point, time, day, week, the moon and with counting in the year that the leap year compensates;

For 31 × 8 temporary RAM of high-speed data;

Serial i/the O of minimum pins;

2.5～5.5V voltage power supply scope;

When 2.5V, power consumption is less than 300nA;

For single byte or multibyte (pulse mode) data mode of clock or RAM data read/write;

Simple 3 line interfaces;

Optionally at a slow speed charging (to VCC1) ability.

DS1302 clock chip comprises the static RAM (SRAM) of real-time clock/calendar and 31 bytes. It is through a simple serial line interface and microprocessor communication. Real-time clock/calendar provides second, point, time, day, week, Month And Year etc. information. Automatically adjust for the moon and the date at the end of month that are less than 31 days, also comprise the function of leap year correction. The operation of clock can adopt 24h or band AM(morning)/PM(afternoon) 12h form. Adopt three-wire interface and CPU to carry out synchronous communication, and can adopt burst mode once to transmit clock signal or the RAM data of multiple bytes. DS1302 has main power source/back-up source dual power supply pin: VCC1 provides low power supply in single supply and battery powered system, and lower powered battery backup is provided; VCC2 provides main power source in double power-supply system, and in this operational mode, VCC1 is connected to backup battery, so that can holding time information and data in the situation that there is no main power source. DS1302 is powered by the greater in VCC1 or VCC2. In the time that VCC2 is greater than VCC1+0.2V, VCC2 powers to DS1302; In the time that VCC2 is less than VCC1, DS1302 is powered by VCC1.

(2) DS1302 data manipulation principle

DS1302 must first initialize in the time that any data transmit, and RST pin is set to high level, then 8 bit address and command word is packed into shift register, and data are transfused at the rising edge of SCLK. No matter be read cycle or write cycle time, start 8 and specify in 40 registers which is accessed to. Starting 8 clock cycle, after command byte is packed into shift register, the other clock cycle is exported data, data writing in the time of write operation in the time of read operation. The number of clock pulses is 8 to add 8 under single byte mode, is 8 to add byte number under multibyte mode, and maximum can reach 248 byte numbers.

If be low level at the mid-RST of transport process, can stop the transmission of this secondary data, and I/O pin becomes high-impedance state. While powering on operation, before VCC is more than or equal to 2.5V, RST pin must keep low level. Only in the time that SCLK is low level.

Pin number pin name function

1VCC2 main power source

2,3X1, X2 oscillation source, external 32768HZ crystal oscillator

4GND ground wire

5 resets/chip select line

6I/O serial data input/output terminal (two-way)

7SCLK serial data input

8VCC1 back-up source

The highest significant position (position 7) of the control byte of DS1302 must be logical one; If it is logical zero, can not write data in DS1302. Position 6 if 0, represents access calendar clock data; Be 1 expression access RAM data. Position 5～1(A4～A0) instruction operating unit address. Least significant bit (position 0), as being 0, indicates to carry out write operation; Be that read operation is carried out in 1 expression. Control byte always starts I/O from lowest order.

In order to improve the addressability (address/command position 1～5=logical one) to 32 addresses, clock/calendar or ram register can be defined as to multibyte (burst) mode. Position 6 regulation clock or RAM, and position 0 regulation reads or writes. Data can not be stored in address 31 in address 9～31 or ram register in clock/calendar register. In multibyte mode, read or write from the position 0 of address 0. The order that must transmit by data is write 8 registers at first. But, in the time writing RAM in multibyte mode, needn't write all 31 bytes in order to transmit data. No matter whether write whole 31 bytes, each byte of writing all will be sent to RAM.

DS1302 has 12 registers, wherein has 7 registers and calendar, clock relevant, and the data bit of depositing is binary-coded decimal form, and its calendar, time register and control word thereof are in shown in Table 3-3, and wherein odd number is read operation, and even number is write operation.

AM-PM/12-24 hour mode: the position 7 of hour register is defined as 12 or 24 hours modes and selects position. When it is high level, select 12 hours modes. Under this mode, position 5 is AM/PM positions, and this position represents PM while being high level, and low level represents AM, and under 24 hours modes, position 5 is second 10 hours position (20～23h).

Clock suspension: the position 7 definition bit clocks of second register suspend position. In the time that it is 1, the DS1302 failure of oscillations, enters the backup mode of low-power consumption. Conventionally in the time that DS1302 is carried out to write operation (as entering clock adjustment programme), the failure of oscillations. In the time that it is 0, clock will start to start.

The application of DS1302

Real-time timepiece chip DS1302 adopts serial data transmission, can be power down protection power supply programmable charge function is provided, also can charge closing function, and chip adopts 32768Hz crystal oscillator. Specify, stand-by power supply BT1 can be with battery or super capacitor (more than 100,000 μ F). Although DS1302 power consumption after main power source power down is very little, if ensure that for a long time clock is normal, preferably select miniature charging battery. If power-off time shorter (several hours or several days), can replace (when 100 μ F just can ensure 1 hour normally walking) [9] with the less common electrochemical capacitor of electric leakage. DS1302, after powering up for the first time, need carry out initialization operation. After initializing, just can adjust time and quarter-bell by normal method.

Memory circuit

1,2,3 pin of AT24C02 are three address wires, for determining the hardware address of chip. The 8th pin and the 4th pin are respectively positive and negative power supply. The 5th pin SDA is serial data I/O, and data are by this two-way I2C bus serial transfer. The 6th pin SCL is serial clock input line. SDA and SCL all need and positive supply between respectively connect on the resistance of a 4.7K and draw.

I2C bus is a kind of two-wire system bus for connecting between I2C device. It is by SDA(serial data line) and SCL(serial time clock line) two pieces line transmission information between the device of linking in bus, and according to the each device of Address Recognition: no matter be single-chip microcomputer, memory, lcd driver or keyboard interface.

The characteristic of AT24C02

(1) basic structure of I2C bus

The single-chip microcomputer or the I2C device that adopt I2C bus standard, not only there is I2C interface circuit its inside, and each inside element circuit is divided into some relatively independent modules by function, realizes sheet choosing by software addressing, has reduced the connection of device chip select line. CPU can not only be affiliated to or pluck certain functional unit circuit from bus by instruction, also can detect the working condition of this unit, thereby realize not only simply but also flexibly expanding and control hardware system.

(2) interface features of transmitted in both directions

The sending and receiving of traditional Host μC serial interface is generally all respectively used a line, and I2C bus makes it can work in transmission or receive mode according to the function of device by software program. When certain device is when sending information in bus, its transmitter (being also main device), and when it is when bus receives information, become again receiver (also crying from device). Main device transmits data and produces clock with the open device transmitting for starting in bus, now any addressed device is all considered to from device. Address and data that the control of I2C bus is sent by the main device being articulated in bus completely determine.

It is not unalterable in bus, advocating peace from the relation of (being sending and receiving), but depends on the direction that now data transmit. SDA and SCL are two-way I/O line, connect positive supply by pull-up resistor. In the time that bus is idle, two lines are all high level. The output stage that connects the device of bus must be colelctor electrode or open-drain, to have wired AND function. The data transfer rate of I2C bus is 100kbit/s under standard operation mode, and under immediate mode, the highest transfer rate can reach 400kbit/s.

(3) clock signal in I2C bus

Clock sync signal in the time that I2C bus is uploaded carry information is to be completed by the logical “and” that is articulated in all devices on SCL clock line. On scl line, will have influence on these devices by high level to low level saltus step, once jump as low level under the clock signal of certain device, will make scl line keep low level always, and make all devices on scl line start low period. Now, the saltus step from low to high of the clock of the short device of low-level period can not affect the state of scl line, so these devices will enter the state that high level is waited for.

In the time that the clock signal of all devices all goes up jumping for high level, low period finishes, and scl line is released and returns to high level, and all devices all start their high period simultaneously. Thereafter, first device that finishes high period pulls into low level by scl line again. So just on scl line, produce a synchronised clock. Visible, clock low level time is determined by the longest device of clock low period, and clock high level time is determined by the shortest device of clock high period.

(4) transmission of data

In data transfer procedure, must confirm beginning and the end that data transmit. In the time that clock line SCL is high level, data wire SDA is that low level is defined as " beginning " signal by high level saltus step; In the time that scl line is high level, sda line generation low level is " end " signal to the saltus step of high level. Beginning and end signal are all to be produced by main device. After commencing signal, bus considered to be in busy condition; In a period of time after end signal, it is idle that bus is considered to.

The data transfer format of I2C bus is: after I2C bus commencing signal, first byte data of sending is used for selecting from address of devices, and wherein first 7 is address code, and the 8th is direction position (R/W). Direction position is that " 0 " represents to send, and main device is write information selected from device; Direction position is that " 1 " represents that main device will be from from device read message. After commencing signal, the address that each device in system is delivered to the address of oneself and main device in bus compares, if with main device, to send to address in bus consistent, this device is by the device of main device addressing, and its reception information still sends information and determined by the 8th (R/W).

In I2C bus, each data word joint number transmitting is not limit, but each byte is necessary for 8, and must, with an authorization bit (the 9th), also be response bits (ACK) after the byte of each transmission. Be all first to pass highest order at every turn, conventionally can make response from device receiving each byte, discharge scl line and return to high level, prepare to receive next data byte, main device can continue to transmit. For example, if (processing an internal interrupt in the time that device is being processed a real-time event and can not receive data, before handling, this interruption just can not receive the data byte in I2C bus), can make clock scl line keep low level, must make SDA keep high level from device, now main device produces 1 end signal, make to transmit abnormal ending, force main device in wait state. In the time being disposed from device, will discharge scl line, main device continues to transmit.

When main device sends after the data of a byte, then send corresponding to a clock (ACK) authorization bit on scl line, in clock, main device discharges sda line at this moment, a byte transmits and finishes, and from the response signal of device, sda line is pulled into low level, make SDA is stable low level between the high period of this clock. From the response signal of device finishes, sda line returns to high level, enters the next transmission cycle.

(5) arbitration of bus contention

In bus, may be mounted with multiple devices, two or more main devices occur sometimes want to take simultaneously the situation of bus. For example, in multi-single-chip microcomputer system, may at a time have two single-chip microcomputers to want to send data to bus, this situation is called bus contention simultaneously. I2C bus has many master controls ability, can arbitrate the bus contention occurring on sda line, its arbitration principle is such: in the time that multiple main devices are wanted to take bus simultaneously, if certain main device sends high level, and another main device sends low level, transmission level will be closed its output stage automatically with that device that now SDA bus level is not inconsistent. The arbitration of bus contention is carried out on two levels. First be the comparison of address bit, if main device addressing is same from device, enter the comparison of data bit, thereby guaranteed the reliability of competition arbitration. Because being utilizes the information in I2C bus to arbitrate, therefore can not cause the loss of information.

The interface of 24C02 and single-chip microcomputer is very simple, A0, and A1, A2 is address of devices line, WP is write-protect pin, SCL, SDA is two-wire serial interface, meets I2C bus protocol.

Liquid crystal display circuit

Display part is made up of HD61202 LCD Controller and Driver and HY12864 liquid crystal display, below we are introduced respectively it.

The feature of LCD Controller and Driver HD61202

HD61202 LCD Controller and Driver is a kind of graphic lcd display controller with driver output, and it can directly be connected with 8-bit microprocessor, and it can coordinate liquid crystal display is carried out to row, column driving with HD61203. HD61202 is a kind of LCD controller with row driver output, and it can be used in conjunction with line driver HD61203, composition liquid crystal display driving control system [12].

(1) built-in 64 × 64=4096 position display random access memory, in RAM, bits per inch shields bright, the dark state of a upper point according to corresponding LCD;

(2) HD61202 is row driver, has 64 road row driver outputs;

(3) the HD61202 reading and writing time sequential routine conforms to 68 series microprocessors, and therefore it can directly be connected with 68 series microprocessor interfaces;

(4) dutycycle of HD61202 is 1/32～1/64.

The pin function of LCD Controller and Driver HD61202

Pin CS1, CS2, the sheet choosing end that CS3 is chip; Pin E is read-write enable signal, and its data in the time of trailing edge is latched into HD61202; Between E high period, data are read out; R/W selects signal for read-write, is to be read gate for the moment when it, is within 1 o'clock, to be write gate; DB0-DB7 is that data/address bus RST is reseting signal reset signal when effective, closes liquid crystal display, makes to show initial behavior 0, and RST can be connected with MCU, is controlled by MCU; Also can directly meet VDD.

The instruction system of LCD Controller and Driver HD61202

The instruction system of HD61202 is fairly simple, altogether only has seven kinds. Now be described below respectively.

(1) show ON/OFF instruction

R/WRSDB7DB6DB5DB4DB3DB2DB1DB0

0000111111/0

In the time of DBO=1, the content in LCD display random access memory; When DBO=0, close demonstration.

(2) show that initial row (ROW) arranges instruction

R/WRSDB7DB6DB5DB4DB3DB2DB1DB0

0011 shows initial row (0-63)

This instruction is provided with the line number of the display random access memory of the lastrow of corresponding liquid crystal display, and regular change shows initial row, can make LCD realize the effect that shows roll screen.

(3) page (PAGE) is put instruction

Display random access memory is totally 64 row, divides 8 pages, every page of 8 row.

(4) column address (YAddress) arranges instruction

R/WRSDB7DB6DB5DB4DB3DB2DB1DB0

0001 display column address (0-63)

Be provided with page address and column address, determined a unit in display random access memory with regard to unique, MCU just can read interior in this unit with reading and writing instruction and perhaps write into a byte data to this unit like this.

(5) read states instruction

R/WRSDB7DB6DB5DB4DB3DB2DB1DB0

10BUSY0ON/OFFREST0000

This instruction is used for inquiring about the state of HD61202, and each parameter implication is as follows:

BUSY:1-inside is in work 0-normal condition

ON/OFF:1-shows that closing 0-demonstration opens

REST:1-reset mode 0-normal condition

In the time of BUSY and REST state, except read states instruction, other instruction is not all to HD61202 generation effect. To inquire about BUSY state to before HD61202 operation, can operate HD61202 determining whether.

(6) write data command

R/WRSDB7DB6DB5DB4DB3DB2DB1DB0

01 writes data

Reading and writing data command often executes reading and writing operations, and column address just increases one automatically, and before must be noted that and carrying out read operation, once empty read operation, and then reads just can read the data in the unit that will read again.

Be connected; With HD61202(2) CS1 be connected, therefore, gating composite signal is ,=01 gating (1), ,=10 gatings (2). For HY-12864, as long as supply with VDD, VSS and V0, the required power supply of HD61202 and HD61203 will be produced by inside modules circuit under the effect of VDD and V0, VSS.

The application of HY-12864

Following content is the interface circuit taking single-chip microcomputer 89S52 as example machine, the interface circuit that control circuit is Direct Access Mode. VSS ground connection; Connect+5V of digital power VDD; Contrast control voltage V0 connects potentiometer, can adjust liquid crystal brightness by regulator potentiometer; Data, instruction select signal RS to connect single-chip microcomputer P2.0 mouth; Read-write selects signal R/W to connect single-chip microcomputer P2.1 mouth; Single-chip microcomputer reading and writing gating signal, meet the read-write enable signal E of liquid crystal by NAND gate; DB0～DB7 connects respectively P0.0～P0.7 mouth of single-chip microcomputer; The sheet choosing of chip 1, chip 2 connects respectively P2.2, the P2.3 mouth of single-chip microcomputer; Reset terminal RST, connect+5V of positive supply LEDA backlight; Liquid crystal drive voltage VEE, negative supply LEDK ground connection backlight.

Keyboard circuit

The present invention adopts 3 of buttons altogether, is connected with P1.5, P1.6, the P1.7 mouth of single-chip microcomputer respectively, and respectively corresponding cursor movement, time, date are adjusted, and exit, the function of quarter-bell on & off switch.

Quarter-bell circuit

In the time that quarter-bell shows " pass ", quarter-bell is inoperative; In the time that quarter-bell shows " opening ", set the quarter-bell time, when the quarter-bell time is set only and point, the continuous quarter-bell time comparison with setting of current time, when unequal, do not produce any phenomenon, once equate, a low level of P3.5 output makes triode conducting, thereby make buzzer work, quarter-bell works.

The invention of 4.1 solar calendar programs

Because used clock chip DS1302, solar calendar program only need be read year from the each register of DS1302, week, month, day, when ［ little ］, the data such as minute, second, then process. Before first DS1302 being operated, must initialize it, then sense data from DS1302, more after treatment, give display buffer unit.

Time adjustment programme invention

The adjustment time is shifted, controls use with three adjustment buttons a, conduct, and a conduct adds use, and a conduct is exited and adjusted and quarter-bell switch use. Be defined as respectively control button, add button, exit button. Adjusting in time course, should have any different with other position in the position that adjust, so increased flashing function, glimmer in the position of adjusting always, until adjustment next bit. Flicker principle is exactly, and allows of will adjust often extinguish at regular intervals once, and be 50ms for example interval time. Utilize timer timing, in the time reaching 50ms and overflow, just give this position and extinguish symbol, upper while once overflowing, then send the value of normal demonstration, constantly replace, until adjust this end. Now send normal show value to this position, then enter next bit adjustment flicker program.

The invention of lunar calendar program

The realization of lunar calendar program will lean on the solar calendar date to calculate. To calculate lunar date according to solar calendar, first will invention algorithm. Projectional technique is that the number of days according to solar calendar current date in a year calculates lunar date. Solar calendar one month is not within 30 days, to be exactly 31 days (except February, be 29 days February in leap year, and be 28 days February in non-leap year). Lunar calendar has 12 months in 1 year or 13 months (leap month of containing), within one month, is 30 days or 29 days. If only have the moon of 29 days to call the solar month of 30 days one, with 1 being mark, the moon of 30 days is called to the solar month, be to indicate with 0,12 binary systems just can represent the size of a year 12 months so. If the leap month of having, using leap month high 4 as a byte of month, the size leap month of low 4 bit representation, be 0 the solar month, the solar month of 30 days is 1, such byte has just comprised the information all leap month. The number of days that the lunar calendar Spring Festival and solar calendar differ New Year's Day is also used a byte representation. Altogether just can store in 1 year the relevant data of the corresponding relation of any one day solar calendar and lunar calendar by 4 bytes.

Differ from the Spring Festival of 2004 and New Year's Day 21 days, the information table of such 2004 is shown: 21,42H, 52H, 21H. Wherein represent the byte of 12 months size information, the 4th and the 7th need not, the 1st byte is the decimal system, other be all hexadecimal. According to said method, the solar calendar of 50 years and lunar calendar mapping table use 200 bytes altogether.

After having had algorithm and data, just can invention software. First will be according to the date of current solar calendar, calculating solar calendar is which day in this year. Calculate any one day program circuit in which sky of this Nian Zhongwei in solar calendar.

Calculate the current solar calendar date and be after which day in this year, then deduct the diurnal inequality on this year Spring Festival of solar calendar and New Year's Day, subtract if enough, be exactly total the result lunar calendar subtracting each other which day in this year. Just can extrapolate concrete current lunar date according to these data; If subtracted not, represent that the current lunar year is the previous year of solar year. In this case, according to reality, current lunar date can be in lunar calendar November or December, and now to deduct the current solar calendar date that previous calculations goes out be the data of which day at solar year to the diurnal inequality on the Spring Festival and New Year's Day, and its result represents the number of days of current lunar date from the Spring Festival. Which day that the solar calendar number of days calculating is this year, leave in register R2 and R3. Calculate after number of days, if be greater than #FFH, #FFH is left in R2, residual value leaves in R3. That is to say that R2 serves as master register in the number of days information representing with register R2 and R3, data are first filled with R2, then deposit R3. In whole conversion program, the data here can not be capped.

Calculate after the total number of days of solar calendar, just can calculate lunar date according to it. Projectional technique is, first deducts the diurnal inequality on the Spring Festival and New Year's Day with total number of days, if result is 1, this sky is just in time that the Spring Festival, (because after New Year's Day, in the time calculating the diurnal inequality on the Spring Festival and New Year's Day, suppose that be 0 day New Year's Day the Spring Festival, be n days the Spring Festival, and diurnal inequality is n. And the total number of days of the solar calendar of previous calculations is this day which day in this year, obtain taking New Year's Day as 1, with calculate the Spring Festival with New Year's Day diurnal inequality this quadrat method compare, its numerical value has lacked 1, so on the basis of foundation that should be exactly using 0 as this day originally the Spring Festival, add 1, thus using 1 as this day be the mark in the Spring Festival); If result is less than 1, lunar calendar should be the previous year of solar calendar; If result is greater than 1, illustrate that solar calendar and lunar calendar are same year. According to the information in the leap year of the lunar calendar of this year of the gained of tabling look-up and large solar month of 30 days, just the lunar date of this day can be extrapolated again.

Regulate the brightness of 10K potentiometer R4 capable of regulating LCDs. Adjust to after appropriate brightness, by control button, cursor can start from solar year position flicker, enters the adjustment state of setting. Now press and add button, Contemporary Digital just can change. Press once, numeral adds 1; If press long, numeral adds continuously. Now, glimmering in the position of adjustment always, until again press cursor movement control bit, cursor jumps to next bit flicker. Adjustment order is followed successively by: solar calendar year, month, day, lunar calendar year, month, day, time, minute, second, when quarter-bell, point. After whole parameter adjustments, by exit button, cursor stops flicker, exits the adjustment state of setting; When again pressing this button, quarter-bell shows " opening "; When pressing this key for the third time, quarter-bell shows " pass ". The leap month of if current month being, the screen lower left corner can show " leap month "; If not leap month, without showing.

Debugging is divided into hardware debug and software debugging. Hardware debug is mainly whether detection hardware circuit has short circuit, opens circuit, rosin joint etc. The hardware circuit of DS1302 is very simple, is only connected with single-chip microcomputer by 3 lines, be easy to detect, and be mainly to check its pin, as whether crystal oscillator and power supply etc. connect. Can carry out debug hardware by software in addition, as whether correct in order to test display circuit connection, can write a simple display routine and test it. Next can carry out software debugging, only can write containing the timing of DS1302 and read-write program, display routine, whether test DS1302 normally works. Last debug time adjustment programme and lunar calendar estimation program.

Timer most critical be the precision of timing. In electronic calendar, DS1302 circuit uses special crystal oscillator, the electronic calendar of making after tested, a week fast about 3s, error is larger, can use standard crystal oscillator instead or revise with software in experiment invention.

Claims (8)

1. a kind of intention electronic calendar of the present invention does not use clock chip, and directly realizes electronic calendar invention with AT89S52 single-chip microcomputer; AT89S52 is a kind of low-voltage with 8K byte flicker programmable and erasable read-only storage, and high-performance CMOS 8-bit microprocessor, is commonly called as single-chip microcomputer; The erasable read-only memory of single-chip microcomputer can be repeatedly erasable more than 1000 times; Due to multi-functional 8 bit CPUs and flash memory are combined in one single chip, the AT89S52 of ATMEL is a kind of efficient microcontroller, for a lot of embedded control systems provide a kind of flexibility high and inexpensive invention;

If adopt single-chip microcomputer timing, utilize its an every 50ms of 16 bit timing device/counter to produce an interrupt signal, produce after interrupting 20 times one second signal, then according to time system relation successively to point, time, day, week, the moon, year carry; So just realize directly and realized electronic calendar invention with single-chip microcomputer;

Realize electronic calendar invention with single-chip microcomputer, need not external other chips, take full advantage of the resource of single-chip microcomputer; But precision is not high enough, error is larger, loses all data after power down, and software programming is more complicated;

In the device forming taking single-chip microcomputer as core, often need a real-time clock and calendar, to give markers when some in real time logouts are occurred to, real-time timepiece chip just can play this effect; The clock chip of multiplex parallel interface of past, as MC146818, DS12887 etc.; They can meet the requirement of SCM system to real-time clock completely, but these chips and interface microcontroller complexity, take address, data/address bus wiring is many, chip volume takes up room greatly, and various chips many, serial line interface in recent years are applied more and more many in SCM system, the real-time timepiece chip of serial line interface also occurred much, and DS1302 is a better and low-cost serial line interface real-time timepiece chip of combination property; Adopt and use it as the data record recording in TT&C system, its software and hardware invention is simple, time interocclusal record accurate, both avoided continuous recording large workload, avoid again the blindness of time recording, give continuously the normal operation of long measurement, control system and check and all carried out very large convenience, can be widely used in the TT&C system of long-time continuous; In Measurement and Control System, particularly, in the TT&C system of long-time unattended duty, often need to record the time of some data that acquire a special sense and appearance thereof; Traditional data record mode is every time sampling or timing sampling, there is no concrete time interocclusal record, therefore can only record data and time that cannot its appearance of accurate recording; If adopt single-chip microcomputer timing, need to adopt counter on the one hand, take hardware resource, need on the other hand to arrange interruption, inquiry etc., expend equally the resource of single-chip microcomputer, and some TT&C system may not allow; In system, adopt DS1302 can address this problem well

Utilize single-chip microcomputer to control, adopt DS1302 as real-time timepiece chip, its three-wire interface SCLK, I/O, with single-chip microcomputer carry out synchronous communication, additional power down memory circuit, display circuit, keyboard circuit and quarter-bell circuit, form a basic electronic calendar system, if also will add other functions, at this basic upper outside despreading circuit.

2. due in the time that system is invented, need to consider following some factor: low in energy consumption, accuracy is high, software programming is simpler, manufacturing process is easy, the volume of chip is little, be easy to carry, and chip cost is low etc., and DS1302 chip has plurality of advantages recited above;

The present invention is taking AT89S52 single-chip microcomputer as core, form single chip machine controlling circuit, in conjunction with DS1302 clock chip and 24C02FLASH memory, show solar calendar year, month, day, week, time, minute, second and lunar calendar year, month, day, in the time showing between lunar time, the leap month of whether indicating, complete automatic adjustment and power down protection to them simultaneously, full detail with liquid crystal display out; Input interface is realized by three buttons, can adjust date and time with these three buttons, and can arrange the time of the switch of quarter-bell and quarter-bell; Alarm is realized by buzzer; Software control procedure is realized all functions; Circuitry use+5V voltage-stabilized power supply, can steady operation; The invention of its software and hardware is simple, time interocclusal record accurate, can be widely used in system that long-time continuous shows;

According to the requirement of system invention function, tentatively determine invention system by main control module, clock module, memory module, keyboard interface module, display module and quarter-bell module totally 6 modules form, Circuits System structure; Main control chip uses 52 series A T89S52 single-chip microcomputers, clock chip uses a kind of high-performance that U.S. DALLAS company releases, low-power consumption, real-time timepiece chip DS1302 with RAM, the Low-Power CMOS serial EEPROM storage chip AT24C02 that memory module adopts American ATMEL to produce; DS1302, as main timing chip, can accomplish accurate timing; The more important thing is, DS1302 can be at the standby of very little electric current (2.5～5.5V power supply, in the time of 2.5V, power consumption is less than 300nA) lower continue timing, and the multiple charging current of selection able to programme charges at a slow speed to back-up source, can ensure back-up source not power consumption substantially;

A kind of intention electronic calendar of the present invention system core part---single chip computer AT 89S52

AT89S52 is a low-power consumption, 8 single-chip microcomputers of high-performance CMOS, sheet includes the Flash read-only program memory of erasable 1000 times repeatedly of 8kBytesISP (In-systemprogrammable), device adopts high density, the nonvolatile storage technologies manufacture of atmel corp, compatibility standard MCS-51 instruction system and 80C51 pin configuration, core Embedded general 8 central processing units and ISPFlash memory cell, the AT89S52 of powerful microcomputer can be many embedded Control application systems provides the solution invention of high performance-price ratio;

AT89S52 has following main performance

8KB reprogrammable Flash memory (can stand the write/erase cycle of 1000 times)

Full quiescent operation: 0Hz～24MHz

Three grades of program storages are maintained secrecy

128 × 8 byte inner RAM

Article 32, programmable I/O line

2 16 bit timing device/counters

6 interrupt sources

Serial-port able to programme

On-chip clock oscillator

The pin of AT89S52 and function

The pin explanation of AT89S52 single-chip microcomputer;

(1) main power source pin

1. VCC power end

2. GND earth terminal

(2) external crystal pins XTAL1 and XTAL2

1. XTAL1 connects a pin of external crystal; In single-chip microcomputer inside, it is the input that forms the inverting amplifier of sheet internal oscillator; In the time adopting external oscillator, the signal of this pin reception oscillator, the input of generator while both this signal directly being received to inside;

2. XTAL2 connects another pin of external crystal; In single-chip microcomputer inside, it is the output of the inverting amplifier of above-mentioned oscillator; While adopting external oscillator, this pin should suspend and not connect;

(3) control or with other power supply multiplexing pins RST, ALE/

1. the RESET input; In the time that oscillator moves, on this pin, occur that the high level of two machine cycles will make monolithic processor resetting;

2. ALE/ is in the time of access external memory, and ALE(address latch allows) output for the low byte of latch address; Even not access external memory, still periodically there is positive pulse signal taking constant frequency (this frequency is as 1/6 of oscillator frequency) in ALE end; Therefore, it can be used as the externally clock of output, or for timing object; But be noted that: in the time of access external data memory, will skip an ALE pulse; During to Flash memory program, this pin is also for inputting programming pulse ();

3. program storage permission () output is the read strobe signal of external program memory; When AT89S52/LV52 is during by external program memory instruction fetch (or constant), twice of each machine cycle effective (both having exported 2 pulses); But during this period, in the time of access external data memory, this twice effective signal will not occur;

4./VPP external reference allows end; Make CPU only access external program memory (address is 0000H～FFFFH), end must keep low level (receiving GND end); In the time that end keeps high level (connecing VSS end), CPU carries out the program in internal program memory;

(4) I/O pin P0.0～P0.7, P1.0～P1.7, P2.0～P2.7 and P3.0～P3.7

1. P0 port (P0.0～P0.7) P0 is a two-way I/O port of 8 open-drain types; As the delivery outlet used time, every potential energy drives 8 TTL inputs in the mode of Absorption Current, during to port write 1, can be used as again high impedance input;

2. P1 port (P1.0～P1.7) P1 is 8 two-way I/O ports with internal pull-up resistor; The output buffer of P1 can drive (absorbing or output current mode) 4 TTL inputs; During to port write 1, by inner pull-up resistor, port is moved to high potential, at this moment can be used as input port; While doing input port, because there is inner pull-up resistor, those pins that dragged down by external signal can be exported an electric current;

3. P2 port (P2.0～P2.7) P2 is 8 two-way I/O ports with internal pull-up resistor; The output buffer of P2 can drive (absorbing or output current mode) 4 TTL inputs; During to port write 1, by inner pull-up resistor, port is moved to high potential, at this moment can be used as input port; When P2 does input port use, because there is inner pull-up resistor, those pins that dragged down by external signal can be exported an electric current;

4. P3 port (P3.0～P3.7) P3 mouth pin is 8 two-way I/O mouths with internal pull-up resistor, can receive 4 TTL gate currents of output; When P3 mouth writes after " 1 ", they are drawn on inside as high level, and as input; As input, be low level because outside is drop-down, P3 mouth is by output current, and this is due to the cause of above drawing; P3 mouth also can be used as some specific functions of AT89S52.

3. port pinout dual-purpose function

P3.0RXD(serial input mouth)

P3.1TXD(serial delivery outlet)

P3.2(external interrupt 0)

P3.3(external interrupt 1)

The outside input of P3.4T0(timer 0)

The outside input of P3.5T1(timer 1)

P3.6(external data memory write gate)

P3.7(external data memory read gate)

A kind of intention electronic calendar of the present invention DS1302 clock circuit

DS1302 chip is introduced

Low-power Clock Chip DS1302 can carry out timing, and have the several functions such as leap year compensation year, month, day, hour, min, second; DS1302, for data record, on the record of the data point particularly some being acquired a special sense, can realize data and the time record simultaneously that occurs these data; Searching of the analysis of this record to for a long time continuous TT&C system result and the reason to abnormal data appearance is significant;

Adopt DS1302 as the data record recording in TT&C system, its software and hardware invention is simple, time interocclusal record accurate, both avoided continuous recording large workload, avoid again the blindness of time recording, give continuously the normal operation of long measurement, control system and check and all carried out very large convenience, can be widely used in the TT&C system of long-time continuous; In Measurement and Control System, particularly, in the TT&C system of long-time unattended duty, often need to record the time of some data that acquire a special sense and appearance thereof; Record and analyze the data of these Special Significance, the performance evaluation to TT&C system and normal operation have great importance; Traditional data record mode is every time sampling or timing sampling, there is no concrete time interocclusal record, therefore can only record data and time that cannot its appearance of accurate recording; If adopt single-chip microcomputer timing, need to adopt counter on the one hand, take hardware resource, need on the other hand to arrange interruption, inquiry etc., expend equally the resource of single-chip microcomputer, and some TT&C system may not allow; In system, adopt DS1302 can address this problem well;

The Performance Characteristics of DS1302

Real-time clock, can to second, point, time, day, week, the moon and with counting in the year that the leap year compensates;

For 31 × 8 temporary RAM of high-speed data;

Serial i/the O of minimum pins;

2.5～5.5V voltage power supply scope;

When 2.5V, power consumption is less than 300nA;

For single byte or multibyte (pulse mode) data mode of clock or RAM data read/write;

Simple 3 line interfaces;

Optionally at a slow speed charging (to VCC1) ability;

DS1302 clock chip comprises the static RAM (SRAM) of real-time clock/calendar and 31 bytes; It is through a simple serial line interface and microprocessor communication; Real-time clock/calendar provides second, point, time, day, week, Month And Year etc. information; Automatically adjust for the moon and the date at the end of month that are less than 31 days, also comprise the function of leap year correction; The operation of clock can adopt 24h or band AM(morning)/PM(afternoon) 12h form; Adopt three-wire interface and CPU to carry out synchronous communication, and can adopt burst mode once to transmit clock signal or the RAM data of multiple bytes; DS1302 has main power source/back-up source dual power supply pin: VCC1 provides low power supply in single supply and battery powered system, and lower powered battery backup is provided; VCC2 provides main power source in double power-supply system, and in this operational mode, VCC1 is connected to backup battery, so that can holding time information in the situation that there is no main power source and data; DS1302 is powered by the greater in VCC1 or VCC2; In the time that VCC2 is greater than VCC1+0.2V, VCC2 powers to DS1302; In the time that VCC2 is less than VCC1, DS1302 is powered by VCC1;

(2) DS1302 data manipulation principle

DS1302 must first initialize in the time that any data transmit, and RST pin is set to high level, then 8 bit address and command word is packed into shift register, and data are transfused at the rising edge of SCLK; No matter be read cycle or write cycle time, start 8 and specify in 40 registers which is accessed to; Starting 8 clock cycle, after command byte is packed into shift register, the other clock cycle is exported data, data writing in the time of write operation in the time of read operation; The number of clock pulses is 8 to add 8 under single byte mode, is 8 to add byte number under multibyte mode, and maximum can reach 248 byte numbers;

If be low level at the mid-RST of transport process, can stop the transmission of this secondary data, and I/O pin becomes high-impedance state; While powering on operation, before VCC is more than or equal to 2.5V, RST pin must keep low level; Only in the time that SCLK is low level;

Pin number pin name function

1

VCC2 main power source

2,3X1, X2 oscillation source, external 32768HZ crystal oscillator

4GND ground wire

5

Reset/chip select line

6I/O serial data input/output terminal (two-way)

7SCLK serial data input

8VCC1 back-up source

The highest significant position (position 7) of the control byte of DS1302 must be logical one; If it is logical zero, can not write data in DS1302; Position 6 if 0, represents access calendar clock data; Be 1 expression access RAM data; Position 5～1(A4～A0) instruction operating unit address; Least significant bit (position 0), as being 0, indicates to carry out write operation; Be that read operation is carried out in 1 expression; Control byte always starts I/O from lowest order;

In order to improve the addressability (address/command position 1～5=logical one) to 32 addresses, clock/calendar or ram register can be defined as to multibyte (burst) mode; Position 6 regulation clock or RAM, and position 0 regulation reads or writes; Data can not be stored in address 31 in address 9～31 or ram register in clock/calendar register; In multibyte mode, read or write from the position 0 of address 0; The order that must transmit by data is write 8 registers at first; But, in the time writing RAM in multibyte mode, needn't write all 31 bytes in order to transmit data; No matter whether write whole 31 bytes, each byte of writing all will be sent to RAM;

DS1302 has 12 registers, wherein has 7 registers and calendar, clock relevant, and the data bit of depositing is binary-coded decimal form, and its calendar, time register and control word thereof are in shown in Table 3-3, and wherein odd number is read operation, and even number is write operation.

4. register

Name command word value

The every content of scope

Write operation read operation 76543210

Second register 80H81H00-59CH10SECSEC

Minute register 82H83H00-59010MINMIN

Hour

Register 84H85H1-12 or

00-2312/

24010

APHRHR

Date

Register 86H87H01-28,29,

30,310010DATEDATE

Month register 88H89H01-12000IOMMONTH

Sunday register 8AH8BH01-0700000DAY

Time register 8CH8DH00-9910YEARYEAR

AM-PM/12-24 hour mode: the position 7 of hour register is defined as 12 or 24 hours modes and selects position; When it is high level, select 12 hours modes; Under this mode, position 5 is AM/PM positions, and this position represents PM while being high level, and low level represents AM, and under 24 hours modes, position 5 is second 10 hours position (20～23h);

Clock suspension: the position 7 definition bit clocks of second register suspend position; In the time that it is 1, the DS1302 failure of oscillations, enters the backup mode of low-power consumption; Conventionally in the time that DS1302 is carried out to write operation (as entering clock adjustment programme), the failure of oscillations; In the time that it is 0, clock will start to start;

The application of DS1302

Real-time timepiece chip DS1302 adopts serial data transmission, can be power down protection power supply programmable charge function is provided, also can charge closing function, and chip adopts 32768Hz crystal oscillator; Specify, stand-by power supply BT1 can be with battery or super capacitor (more than 100,000 μ F); Although DS1302 power consumption after main power source power down is very little, if ensure that for a long time clock is normal, preferably select miniature charging battery; If power-off time shorter (several hours or several days), can replace (when 100 μ F just can ensure 1 hour normally walking) [9] with the less common electrochemical capacitor of electric leakage; DS1302, after powering up for the first time, need carry out initialization operation; After initializing, just can adjust time and quarter-bell by normal method;

Memory circuit

1,2,3 pin of AT24C02 are three address wires, for determining the hardware address of chip; The 8th pin and the 4th pin are respectively positive and negative power supply; The 5th pin SDA is serial data I/O, and data are by this two-way I2C bus serial transfer; The 6th pin SCL is serial clock input line; SDA and SCL all need and positive supply between respectively connect on the resistance of a 4.7K and draw;

I2C bus is a kind of two-wire system bus for connecting between I2C device; It is by SDA(serial data line) and SCL(serial time clock line) two pieces line transmission information between the device of linking in bus, and according to the each device of Address Recognition: no matter be single-chip microcomputer, memory, lcd driver or keyboard interface.

The characteristic of 5.AT24C02

(1) basic structure of I2C bus

The single-chip microcomputer or the I2C device that adopt I2C bus standard, not only there is I2C interface circuit its inside, and each inside element circuit is divided into some relatively independent modules by function, realizes sheet choosing by software addressing, has reduced the connection of device chip select line; CPU can not only be affiliated to or pluck certain functional unit circuit from bus by instruction, also can detect the working condition of this unit, thereby realize not only simply but also flexibly expanding and control hardware system;

(2) interface features of transmitted in both directions

The sending and receiving of traditional Host μC serial interface is generally all respectively used a line, and I2C bus makes it can work in transmission or receive mode according to the function of device by software program; When certain device is when sending information in bus, its transmitter (being also main device), and when it is when bus receives information, become again receiver (also crying from device); Main device transmits data and produces clock with the open device transmitting for starting in bus, now any addressed device is all considered to from device; Address and data that the control of I2C bus is sent by the main device being articulated in bus completely determine;

It is not unalterable in bus, advocating peace from the relation of (being sending and receiving), but depends on the direction that now data transmit; SDA and SCL are two-way I/O line, connect positive supply by pull-up resistor; In the time that bus is idle, two lines are all high level; The output stage that connects the device of bus must be colelctor electrode or open-drain, to have wired AND function; The data transfer rate of I2C bus is 100kbit/s under standard operation mode, and under immediate mode, the highest transfer rate can reach 400kbit/s;

(3) clock signal in I2C bus

Clock sync signal in the time that I2C bus is uploaded carry information is to be completed by the logical “and” that is articulated in all devices on SCL clock line; On scl line, will have influence on these devices by high level to low level saltus step, once jump as low level under the clock signal of certain device, will make scl line keep low level always, and make all devices on scl line start low period; Now, the saltus step from low to high of the clock of the short device of low-level period can not affect the state of scl line, so these devices will enter the state that high level is waited for;

In the time that the clock signal of all devices all goes up jumping for high level, low period finishes, and scl line is released and returns to high level, and all devices all start their high period simultaneously; Thereafter, first device that finishes high period pulls into low level by scl line again; So just on scl line, produce a synchronised clock; Visible, clock low level time is determined by the longest device of clock low period, and clock high level time is determined by the shortest device of clock high period;

(4) transmission of data

In data transfer procedure, must confirm beginning and the end that data transmit; In the time that clock line SCL is high level, data wire SDA is that low level is defined as " beginning " signal by high level saltus step; In the time that scl line is high level, sda line generation low level is " end " signal to the saltus step of high level; Beginning and end signal are all to be produced by main device; After commencing signal, bus considered to be in busy condition; In a period of time after end signal, it is idle that bus is considered to.

The data transfer format of 6.I2C bus is: after I2C bus commencing signal, first byte data of sending is used for selecting from address of devices, and wherein first 7 is address code, and the 8th is direction position (R/W); Direction position is that " 0 " represents to send, and main device is write information selected from device; Direction position is that " 1 " represents that main device will be from from device read message; After commencing signal, the address that each device in system is delivered to the address of oneself and main device in bus compares, if with main device, to send to address in bus consistent, this device is by the device of main device addressing, and its reception information still sends information and determined by the 8th (R/W);

In I2C bus, each data word joint number transmitting is not limit, but each byte is necessary for 8, and must, with an authorization bit (the 9th), also be response bits (ACK) after the byte of each transmission; Be all first to pass highest order at every turn, conventionally can make response from device receiving each byte, discharge scl line and return to high level, prepare to receive next data byte, main device can continue to transmit; For example, if (processing an internal interrupt in the time that device is being processed a real-time event and can not receive data, before handling, this interruption just can not receive the data byte in I2C bus), can make clock scl line keep low level, must make SDA keep high level from device, now main device produces 1 end signal, make to transmit abnormal ending, force main device in wait state; In the time being disposed from device, will discharge scl line, main device continues to transmit;

When main device sends after the data of a byte, then send corresponding to a clock (ACK) authorization bit on scl line, in clock, main device discharges sda line at this moment, a byte transmits and finishes, and from the response signal of device, sda line is pulled into low level, make SDA is stable low level between the high period of this clock; From the response signal of device finishes, sda line returns to high level, enters the next transmission cycle;

(5) arbitration of bus contention

In bus, may be mounted with multiple devices, two or more main devices occur sometimes want to take simultaneously the situation of bus; For example, in multi-single-chip microcomputer system, may at a time have two single-chip microcomputers to want to send data to bus, this situation is called bus contention simultaneously; I2C bus has many master controls ability, can arbitrate the bus contention occurring on sda line, its arbitration principle is such: in the time that multiple main devices are wanted to take bus simultaneously, if certain main device sends high level, and another main device sends low level, transmission level will be closed its output stage automatically with that device that now SDA bus level is not inconsistent; The arbitration of bus contention is carried out on two levels; First be the comparison of address bit, if main device addressing is same from device, enter the comparison of data bit, thereby guaranteed the reliability of competition arbitration; Because being utilizes the information in I2C bus to arbitrate, therefore can not cause the loss of information;

The interface of 24C02 and single-chip microcomputer is very simple, A0, and A1, A2 is address of devices line, WP is write-protect pin, SCL, SDA is two-wire serial interface, meets I2C bus protocol;

Liquid crystal display circuit

Display part is made up of HD61202 LCD Controller and Driver and HY12864 liquid crystal display, below we are introduced respectively it;

The feature of LCD Controller and Driver HD61202

HD61202 LCD Controller and Driver is a kind of graphic lcd display controller with driver output, and it can directly be connected with 8-bit microprocessor, and it can coordinate liquid crystal display is carried out to row, column driving with HD61203; HD61202 is a kind of LCD controller with row driver output, and it can be used in conjunction with line driver HD61203, composition liquid crystal display driving control system [12];

(1) built-in 64 × 64=4096 position display random access memory, in RAM, bits per inch shields bright, the dark state of a upper point according to corresponding LCD;

(2) HD61202 is row driver, has 64 road row driver outputs;

(3) the HD61202 reading and writing time sequential routine conforms to 68 series microprocessors, and therefore it can directly be connected with 68 series microprocessor interfaces;

(4) dutycycle of HD61202 is 1/32～1/64.

7. the pin function of LCD Controller and Driver HD61202

Pin CS1, CS2, the sheet choosing end that CS3 is chip; Pin E is read-write enable signal, and its data in the time of trailing edge is latched into HD61202; Between E high period, data are read out; R/W selects signal for read-write, is to be read gate for the moment when it, is within 1 o'clock, to be write gate; DB0-DB7 is that data/address bus RST is reseting signal reset signal when effective, closes liquid crystal display, makes to show initial behavior 0, and RST can be connected with MCU, is controlled by MCU; Also can directly meet VDD;

Pin sign condition pin name function

CS1, CS2, CS3 input chip slapper choosing end CS1 and CS2 low level gating, CS3 high-level strobe;

E input read-write enable signal is at E trailing edge, and data are latched (writing) and enter HD61202; Between E high period, data are read out

It is read gate that signal R/W=1 is selected in R/W input read-write, and R/W=0 is write gate

It is data manipulation that signal RS=1 is selected in RS input data, instruction

RS=0 is write command or read states

DB0-DB7 tri-state data/address bus

When RST input reseting signal reset signal is effective, close liquid crystal display, make to show initial behavior 0, RST can be connected with MCU, is controlled by MCU; Also can directly meet VDD, make it inoperative;

The instruction system of LCD Controller and Driver HD61202

The instruction system of HD61202 is fairly simple, altogether only has seven kinds; Now be described below respectively;

(1) show ON/OFF instruction

R/WRSDB7DB6DB5DB4DB3DB2DB1DB0

0000111111/0

In the time of DBO=1, the content in LCD display random access memory; When DBO=0, close demonstration;

(2) show that initial row (ROW) arranges instruction

R/WRSDB7DB6DB5DB4DB3DB2DB1DB0

0011 shows initial row (0-63)

This instruction is provided with the line number of the display random access memory of the lastrow of corresponding liquid crystal display, and regular change shows initial row, can make LCD realize the effect that shows roll screen;

(3) page (PAGE) is put instruction

R/WRSDB7DB6DB5DB4DB3DB2DB1DB0

0010111 page number (0-7)

Display random access memory is totally 64 row, divides 8 pages, every page of 8 row;

(4) column address (YAddress) arranges instruction

R/WRSDB7DB6DB5DB4DB3DB2DB1DB0

0001 display column address (0-63)

Be provided with page address and column address, determined a unit in display random access memory with regard to unique, MCU just can read interior in this unit with reading and writing instruction and perhaps write into a byte data to this unit like this;

(5) read states instruction

R/WRSDB7DB6DB5DB4DB3DB2DB1DB0

10BUSY0ON/OFFREST0000

This instruction is used for inquiring about the state of HD61202, and each parameter implication is as follows:

BUSY:1-inside is in work 0-normal condition

ON/OFF:1-shows that closing 0-demonstration opens

REST:1-reset mode 0-normal condition

In the time of BUSY and REST state, except read states instruction, other instruction is not all to HD61202 generation effect; To inquire about BUSY state to before HD61202 operation, can operate HD61202 determining whether;

(6) write data command

R/WRSDB7DB6DB5DB4DB3DB2DB1DB0

01 writes data

Reading and writing data command often executes reading and writing operations, and column address just increases one automatically, and before must be noted that and carrying out read operation, once empty read operation, and then reads just can read the data in the unit that will read again;

Be connected; With HD61202(2) CS1 be connected, therefore, gating composite signal is ,=01 gating (1), ,=10 gatings (2); For HY-12864, as long as supply with VDD, VSS and V0, the required power supply of HD61202 and HD61203 will be produced by inside modules circuit under the effect of VDD and V0, VSS.

The application of 8.HY-12864

Following content is the interface circuit taking single-chip microcomputer 89S52 as example machine, the interface circuit that control circuit is Direct Access Mode; VSS ground connection; Connect+5V of digital power VDD; Contrast control voltage V0 connects potentiometer, can adjust liquid crystal brightness by regulator potentiometer; Data, instruction select signal RS to connect single-chip microcomputer P2.0 mouth; Read-write selects signal R/W to connect single-chip microcomputer P2.1 mouth; Single-chip microcomputer reading and writing gating signal, meet the read-write enable signal E of liquid crystal by NAND gate; DB0～DB7 connects respectively P0.0～P0.7 mouth of single-chip microcomputer; The sheet choosing of chip 1, chip 2 connects respectively P2.2, the P2.3 mouth of single-chip microcomputer; Reset terminal RST, connect+5V of positive supply LEDA backlight; Liquid crystal drive voltage VEE, negative supply LEDK ground connection backlight;

A kind of intention electronic calendar of the present invention adopts 3 of buttons altogether, is connected with P1.5, P1.6, the P1.7 mouth of single-chip microcomputer respectively, and corresponding cursor movement respectively, time, date adjustment, exit, the function of quarter-bell on & off switch.