CN206003078U

CN206003078U - A kind of modularity machine carried memory read-write equipment

Info

Publication number: CN206003078U
Application number: CN201620658664.1U
Authority: CN
Inventors: 张子明; 周勇军; 周章勇
Original assignee: State Run Wuhu Machinery Factory
Current assignee: State Run Wuhu Machinery Factory
Priority date: 2016-06-28
Filing date: 2016-06-28
Publication date: 2017-03-08
Anticipated expiration: 2026-06-28

Abstract

The utility model discloses a kind of modularity machine carried memory read-write equipment, including processor core control module FPGA, Memory connector module, UART serial communication interface module, power module, indicating lamp module, connector interface module, processor core control module FPGA respectively with Memory connector module, UART serial communication interface module, power module, indicating lamp module, connector interface module is connected, realize sending instruction and data interaction to processor core control module FPGA by UART serial communication interface module, processor core control module FPGA is connected with target memory by Memory connector module.This utility model, using the convenient Memory connector module section dismantled and install, adapts to the memorizer of various encapsulation, using modularized design, separation processor and target memory, contributes to secondary development, effectively expand range.

Description

A kind of modularity machine carried memory read-write equipment

Technical field

This utility model is related to a kind of storage read-write equipment, specifically a kind of modularity machine carried memory read-write dress Put.

Background technology

In present Avionic Products, the memorizer such as EPROM, EEPROM, FLASH has quite varied utilization, It is mainly used in program code and the data of storage control, so being flexibly written and read operation to memorizer is also avionics product The problem having in exploitation and repairing solve.Existing memory program device is general to pass through USB debugger using with computer The form connecting, user carrys out the program on read-write memory by using the application program being previously installed on computer, is criticizing There is very big advantage in the application of amount programming.But the memorizer species due to being related in avionics repairing trades and its various, Wherein more have much because of the remote past be already at end-of-life state, and these memory devices be all a small amount of read-write operation, Now common programmable device is difficult to be related to it is impossible to be competent at the reading writing working of memorizer very well comprehensively.

Content of the invention

In order to solve above-mentioned technical problem, this utility model provides a kind of modularity machine carried memory read-write equipment.

This utility model solves its technical problem and employs the following technical solutions to realize：

A kind of modularity machine carried memory read-write equipment, including processor core control module FPGA, Memory connector Module, UART serial communication interface module, power module, indicating lamp module, connector interface module, described processor core control Molding block FPGA respectively with Memory connector module, UART serial communication interface module, power module, indicating lamp module, connect Card i/f module is connected, and realizes sending instruction to processor core control module FPGA by UART serial communication interface module And data interaction, processor core control module FPGA is connected with target memory by Memory connector module, installs Dismounting is very convenient；Indicating lamp module is used for I/O digital signal output display, can be possible in debugging process for developer Produced problem provides and judges, can also indicate that system state in which in operation；Power module is processor core control Molding block FPGA provides various voltages, has specifically included 3.3V, 2.5V and 1.2V, using LMS1117 family chip to 5V voltage Carry out being converted to corresponding power supply, power module includes VCCIO interface, VCCA interface, VCCINT interface.

Processor core control module FPGA of the present utility model mainly completes storage operation sequential and response are used Family order and carry out the function of corresponding operating, processor core control module FPGA is by one piece of FPGA as core embedded processing Device, for different types of its reading and writing of memorizer designed in advance, erasing sequential.

Memory connector module is the polylith circuit board being fabricated to for adapting to the encapsulation of different kinds of memory, one Side is connected with processor core control module FPGA by unified Memory connector module, and opposite side is then according to different envelopes The memorizer fixture that dress makes, for fixing and linking objective memorizer.

Described processor core control module FPGA includes reset circuit, clock circuit, JTAG debugging circuit, jtag interface Circuit and CONFIG configuration circuit module, described reset circuit, clock circuit provide work for processor core control module FPGA Necessary reset, clock signal when making, JTAG debugging circuit, jtag interface circuit and CONFIG configuration circuit module are directed to and process The debugging of program of device kernel control module FPGA and solidification, JTAG debugging circuit, jtag interface circuit and CONFIG configuration electricity Road module needs to download in processor the programs such as the time sequential routine of memorizer and PC Communication by this mouth.

1 foot of the U1A module of described processor core control module FPGA, 2 feet, 3 feet, 4 feet, 7 feet, 10 feet, 11 feet divide Dui Ying not be with the A15 foot of the J9 module of Memory connector module, A16 foot, A17 foot, A18 foot, B19 foot, B20 foot, B21 foot phase Even.

28 feet of the U1B module of described processor core control module FPGA, 30 feet, 31 feet, 32 feet, 33 feet, 34 feet divide Dui Ying not be connected with the B22 foot B15 foot of the J9 module of Memory connector module, B16 foot, B17 foot, B18 foot, A20 foot.

38 feet of the U1C module of processor core control module FPGA, 39 feet, 42 feet correspond to and Memory connector respectively The A21 foot of the J9 module of module, A22 foot, A23 foot are connected, 43 feet of the U1C module of processor core control module FPGA, 44 Foot, 46 feet, 49 feet, 50 feet, the 51 feet B6 foot of J9 module of correspondence and Memory connector module, A8 foot, A24 foot, B14 respectively Foot, B13 foot, A6 foot are connected.

54 feet of the U1D module of processor core control module FPGA, 55 feet, 58 feet, 59 feet, 60 feet, 64 feet, 65 feet, 66 feet, 67 feet, 68 feet, 69 feet, 70 feet, 71 feet, 72 feet respectively the corresponding A13 foot of J9 module with Memory connector module, B12 foot, A12 foot, B11 foot, A11 foot, B10 foot, A10 foot, B9 foot, B4 foot, A4 foot, B3 foot, A3 foot, B2 foot, A2 foot are connected.

73 feet of the U1E module of processor core control module FPGA, 74 feet, 75 feet correspond to and Memory connector respectively The B1 foot of the J9 module of module, A1 foot, B24 foot be connected, 76 feet of the U1E module of processor core control module FPGA, 80 feet, 83 feet, 84 feet, 85 feet, 86 feet, 87 feet respectively corresponding 26 feet of J8 module with Memory connector module, 29 feet, 30 feet, 31 Foot, 32 feet, 33 feet, 34 feet are connected, 77 feet of the U1E module of processor core control module FPGA, 79 feet respectively corresponding with 12 feet of the U8 module of UART serial communication interface module, 11 feet are connected, the U1E module of processor core control module FPGA Correspondence is connected with 27 feet of the J8 module of Memory connector module, 28 feet respectively for 77 feet, 79 feet.Processor core control module 98 feet of the U1F module of FPGA, 99 feet, 100 feet, 101 feet, 103 feet, 104 feet are corresponding and Memory connector module respectively 35 feet of J8 module, 36 feet, 37 feet, 38 feet, 39 feet, 40 feet are connected, the U1F module of processor core control module FPGA Correspondence is connected with connector interface module respectively for 105 feet, 106 feet.The 110 of the U1G module of processor core control module FPGA Foot, 111 feet, 112 feet, 113 feet, 114 feet, 115 feet, 119 feet, 120 feet, 121 feet, 124 feet, 125 feet, 126 feet, 127 feet divide Dui Ying not be connected with connector interface module.128 feet of the U1H module of processor core control module FPGA, 129 feet, 132 Correspondence is connected with connector interface module respectively for foot, 133 feet, 135 feet of the U1H module of processor core control module FPGA, Correspondence is connected with indicating lamp module respectively for 136 feet, 137 feet, 138 feet, 141 feet, 142 feet, 143 feet, 144 feet.Processor core Correspondence is connected with reset circuit, clock circuit respectively for 24 feet of the U1I module of control module FPGA, 23 feet, processor core control 9 feet of the U1J module of molding block FPGA are connected with indicating lamp module after being serially connected with the 8th resistance R8.

14 feet of the U1J module of processor core control module FPGA, 92 feet, 12 feet, 21 feet and jtag interface circuit phase Even, 97 feet of the U1J module of processor core control module FPGA, 94 foot ground connection, the U1J of processor core control module FPGA 96 feet of module are connected with power module, 18 feet of the U1J module of processor core control module FPGA, 16 feet, 20 feet, 15 feet Correspondence is connected with JTAG debugging circuit respectively.

19 feet of the U1L module of processor core control module FPGA, 27 feet, 41 feet, 48 feet, 57 feet, 63 feet, 82 feet, 95 feet, 118 feet, 123 feet, 131 feet, 140 feet, 145 feet are all grounded, the CONFIG configuration electricity of processor core control module FPGA Road module is connected with power module.

35 feet of the U1M module of processor core control module FPGA, 107 feet are linked into the VCCIO interface of power module On, 37 feet of the U1M module of processor core control module FPGA, 109 feet are connected with CONFIG configuration circuit module, processor Correspondence is serially connected with the second inductance coil, the 3rd inductance coil respectively for 36 feet of the U1M module of kernel control module FPGA, 108 feet After be grounded.

17 feet of the U1K module of processor core control module FPGA, 26 feet, 40 feet, 47 feet, 56 feet, 62 feet, 81 feet, 93 feet, 117 feet, 122 feet, 130 feet, 139 feet are linked on the VCCIO interface of power module, processor core control module 5 feet of the U1K module of FPGA, 29 feet, 45 feet, 61 feet, 78 feet, 102 feet, 116 feet, 134 feet are linked into power module On VCCINT interface.

Clock circuit includes the first inductance coil, the first electric capacity, the second electric capacity, the second chip module, described first inductance One end of coil is connected with power module, and the other end of the first inductance coil is connected with 1 foot of the second chip module U2, the first electricity The positive pole holding is connected with 1 foot of the second chip module, the minus earth of the first electric capacity, one end of the second electric capacity and the second chip dies 1 foot of block is connected, and 2 feet of the other end of the second electric capacity and the second chip module are simultaneously grounded after connecing, the 1 of described second chip module Foot is connected with 4 feet, and 3 feet of described second chip module are connected with 23 feet of the U1I module of processor core control module FPGA.

Described reset circuit includes switching one, button switch one, the 3rd chip module, the 3rd electric capacity, 3rd resistor, described 1 foot of the 3rd chip module is concatenated with switch one and is followed by ground, after 1 foot of described 3rd chip module is concatenated with button switch one J1 It is linked on 8 feet of the 3rd chip module, be grounded after 2 feet of the 3rd chip module and the 3rd capacitance series, the 3rd chip module 2 feet be connected with power module, 3 feet of described 3rd chip module, 4 feet ground connection, 7 feet and the 3rd of described 3rd chip module On 24 feet of U1I module that resistance concatenation is followed by processor kernel control module FPGA.

Described JTAG debugging circuit includes debugging chip, the 4th resistance, the 5th resistance, the 6th resistance, described debugging chip 1 foot, 2 feet, 5 feet, 9 feet respectively corresponding 16 feet of U1J module with processor core control module FPGA, 20 feet, 18 feet, 15 Foot is connected, and 1 foot of described debugging chip is concatenated with the 4th resistance and is followed by ground, and 5 feet of described debugging chip are concatenated with the 6th resistance After be linked on power module, 9 feet of described debugging chip are concatenated with the 5th resistance and are followed by power module, described debugging 4 feet of chip are connected with power module, 2 feet of described debugging chip, 10 foot ground connection.

Described jtag interface circuit includes configuring chip, first resistor, second resistance, the 7th resistance, fourth chip, described 1 foot of configuration chip is connected with 12 feet of the U1J module of processor core control module FPGA, 3 feet and first of configuration chip Resistance concatenation is followed by the VCCIO interface of power module, configures 3 feet and processor core control module FPGA of chip 92 feet of U1J module are connected, and 5 feet of configuration chip are linked on the VCCIO interface of power module after being concatenated with second resistance, join 14 feet putting 5 feet of chip with the U1J module of processor core control module FPGA are connected, configuration 7 feet of chip J3,8 feet, 9 Foot is corresponded to respectively and is connected with 13 feet of the U1A module of processor core control module FPGA, 8 feet, 6 feet, configure chip 2 feet, 10 foot ground connection, 4 feet of configuration chip are linked on the VCCIO interface of power module, and 6 feet of configuration chip and the 7th resistance R7 go here and there It is grounded after connecing, 6 feet of configuration chip are connected with 21 feet of the U1J module of processor core control module FPGA, the 6 of fourth chip 12 feet of the U1J module of foot processor core control module FPGA are connected, 2 feet of fourth chip, 5 feet, 1 foot and processor core 13 feet of the U1A module of control module FPGA, 6 feet, 8 feet are connected, and 3 feet of fourth chip, 7 feet, 8 feet are linked into power module On VCCIO interface, 4 foot ground connection of fourth chip.

Described CONFIG configuration circuit module include the 4th inductance coil, the 4th electric capacity, the 5th electric capacity, the 6th electric capacity, Seven electric capacity, the 5th inductance coil, the 8th electric capacity, the 9th electric capacity, the tenth electric capacity, the 11st electric capacity, the 12nd electric capacity, the 13rd electricity Appearance, the 14th electric capacity, the 15th electric capacity, the 16th electric capacity, the 17th electric capacity, the 18th electric capacity, the 19th electric capacity, the 20th electricity Appearance, the 21st electric capacity, the 22nd electric capacity, the 23rd electric capacity, the 24th electric capacity, the 25th electric capacity, the 26th Electric capacity, the 27th electric capacity, the 28th electric capacity, the 29th electric capacity, the 30th electric capacity, the 31st electric capacity, the described 4th The positive pole of electric capacity is linked on the VCCINT interface of power module, the minus earth of the 4th electric capacity, the 5th electric capacity, the 6th electric capacity, The 7th electric capacity one end after connecing is connected with 37 feet of the U1M module of processor core control module FPGA, the 5th electric capacity, the 6th Electric capacity, the 7th electric capacity the ground connection of the other end after connecing, one end of the 4th inductance coil is linked into the VCCINT interface of power module On, one end of the 4th inductance coil is linked on 37 feet of the U1M module of processor core control module FPGA, described 8th electricity The positive pole holding is linked on the VCCINT interface of power module, the minus earth of described 8th electric capacity, described 9th electric capacity, the tenth Electric capacity, the 11st electric capacity the one end after connecing is connected with 109 feet of the U1M module of processor core control module FPGA, described 9th electric capacity, the tenth electric capacity, the 11st electric capacity the ground connection of the other end after connecing, one end of the 5th inductance coil is linked into power supply mould On the VCCINT interface of block, the other end of the 5th inductance coil is linked into the U1M module of processor core control module FPGA On 109 feet, the 12nd electric capacity, the 13rd electric capacity, the 14th electric capacity, the 15th electric capacity, the 16th electric capacity, the 17th electric capacity, 18 electric capacity, the 19th electric capacity the one end after connecing is linked on the VCCINT interface of power module, the 12nd electric capacity, the 13rd Electric capacity, the 14th electric capacity, the 15th electric capacity, the 16th electric capacity, the 17th electric capacity, the 18th electric capacity, the 19th electric capacity after connecing The other end ground connection, described 20th electric capacity, the 21st electric capacity, the 22nd electric capacity, the 23rd electric capacity, the 24th electricity Appearance, the 25th electric capacity, the 26th electric capacity, the 27th electric capacity, the 28th electric capacity, the 29th electric capacity, the 30th electricity Hold, the 31st electric capacity the one end after connecing are linked on the VCCIO interface of power module, described 20th electric capacity, the 20th One electric capacity, the 22nd electric capacity, the 23rd electric capacity, the 24th electric capacity, the 25th electric capacity, the 26th electric capacity, second 17 electric capacity, the 28th electric capacity, the 29th electric capacity, the 30th electric capacity, the 31st electric capacity the ground connection of the other end after connecing.

1 foot of the J8 module of Memory connector module, 2 feet, 3 feet, 4 feet, 5 feet, 6 feet correspond to and processor core respectively 43 feet of the U1C module of control module FPGA, 44 feet, 46 feet, 49 feet, 50 feet, 51 feet are connected, described Memory connector module 41 feet of J8 module, 42 feet, 43 feet, 44 feet, 45 feet are connected with 5V power supply respectively.

The A19 foot of the J9 module of Memory connector module is linked on the VCCIO interface of power module.

UART serial communication interface module include the 8th chip module, the first link block, the 44th electric capacity, the 40th Five electric capacity, the 46th electric capacity, the 47th electric capacity, the 48th electric capacity, the positive pole of described 44th electric capacity and the 8th core 1 foot of piece module is connected, and the negative pole of the 44th electric capacity is connected with 3 feet of the 8th chip module, described 45th electric capacity Positive pole is connected with 4 feet of the 8th chip module, and the negative pole of described 45th electric capacity is connected with 5 feet of the 8th chip module, institute State the plus earth of the 46th electric capacity, the negative pole of the 46th electric capacity is connected with 6 feet of the 8th chip module, the described 40th The positive pole of seven electric capacity is connected with 2 feet of the 8th chip module, the negative pole of described 47th electric capacity and the 16 of the 8th chip module Foot is connected, and the positive pole of the 48th electric capacity is connected with 16 feet of the 8th chip module, the minus earth of the 48th electric capacity C48, 15 foot ground connection of the 8th chip module, 12 feet of the 8th chip module, 11 feet correspond to and processor core control module respectively 77 feet of the U1E module of FPGA, 79 feet are connected, and 14 feet of the 8th chip module, 13 feet correspond to 3 with the first link block respectively Foot, 2 feet are connected, 5 foot ground connection of the first link block.

Connector interface module includes the second link block, the 3rd link block, the 4th link block, the second link block 1 foot be linked on 5V power supply, 2 feet ground connection of the second link block, 1 foot of the 3rd link block, 2 feet respectively corresponding with process 105 feet of the U1F module of device kernel control module FPGA, 106 feet be connected, 3 feet of the 3rd link block, 4 feet, 5 feet, 6 feet, 7 Foot, 8 feet, 9 feet, 10 feet, 11 feet, 12 feet, 13 feet, 14 feet, the 15 feet corresponding U1G with processor core control module FPGA respectively 110 feet of module, 111 feet, 112 feet, 113 feet, 114 feet, 115 feet, 119 feet, 120 feet, 121 feet, 124 feet, 125 feet, 126 Foot, 127 feet are connected, and 16 feet of the 3rd link block J12,17 feet, 18 feet, 19 feet correspond to and processor core control module respectively 128 feet of the U1H module of FPGA, 129 feet, 132 feet, 133 feet are connected, and 20 feet of the 3rd link block J12,21 feet, 22 feet divide It is not linked on 5V power supply, 23 feet of the 3rd link block J12,24 feet, 25 feet, 26 feet are all grounded, described 4th link block 1 foot of J13,2 feet, 3 feet, 4 feet, 5 feet, 6 feet, 7 feet correspond to 1 with the U1A module of processor core control module FPGA respectively Foot, 2 feet, 3 feet, 4 feet, 7 feet, 10 feet, 11 feet are connected, and 8 feet of the 4th link block, 9 feet, 10 feet, 11 feet, 12 feet, 13 feet divide Dui Ying not be connected with 28 feet of the U1B module of processor core control module FPGA, 30 feet, 31 feet, 32 feet, 33 feet, 34 feet.

14 feet of the 4th link block J13,15 feet, the 16 feet corresponding U1C with processor core control module FPGA respectively 38 feet of module, 39 feet, 42 feet are connected, and 17 feet of the 4th link block, 18 feet, 19 feet, 20 feet are all grounded.

Indicating lamp module include the 27th resistance, the 28th resistance, the 29th resistance, the 30th resistance, the 3rd 11 resistance, the 32nd resistance, the 33rd resistance, the 34th resistance, the 9th resistance, the first LED, the second LED, 3rd LED, the 4th LED, the 5th LED, the 6th LED, the 7th LED, the 8th LED, the 9th LED, described The negative pole of one LED is grounded after being concatenated with the 9th resistance R9, and the positive pole of the first LED is linked on 5V power supply, the second LED Negative pole concatenates on 135 feet of the U1H module being followed by processor kernel control module FPGA with the 27th resistance, and the 3rd The negative pole of LED concatenates, with the 28th resistance, 136 feet being followed by into the U1H module to processor kernel control module FPGA On, the negative pole of the 4th LED concatenates, with the 9th resistance, 137 being followed by into the U1H module to processor kernel control module FPGA On foot, the negative pole of the 5th LED is concatenated with the 30th resistance and is followed by into the U1H module to processor kernel control module FPGA On 138 feet, the negative pole of the 6th LED concatenates, with the 31st resistance, the U1H being followed by into processor kernel control module FPGA On 139 feet of module, the negative pole of the 7th LED is concatenated with the 32nd resistance and is followed by into processor kernel control module FPGA 140 feet of U1H module on, the negative pole of the 8th LED concatenate with the 33rd resistance be followed by into processor core control mould On 141 feet of the U1H module of block FPGA, the negative pole of the 9th LED is concatenated with the 34th resistance and is followed by into processor core On 142 feet of the U1H module of control module FPGA, the second LED, the 3rd LED, the 4th LED, the 5th LED, the 6th LED, the 7th LED, the 8th LED, the positive pole of the 9th LED are all linked on the VCCIO interface of power module.

Power module includes 3.3V power circuit, 2.5V power circuit and 1.2V power circuit, described 3.3V power circuit Including the first power supply chip, the 32nd electric capacity, the 33rd electric capacity, the 34th electric capacity, the 35th electric capacity, button switch Two, 1 foot ground connection of the first power supply chip, it is grounded after 3 feet of the first power supply chip and the 33rd capacitance series, the 32nd electricity The positive pole holding is connected with 3 feet of the first power supply chip, the minus earth of the 32nd electric capacity, and 3 feet of the first power supply chip access To on 5V power supply, it is grounded after 2 feet of the first power supply chip and the 34th capacitance series, the positive pole and first of the 35th electric capacity 2 feet of power supply chip are connected, and the minus earth of the 35th electric capacity, after 2 feet of the first power supply chip are concatenated with button switch two Form VCCIO interface.

2.5V power circuit include second source chip, the 40th electric capacity, the 41st electric capacity, the 42nd electric capacity, 43 electric capacity, button switch three, 1 foot ground connection, the positive pole of the 40th electric capacity and the second source core of described second source chip 3 feet of piece are connected, and the minus earth of the 40th electric capacity is grounded after 3 feet of second source chip and the 41st capacitance series, the 3 feet of two power supply chips are linked on 5V power supply, are grounded, the 4th after 2 feet of second source chip and the 42nd capacitance series The positive pole of 13 electric capacity is connected with 2 feet of second source chip, the minus earth of the 43rd electric capacity, and the 2 of second source chip Foot forms VCCA interface after concatenating with button switch three.

1.2V power circuit include the 3rd power supply chip, the 36th electric capacity, the 37th electric capacity, the 38th electric capacity, 39th electric capacity, button switch four, 1 foot ground connection, the positive pole of the 36th electric capacity and the 3rd electricity of described 3rd power supply chip 3 feet of source chip are connected, and the minus earth of the 36th electric capacity, after 3 feet of the 3rd power supply chip and the 37th capacitance series Ground connection, ground connection, the positive pole of the 39th electric capacity and the 3rd power supply core after 2 feet of the 3rd power supply chip and the 38th capacitance series 2 feet of piece are connected, the minus earth of the 39th electric capacity, and 2 feet of the 3rd power supply chip are formed after being concatenated with button switch four VCCINT interface.

The beneficial effects of the utility model are：

This utility model, using the convenient Memory connector module section dismantled and install, adapts to the storage of various encapsulation Device, solves the problems, such as that traditional programmable device can only operate limited encapsulation, and the feature that can dismount also makes this device when using Volume and weight can be reduced；

Adopt FPGA as core processor can with its pin of effectively utilizes can with flexible configuration, the speed of service is fast, be easy to The features such as exploitation, for producing various sequential level, reserve debugging jtag interface simultaneously, read-write memory can be wanted in increase When re-download program meet require；

This utility model adopts modularized design, separation processor and target memory, so can carry out processor Secondary development, in the work for such as digital signal acquiring, the range of effective expansion instrument.

Brief description

With reference to the accompanying drawings and examples this utility model is further illustrated.

The systematic schematic diagram that Fig. 1 is connected with external computer for this utility model；

Fig. 2 is the U1A module of processor core control module FPGA of the present utility model, U1B module, U1C module, U1D The structural representation of module；

Fig. 3 is the U1E module of processor core control module FPGA of the present utility model, U1F module, U1G module, U1H The structural representation of module；

Fig. 4 is the U1I module of processor core control module FPGA of the present utility model, U1J module, U1L module, U1M The structural representation of module；

Fig. 5 is the structural representation of the U1K module of processor core control module FPGA of the present utility model；

Fig. 6 is the structural representation of clock circuit of the present utility model, reset circuit；

Fig. 7 is the structural representation of JTAG debugging circuit of the present utility model；

Fig. 8 is the structural representation of jtag interface circuit of the present utility model；

Fig. 9 is the part-structure schematic diagram one of CONFIG configuration circuit module of the present utility model；

Figure 10 is the part-structure schematic diagram two of CONFIG configuration circuit module of the present utility model；

Figure 11 is the part-structure schematic diagram one of Memory connector of the present utility model；

Figure 12 is the part-structure schematic diagram two of Memory connector of the present utility model；

Figure 13 is the structural representation of UART serial communication interface module of the present utility model；

Figure 14 is the structural representation of connector interface module of the present utility model；

Figure 15 is indicating lamp module part-structure schematic diagram one of the present utility model；

Figure 16 is indicating lamp module part-structure schematic diagram two of the present utility model；

Figure 17 is power module structure schematic diagram of the present utility model.

Specific embodiment

In order that the purpose of this utility model, technical scheme and beneficial effect are clearer, below in conjunction with accompanying drawing, to this The preferred embodiment of utility model is described in detail, and this utility model is described further, to facilitate technical staff to manage Solution.

As shown in Fig. 1 to Figure 17, a kind of modularity machine carried memory read-write equipment, including processor core control module FPGA, Memory connector module, UART serial communication interface module, power module, indicating lamp module, connector interface mould Block, described processor core control module FPGA respectively with Memory connector module, UART serial communication interface module, power supply Module, indicating lamp module, connector interface module are connected, and UART serial communication interface module is used for external computer to process Device kernel control module FPGA sends instruction and data interaction, and processor core control module FPGA passes through Memory connector Module is connected with target memory, and installing/dismounting is very convenient；Indicating lamp module is used for I/O digital signal output display, permissible There is provided for the problem that developer is likely to occur in debugging process and judge, can also indicate that the shape in operation residing for system State；Power module provides various voltages for processor core control module FPGA, has specifically included 3.3V, 2.5V and 1.2V, has made With LMS1117 family chip, 5V voltage is carried out being converted to corresponding power supply, power module include VCCIO interface, VCCA interface, VCCINT interface.

73 feet of the U1E module of processor core control module FPGA, 74 feet, 75 feet correspond to and Memory connector respectively The B1 foot of the J9 module of module, A1 foot, B24 foot be connected, 76 feet of the U1E module of processor core control module FPGA, 80 feet, 83 feet, 84 feet, 85 feet, 86 feet, 87 feet respectively corresponding 26 feet of J8 module with Memory connector module, 29 feet, 30 feet, 31 Foot, 32 feet, 33 feet, 34 feet are connected, 77 feet of the U1E module of processor core control module FPGA, 79 feet respectively corresponding with 12 feet of the U8 module of UART serial communication interface module, 11 feet are connected, the U1E module of processor core control module FPGA Correspondence is connected with 27 feet of the J8 module of Memory connector module, 28 feet respectively for 77 feet, 79 feet.

98 feet of the U1F module of processor core control module FPGA, 99 feet, 100 feet, 101 feet, 103 feet, 104 feet divide Dui Ying not be connected with 35 feet of the J8 module of Memory connector module, 36 feet, 37 feet, 38 feet, 39 feet, 40 feet, processor core Correspondence is connected with connector interface module respectively for 105 feet of the U1F module of heart control module FPGA, 106 feet.

110 feet of the U1G module of processor core control module FPGA, 111 feet, 112 feet, 113 feet, 114 feet, 115 feet, Correspondence is connected with connector interface module respectively for 119 feet, 120 feet, 121 feet, 124 feet, 125 feet, 126 feet, 127 feet.

128 feet of the U1H module of processor core control module FPGA, 129 feet, 132 feet, 133 feet correspond to respectively and connect Card i/f module be connected, 135 feet of the U1H module of processor core control module FPGA, 136 feet, 137 feet, 138 feet, 141 Correspondence is connected with indicating lamp module respectively for foot, 142 feet, 143 feet, 144 feet.

24 feet of the U1I module of processor core control module FPGA, 23 feet correspond to and reset circuit, clock circuit respectively It is connected, 9 feet of the U1J module of processor core control module FPGA are connected with indicating lamp module after being serially connected with the 8th resistance R8.

35 feet of the U1M module of processor core control module FPGA, 107 feet are linked into the VCCIO interface of power module On, 37 feet of the U1M module of processor core control module FPGA, 109 feet are connected with CONFIG configuration circuit module, processor Correspondence is serially connected with the second inductance coil L2, the 3rd inductor wire respectively for 36 feet of the U1M module of kernel control module FPGA, 108 feet It is grounded after circle L3.

Clock circuit includes the first inductance coil L1, the first electric capacity C1, the second electric capacity C2, the second chip module U2, described One end of first inductance coil L1 is connected with power module, and the 1 of the other end of the first inductance coil L1 and the second chip module U2 Foot is connected, and the positive pole of the first electric capacity C1 is connected with 1 foot of the second chip module U2, the minus earth of the first electric capacity C1, the second electricity The one end holding C2 is connected with 1 foot of the second chip module U2, and 2 feet of the other end of the second electric capacity C2 and the second chip module U2 are simultaneously It is grounded after connecing, 1 foot of described second chip module U2 is connected with 4 feet, 3 feet of described second chip module U2 and processor core 23 feet of the U1I module of control module FPGA are connected.

Described reset circuit include switching a S1, button switch one J1, the 3rd chip module U3, the 3rd electric capacity C3, the 3rd Resistance R3,1 foot of described 3rd chip module U3 with switch one S1 concatenate after ground connection, 1 foot of described 3rd chip module U3 and It is linked on 8 feet of the 3rd chip module U3 after button switch one J1 concatenation, 2 feet of the 3rd chip module U3 and the 3rd electric capacity C3 It is grounded after concatenation, 2 feet of the 3rd chip module U3 are connected with power module, 3 feet of described 3rd chip module U3,4 foot ground connection, 7 feet of described 3rd chip module U3 access the U1I mould managing device kernel control module FPGA everywhere with 3rd resistor R3 after concatenating On 24 feet of block.

Described JTAG debugging circuit includes debugging chip J2, the 4th resistance R4, the 5th resistance R5, the 6th resistance R6, described Debugging 1 foot of chip J2,2 feet, 5 feet, 9 feet respectively corresponding 16 feet of U1J module with processor core control module FPGA, 20 Foot, 18 feet, 15 feet are connected, and 1 foot of described debugging chip J2 is grounded after being concatenated with the 4th resistance R4, and the 5 of described debugging chip J2 Foot is linked on power module after being concatenated with the 6th resistance R6, and 9 feet of described debugging chip J2 are concatenated with the 5th resistance R5 and are followed by Enter on power module, 4 feet of described debugging chip J2 are connected with power module, 2 feet of described debugging chip J2,10 feet connect Ground.

Described jtag interface circuit include configure chip J3, first resistor R1, second resistance R2, the 7th resistance R7, the 4th Chip U4,1 foot of described configuration chip J3 is connected with 12 feet of the U1J module of processor core control module FPGA, configures core 3 feet of piece J3 are linked into after being concatenated with first resistor R1 on the VCCIO interface of power module, configure 3 feet and the process of chip J3 92 feet of the U1J module of device kernel control module FPGA are connected, and 5 feet of configuration chip J3 are linked into after being concatenated with second resistance R2 On the VCCIO interface of power module, 14 feet of 5 feet of configuration chip J3 and the U1J module of processor core control module FPGA Be connected, configuration 7 feet of chip J3,8 feet, 9 feet respectively corresponding 13 feet of U1A module with processor core control module FPGA, 8 Foot, 6 feet are connected, 2 feet of configuration chip J3,10 foot ground connection, and 4 feet of configuration chip J3 are linked into the VCCIO interface of power module On, 6 feet of configuration chip J3 are grounded after being concatenated with the 7th resistance R7, configure 6 feet and the processor core control module of chip J3 21 feet of the U1J module of FPGA are connected, 12 feet of the U1J module of 6 foot processor core control modules FPGA of fourth chip U4 It is connected, 13 feet of 2 feet of fourth chip U4,5 feet, 1 foot and the U1A module of processor core control module FPGA, 6 feet, 8 foot phases Even, 3 feet of fourth chip U4,7 feet, 8 feet are linked on the VCCIO interface of power module, 4 foot ground connection of fourth chip U4.

Described CONFIG configuration circuit module includes the 4th inductance coil L4, the 4th electric capacity C4, the 5th electric capacity C5, the 6th electricity Hold C6, the 7th electric capacity C7, the 5th inductance coil L5, the 8th electric capacity C8, the 9th electric capacity C9, the tenth electric capacity C10, the 11st electric capacity C11, the 12nd electric capacity C12, the 13rd electric capacity C13, the 14th electric capacity C14, the 15th electric capacity C15, the 16th electric capacity C16, 17 electric capacity C17, the 18th electric capacity C18, the 19th electric capacity C19, the 20th electric capacity C20, the 21st electric capacity C21, the 20th Two electric capacity C22, the 23rd electric capacity C23, the 24th electric capacity C24, the 25th electric capacity C25, the 26th electric capacity C26, 27 electric capacity C27, the 28th electric capacity C28, the 29th electric capacity C29, the 30th electric capacity C30, the 31st electric capacity C31, The positive pole of described 4th electric capacity C4 is linked on the VCCINT interface of power module, the minus earth of the 4th electric capacity C4, the 5th electricity 37 feet of the U1M module of the one end after holding C5, the 6th electric capacity C6, the 7th electric capacity C7 and connecing and processor core control module FPGA It is connected, the 5th electric capacity C5, the 6th electric capacity C6, the 7th electric capacity C7 the ground connection of the other end after connecing, one end of the 4th inductance coil L4 It is linked on the VCCINT interface of power module, one end of the 4th inductance coil L4 is linked into processor core control module FPGA 37 feet of U1M module on, the positive pole of described 8th electric capacity C8 is linked on the VCCINT interface of power module, described 8th electricity Hold the minus earth of C8, described 9th electric capacity C9, the tenth electric capacity C10, the 11st electric capacity C11 the one end after connecing and processor core 109 feet of the U1M module of heart control module FPGA are connected, and described 9th electric capacity C9, the tenth electric capacity C10, the 11st electric capacity C11 are simultaneously Other end ground connection after connecing, one end of the 5th inductance coil L5 is linked on the VCCINT interface of power module, the 5th inductor wire On 109 feet of U1M module that the other end of circle L5 is linked into processor core control module FPGA, the 12nd electric capacity C12, the tenth Three electric capacity C13, the 14th electric capacity C14, the 15th electric capacity C15, the 16th electric capacity C16, the 17th electric capacity C17, the 18th electric capacity C18, the 19th electric capacity C19 the one end after connecing is linked on the VCCINT interface of power module, the 12nd electric capacity C12, the tenth Three electric capacity C13, the 14th electric capacity C14, the 15th electric capacity C15, the 16th electric capacity C16, the 17th electric capacity C17, the 18th electric capacity C18, the 19th electric capacity C19 the ground connection of the other end after connecing, described 20th electric capacity C20, the 21st electric capacity C21, the 20th Two electric capacity C22, the 23rd electric capacity C23, the 24th electric capacity C24, the 25th electric capacity C25, the 26th electric capacity C26, 27 electric capacity C27, the 28th electric capacity C28, the 29th electric capacity C29, the 30th electric capacity C30, the 31st electric capacity C31 are simultaneously One end after connecing is linked on the VCCIO interface of power module, described 20th electric capacity C20, the 21st electric capacity C21, second 12 electric capacity C22, the 23rd electric capacity C23, the 24th electric capacity C24, the 25th electric capacity C25, the 26th electric capacity C26, 27th electric capacity C27, the 28th electric capacity C28, the 29th electric capacity C29, the 30th electric capacity C30, the 31st electric capacity C31 And the other end ground connection after connecing.

UART serial communication interface module includes the 8th chip module U8, the first link block J14, the 44th electric capacity C44, the 45th electric capacity C45, the 46th electric capacity C46, the 47th electric capacity C47, the 48th electric capacity C48, the described 4th The positive pole of 14 electric capacity C44 is connected with 1 foot of the 8th chip module U8, the negative pole of the 44th electric capacity C44 and the 8th chip dies 3 feet of block U8 are connected, and the positive pole of described 45th electric capacity C45 is connected with 4 feet of the 8th chip module U8, and the described 45th The negative pole of electric capacity C45 is connected with 5 feet of the 8th chip module U8, the plus earth of described 46th electric capacity C46, and the 46th The negative pole of electric capacity C46 is connected with 6 feet of the 8th chip module U8, the positive pole of described 47th electric capacity C47 and the 8th chip dies 2 feet of block U8 are connected, and the negative pole of described 47th electric capacity C47 is connected with 16 feet of the 8th chip module U8, the 48th electricity The positive pole holding C48 is connected with 16 feet of the 8th chip module U8, the minus earth of the 48th electric capacity C48, the 8th chip module The 15 foot ground connection of U8,12 feet of the 8th chip module U8, the 11 feet corresponding U1E mould with processor core control module FPGA respectively 77 feet of block, 79 feet are connected, 14 feet of the 8th chip module U8,13 feet 3 feet of correspondence and the first link block J14,2 feet respectively It is connected, 5 foot ground connection of the first link block J14.

Connector interface module includes the second link block J11, the 3rd link block J12, the 4th link block J13, the 1 foot of two link blocks J11 is linked on 5V power supply, 2 foot ground connection of the second link block J11, and the 1 of the 3rd link block J12 Correspondence is connected with 105 feet of the U1F module of processor core control module FPGA, 106 feet respectively for foot, 2 feet, the 3rd link block 3 feet of J12,4 feet, 5 feet, 6 feet, 7 feet, 8 feet, 9 feet, 10 feet, 11 feet, 12 feet, 13 feet, 14 feet, 15 feet are corresponding respectively and process 110 feet of the U1G module of device kernel control module FPGA, 111 feet, 112 feet, 113 feet, 114 feet, 115 feet, 119 feet, 120 feet, 121 feet, 124 feet, 125 feet, 126 feet, 127 feet are connected, and 16 feet of the 3rd link block J12,17 feet, 18 feet, 19 feet are right respectively Should be connected with 128 feet of the U1H module of processor core control module FPGA, 129 feet, 132 feet, 133 feet, the 3rd link block 20 feet of J12,21 feet, 22 feet are respectively connected on 5V power supply, and 23 feet of the 3rd link block J12,24 feet, 25 feet, 26 feet are equal Ground connection, 1 foot of described 4th link block J13,2 feet, 3 feet, 4 feet, 5 feet, 6 feet, 7 feet are corresponding respectively to be controlled with processor core 1 foot of the U1A module of module FPGA, 2 feet, 3 feet, 4 feet, 7 feet, 10 feet, 11 feet are connected, 8 feet of the 4th link block J13,9 Foot, 10 feet, 11 feet, 12 feet, 13 feet respectively corresponding 28 feet of U1B module with processor core control module FPGA, 30 feet, 31 Foot, 32 feet, 33 feet, 34 feet are connected.

14 feet of the 4th link block J13,15 feet, the 16 feet corresponding U1C with processor core control module FPGA respectively 38 feet of module, 39 feet, 42 feet are connected, and 17 feet of the 4th link block J13,18 feet, 19 feet, 20 feet are all grounded.

Indicating lamp module include the 27th resistance R27, the 28th resistance R28, the 29th resistance R29, the 30th Resistance R30, the 31st resistance R31, the 32nd resistance R32, the 33rd resistance R33, the 34th resistance R34, the 9th Resistance R9, the first LED D1, the second LED D19, the 3rd LED D20, the 4th LED D21, the 5th LED D22, the 6th LED D23, the 7th LED D24, the 8th LED D25, the 9th LED D26, the negative pole of described first LED D1 and the 9th electricity It is grounded after resistance R9 concatenation, the positive pole of the first LED D1 is linked on 5V power supply, and the negative pole of the second LED D19 is electric with the 27th Access after resistance R27 concatenation on 135 feet of U1H module managing device kernel control module FPGA everywhere, the negative pole of the 3rd LED D20 Access on 136 feet of U1H module managing device kernel control module FPGA everywhere after concatenating with the 28th resistance R28, the 4th LED The negative pole of lamp D21 accesses on 137 feet of U1H module managing device kernel control module FPGA everywhere after concatenating with the 9th resistance R9, The negative pole of the 5th LED D22 accesses the U1H module managing device kernel control module FPGA everywhere with the 30th resistance R30 after concatenating 138 feet on, the negative pole of the 6th LED D23 access after concatenating with the 31st resistance R31 everywhere reason device kernel control module On 139 feet of the U1H module of FPGA, the negative pole of the 7th LED D24 accesses reason device everywhere with the 32nd resistance R32 after concatenating On 140 feet of the U1H module of kernel control module FPGA, after the negative pole of the 8th LED D25 is concatenated with the 33rd resistance R33 On 141 feet of the U1H module being linked into processor core control module FPGA, the negative pole of the 9th LED D26 and the 34th electricity Access everywhere on 142 feet of U1H module of reason device kernel control module FPGA after resistance R34 concatenation, the second LED D19, the 3rd LED D20, the 4th LED D21, the 5th LED D22, the 6th LED D23, the 7th LED D24, the 8th LED D25, The positive pole of nine LED D26 is all linked on the VCCIO interface of power module.

Power module includes 3.3V power circuit, 2.5V power circuit and 1.2V power circuit, described 3.3V power circuit Including the first power supply chip U5, the 32nd electric capacity C32, the 33rd electric capacity C33, the 34th electric capacity C34, the 35th electricity Hold C35, button switch two J4,1 foot ground connection, 3 feet of the first power supply chip U5 and the 33rd electric capacity of the first power supply chip U5 It is grounded after C33 concatenation, the positive pole of the 32nd electric capacity C32 is connected with 3 feet of the first power supply chip U5, the 32nd electric capacity C32 Minus earth, 3 feet of the first power supply chip U5 are linked on 5V power supply, 2 feet of the first power supply chip U5 and the 34th electricity It is grounded after holding C34 concatenation, the positive pole of the 35th electric capacity C35 is connected with 2 feet of the first power supply chip U5, the 35th electric capacity The minus earth of C35,2 feet of the first power supply chip U5 form VCCIO interface after concatenating with button switch two J4.

2.5V power circuit include second source chip U6, the 40th electric capacity C40, the 41st electric capacity C41, the 42nd Electric capacity C42, the 43rd electric capacity C43, button switch three J5, the 1 foot ground connection of described second source chip U6, the 40th electric capacity The positive pole of C40 is connected with 3 feet of second source chip U6, the minus earth of the 40th electric capacity C40, and the 3 of second source chip U6 Foot is grounded after being concatenated with the 41st electric capacity C41, and 3 feet of second source chip U6 are linked on 5V power supply, second source chip 2 feet of U6 are grounded after being concatenated with the 42nd electric capacity C42,2 feet of the positive pole of the 43rd electric capacity C43 and second source chip U6 It is connected, the minus earth of the 43rd electric capacity C43,2 feet of second source chip U6 are formed after being concatenated with button switch three J5 VCCA interface.

1.2V power circuit include the 3rd power supply chip U7, the 36th electric capacity C36, the 37th electric capacity C37, the 30th Eight electric capacity C38, the 39th electric capacity C39, button switch four J6, the 1 foot ground connection of described 3rd power supply chip U7, the 36th electricity The positive pole holding C36 is connected with 3 feet of the 3rd power supply chip U7, the minus earth of the 36th electric capacity C36, the 3rd power supply chip U7 3 feet concatenate with the 37th electric capacity C37 after ground connection, 2 feet of the 3rd power supply chip U7 are concatenated with the 38th electric capacity C38 and are followed by Ground, the positive pole of the 39th electric capacity C39 is connected with 2 feet of the 3rd power supply chip U7, the minus earth of the 39th electric capacity C39, 2 feet of the 3rd power supply chip U7 form VCCINT interface after concatenating with button switch four J6.

This utility model entirety stable degree higher, simultaneously plate circuit be designed to prevent by anti-inserted for plate cause short circuit and then Circuit and chip are produced and destroys.

Finally illustrate, preferred embodiment above only in order to the technical solution of the utility model to be described and unrestricted, to the greatest extent Gutron is crossed above preferred embodiment and this utility model is described in detail, but those skilled in the art should manage Solution, can make various changes, in the form and details without departing from this utility model claims institute to it The scope limiting.

Claims

1. a kind of modularity machine carried memory read-write equipment, including processor core control module FPGA, Memory connector mould Block, UART serial communication interface module, power module, indicating lamp module, connector interface module it is characterised in that：Described place Reason device kernel control module FPGA respectively with Memory connector module, UART serial communication interface module, power module, instruction Lamp module, connector interface module are connected, and are realized to processor core control module by UART serial communication interface module FPGA sends instruction and data interaction, and processor core control module FPGA is passed through Memory connector module and stored with target Device be connected, power module be processor core control module FPGA provide various voltages, power module include VCCIO interface, VCCA interface, VCCINT interface.

2. a kind of modularity machine carried memory read-write equipment according to claim 1 it is characterised in that：Described processor core Heart control module FPGA includes reset circuit, clock circuit, JTAG debugging circuit, jtag interface circuit and CONFIG configuration circuit Module, necessary reset, clock letter when described reset circuit, clock circuit provide work for processor core control module FPGA Number, JTAG debugging circuit, jtag interface circuit and CONFIG configuration circuit module are directed to processor core control module FPGA The debugging of program and solidification.

3. a kind of modularity machine carried memory read-write equipment according to claim 2 it is characterised in that：Described processor core 1 foot of the U1A module of heart control module FPGA, 2 feet, 3 feet, 4 feet, 7 feet, 10 feet, 11 feet correspond to and Memory connector respectively The A15 foot of the J9 module of module, A16 foot, A17 foot, A18 foot, B19 foot, B20 foot, B21 foot are connected；

28 feet of the U1B module of described processor core control module FPGA, 30 feet, 31 feet, 32 feet, 33 feet, 34 feet are right respectively Should be connected with the B22 foot B15 foot of the J9 module of Memory connector module, B16 foot, B17 foot, B18 foot, A20 foot；

38 feet of the U1C module of processor core control module FPGA, 39 feet, 42 feet correspond to and Memory connector module respectively The A21 foot of J9 module, A22 foot, A23 foot be connected, 43 feet of the U1C module of processor core control module FPGA, 44 feet, 46 Foot, 49 feet, 50 feet, 51 feet respectively the corresponding B6 foot of J9 module with Memory connector module, A8 foot, A24 foot, B14 foot, B13 foot, A6 foot are connected；

54 feet of the U1D module of processor core control module FPGA, 55 feet, 58 feet, 59 feet, 60 feet, 64 feet, 65 feet, 66 feet, 67 feet, 68 feet, 69 feet, 70 feet, 71 feet, 72 feet respectively the corresponding A13 foot of J9 module with Memory connector module, B12 foot, A12 foot, B11 foot, A11 foot, B10 foot, A10 foot, B9 foot, B4 foot, A4 foot, B3 foot, A3 foot, B2 foot, A2 foot are connected；

73 feet of the U1E module of processor core control module FPGA, 74 feet, 75 feet correspond to and Memory connector module respectively The B1 foot of J9 module, A1 foot, B24 foot be connected, 76 feet of the U1E module of processor core control module FPGA, 80 feet, 83 Foot, 84 feet, 85 feet, 86 feet, 87 feet respectively corresponding 26 feet of J8 module with Memory connector module, 29 feet, 30 feet, 31 Foot, 32 feet, 33 feet, 34 feet are connected, 77 feet of the U1E module of processor core control module FPGA, 79 feet respectively corresponding with 12 feet of the U8 module of UART serial communication interface module, 11 feet are connected, the U1E module of processor core control module FPGA Correspondence is connected with 27 feet of the J8 module of Memory connector module, 28 feet respectively for 77 feet, 79 feet；

98 feet of the U1F module of processor core control module FPGA, 99 feet, 100 feet, 101 feet, 103 feet, 104 feet are right respectively Should be connected with 35 feet of the J8 module of Memory connector module, 36 feet, 37 feet, 38 feet, 39 feet, 40 feet, processor core control Correspondence is connected with connector interface module respectively for 105 feet of the U1F module of molding block FPGA, 106 feet；

110 feet of the U1G module of processor core control module FPGA, 111 feet, 112 feet, 113 feet, 114 feet, 115 feet, 119 Correspondence is connected with connector interface module respectively for foot, 120 feet, 121 feet, 124 feet, 125 feet, 126 feet, 127 feet；

128 feet of the U1H module of processor core control module FPGA, 129 feet, 132 feet, 133 feet correspond to and connector respectively Interface module be connected, 135 feet of the U1H module of processor core control module FPGA, 136 feet, 137 feet, 138 feet, 141 feet, Correspondence is connected with indicating lamp module respectively for 142 feet, 143 feet, 144 feet；

24 feet of the U1I module of processor core control module FPGA, 23 feet correspond to and reset circuit, clock circuit phase respectively Even, 9 feet of the U1J module of processor core control module FPGA are connected with indicating lamp module after being serially connected with the 8th resistance (R8)；

14 feet of the U1J module of processor core control module FPGA, 92 feet, 12 feet, 21 feet are connected with jtag interface circuit, place 97 feet of U1J module of reason device kernel control module FPGA, 94 foot ground connection, the U1J module of processor core control module FPGA 96 feet be connected with the VCCA interface of power module, 18 feet of the U1J module of processor core control module FPGA, 16 feet, 20 Correspondence is connected with JTAG debugging circuit respectively for foot, 15 feet；

19 feet of the U1L module of processor core control module FPGA, 27 feet, 41 feet, 48 feet, 57 feet, 63 feet, 82 feet, 95 feet, 118 feet, 123 feet, 131 feet, 140 feet, 145 feet are all grounded, the CONFIG configuration circuit mould of processor core control module FPGA Block is connected with power module；

35 feet of the U1M module of processor core control module FPGA, 107 feet are linked on the VCCIO interface of power module, place 37 feet of U1M module of reason device kernel control module FPGA, 109 feet are connected with CONFIG configuration circuit module, processor core Correspondence is serially connected with the second inductance coil (L2), the 3rd inductance coil respectively for 36 feet of the U1M module of control module FPGA, 108 feet (L3) it is grounded afterwards；

17 feet of the U1K module of processor core control module FPGA, 26 feet, 40 feet, 47 feet, 56 feet, 62 feet, 81 feet, 93 feet, 117 feet, 122 feet, 130 feet, 139 feet are linked on the VCCIO interface of power module, processor core control module FPGA 5 feet of U1K module, 29 feet, 45 feet, 61 feet, 78 feet, 102 feet, 116 feet, 134 feet are linked into the VCCINT interface of power module On.

4. a kind of modularity machine carried memory read-write equipment according to claim 3 it is characterised in that：Clock circuit includes First inductance coil (L1), the first electric capacity (C1), the second electric capacity (C2), the second chip module (U2), described first inductance coil (L1) one end is connected with power module, and the other end of the first inductance coil (L1) is connected with 1 foot of the second chip module (U2), The positive pole of the first electric capacity (C1) is connected with 1 foot of the second chip module (U2), the minus earth of the first electric capacity (C1), the second electric capacity (C2) one end is connected with 1 foot of the second chip module (U2), the other end of the second electric capacity (C2) and the second chip module (U2) 2 feet and ground connection after connecing, 1 foot of described second chip module (U2) is connected with 4 feet, 3 feet of described second chip module (U2) It is connected with 23 feet of the U1I module of processor core control module FPGA；

Described reset circuit include switching one (S1), button switch one (J1), the 3rd chip module (U3), the 3rd electric capacity (C3), 3rd resistor (R3), 1 foot of described 3rd chip module (U3) is grounded after being concatenated with switch one (S1), described 3rd chip module (U3) 1 foot is linked into after being concatenated with button switch one (J1) on 8 feet of the 3rd chip module (U3), the 3rd chip module (U3) 2 feet concatenate with the 3rd electric capacity (C3) after ground connection, 2 feet of the 3rd chip module (U3) are connected with power module, described 3rd core 3 feet of piece module (U3), 4 foot ground connection, 7 feet of described 3rd chip module (U3) are accessed everywhere after being concatenated with 3rd resistor (R3) On 24 feet of U1I module of reason device kernel control module FPGA；

Described JTAG debugging circuit includes debugging chip (J2), the 4th resistance (R4), the 5th resistance (R5), the 6th resistance (R6), 1 foot of described debugging chip (J2), 2 feet, 5 feet, 9 feet correspond to and the U1J module of processor core control module FPGA respectively 16 feet, 20 feet, 18 feet, 15 feet are connected, and 1 foot of described debugging chip (J2) is grounded after being concatenated with the 4th resistance (R4), described tune 5 feet of examination chip (J2) are linked on power module after concatenating with the 6th resistance (R6), described 9 feet and the debugging chip (J2) It is linked on power module after five resistance (R5) concatenation, 4 feet of described debugging chip (J2) are connected with power module, described debugging 2 feet of chip (J2), 10 foot ground connection；

Described jtag interface circuit include configure chip (J3), first resistor (R1), second resistance (R2), the 7th resistance (R7), Fourth chip (U4), 1 foot of described configuration chip (J3) and 12 foot phases of the U1J module of processor core control module FPGA Even, 3 feet of configuration chip (J3) are linked on the VCCIO interface of power module after being concatenated with first resistor (R1), configure chip (J3) 3 feet are connected with 92 feet of the U1J module of processor core control module FPGA, 5 feet and second of configuration chip (J3) It is linked on the VCCIO interface of power module after resistance (R2) concatenation, 5 feet of configuration chip (J3) control mould with processor core 14 feet of the U1J module of block FPGA are connected, and 7 feet of configuration chip (J3), 8 feet, 9 feet are corresponding respectively to control mould with processor core 13 feet of the U1A module of block FPGA, 8 feet, 6 feet are connected, 2 feet of configuration chip (J3), 10 foot ground connection, and the 4 of configuration chip (J3) Foot is linked on the VCCIO interface of power module, and 6 feet of configuration chip (J3) are grounded after being concatenated with the 7th resistance (R7), configuration 6 feet of chip (J3) are connected with 21 feet of the U1J module of processor core control module FPGA, at 6 feet of fourth chip (U4) 12 feet of the U1J module of reason device kernel control module FPGA are connected, 2 feet of fourth chip (U4), 5 feet, 1 foot and processor core 13 feet of the U1A module of control module FPGA, 6 feet, 8 feet are connected, and 3 feet of fourth chip (U4), 7 feet, 8 feet are linked into power supply mould On the VCCIO interface of block, 4 foot ground connection of fourth chip (U4)；

Described CONFIG configuration circuit module include the 4th inductance coil (L4), the 4th electric capacity (C4), the 5th electric capacity (C5), the 6th Electric capacity (C6), the 7th electric capacity (C7), the 5th inductance coil (L5), the 8th electric capacity (C8), the 9th electric capacity (C9), the tenth electric capacity (C10), the 11st electric capacity (C11), the 12nd electric capacity (C12), the 13rd electric capacity (C13), the 14th electric capacity (C14), the 15th Electric capacity (C15), the 16th electric capacity (C16), the 17th electric capacity (C17), the 18th electric capacity (C18), the 19th electric capacity (C19), 20 electric capacity (C20), the 21st electric capacity (C21), the 22nd electric capacity (C22), the 23rd electric capacity (C23), the 24th Electric capacity (C24), the 25th electric capacity (C25), the 26th electric capacity (C26), the 27th electric capacity (C27), the 28th electric capacity (C28), the 29th electric capacity (C29), the 30th electric capacity (C30), the 31st electric capacity (C31), described 4th electric capacity (C4) Positive pole is linked on the VCCINT interface of power module, the minus earth of the 4th electric capacity (C4), the 5th electric capacity (C5), the 6th electric capacity (C6), the 7th electric capacity (C7) the one end after connecing is connected with 37 feet of the U1M module of processor core control module FPGA, the 5th Electric capacity (C5), the 6th electric capacity (C6), the 7th electric capacity (C7) the ground connection of the other end after connecing, a termination of the 4th inductance coil (L4) Enter on the VCCINT interface of power module, one end of the 4th inductance coil (L4) is linked into processor core control module FPGA 37 feet of U1M module on, the positive pole of described 8th electric capacity (C8) is linked on the VCCINT interface of power module, the described 8th The minus earth of electric capacity (C8), described 9th electric capacity (C9), the tenth electric capacity (C10), the 11st electric capacity (C11) the one end after connecing Be connected with 109 feet of the U1M module of processor core control module FPGA, described 9th electric capacity (C9), the tenth electric capacity (C10), 11st electric capacity (C11) the ground connection of the other end after connecing, one end of the 5th inductance coil (L5) is linked into power module On VCCINT interface, the other end of the 5th inductance coil (L5) is linked into the U1M module of processor core control module FPGA On 109 feet, the 12nd electric capacity (C12), the 13rd electric capacity (C13), the 14th electric capacity (C14), the 15th electric capacity (C15), the tenth Six electric capacity (C16), the 17th electric capacity (C17), the 18th electric capacity (C18), the 19th electric capacity (C19) the one end after connecing is linked into On the VCCINT interface of power module, the 12nd electric capacity (C12), the 13rd electric capacity (C13), the 14th electric capacity (C14), the 15th Electric capacity (C15), the 16th electric capacity (C16), the 17th electric capacity (C17), the 18th electric capacity (C18), the 19th electric capacity (C19) simultaneously connect Afterwards the other end ground connection, described 20th electric capacity (C20), the 21st electric capacity (C21), the 22nd electric capacity (C22), the 20th Three electric capacity (C23), the 24th electric capacity (C24), the 25th electric capacity (C25), the 26th electric capacity (C26), the 27th electricity Hold (C27), the 28th electric capacity (C28), the 29th electric capacity (C29), the 30th electric capacity (C30), the 31st electric capacity (C31) And the one end after connecing is linked on the VCCIO interface of power module, described 20th electric capacity (C20), the 21st electric capacity (C21), the 22nd electric capacity (C22), the 23rd electric capacity (C23), the 24th electric capacity (C24), the 25th electric capacity (C25), the 26th electric capacity (C26), the 27th electric capacity (C27), the 28th electric capacity (C28), the 29th electric capacity (C29), the 30th electric capacity (C30), the 31st electric capacity (C31) the ground connection of the other end after connecing.

5. a kind of modularity machine carried memory read-write equipment according to claim 3 it is characterised in that：Memory connector 1 foot of the J8 module of module, 2 feet, 3 feet, 4 feet, 5 feet, the 6 feet corresponding U1C mould with processor core control module FPGA respectively 43 feet of block, 44 feet, 46 feet, 49 feet, 50 feet, 51 feet are connected, 41 feet of the J8 module of described Memory connector module, 42 Foot, 43 feet, 44 feet, 45 feet are connected with 5V power supply respectively；

6. a kind of modularity machine carried memory read-write equipment according to claim 3 it is characterised in that：UART serial communication Interface module includes the 8th chip module (U8), the first link block (J14), the 44th electric capacity (C44), the 45th electric capacity (C45), the 46th electric capacity (C46), the 47th electric capacity (C47), the 48th electric capacity (C48), described 44th electric capacity (C44) positive pole is connected with 1 foot of the 8th chip module (U8), the negative pole of the 44th electric capacity (C44) and the 8th chip module (U8) 3 feet are connected, and the positive pole of described 45th electric capacity (C45) is connected with 4 feet of the 8th chip module (U8), and the described 4th The negative pole of 15 electric capacity (C45) is connected with 5 feet of the 8th chip module (U8), and the positive pole of described 46th electric capacity (C46) connects Ground, the negative pole of the 46th electric capacity (C46) is connected with 6 feet of the 8th chip module (U8), described 47th electric capacity (C47) Positive pole is connected with 2 feet of the 8th chip module (U8), the negative pole of described 47th electric capacity (C47) and the 8th chip module (U8) 16 feet be connected, the positive pole of the 48th electric capacity (C48) is connected with 16 feet of the 8th chip module (U8), the 48th electric capacity (C48) minus earth, 15 foot ground connection of the 8th chip module (U8), 12 feet of the 8th chip module (U8), 11 feet are right respectively Should be connected with 77 feet of the U1E module of processor core control module FPGA, 79 feet, 14 feet of the 8th chip module (U8), 13 Correspondence is connected foot with 3 feet of the first link block (J14), 2 feet respectively, 5 foot ground connection of the first link block (J14)；

Connector interface module includes the second link block (J11), the 3rd link block (J12), the 4th link block (J13), 1 foot of the second link block (J11) is linked on 5V power supply, 2 foot ground connection of the second link block (J11), the 3rd link block (J12) correspondence is connected with 105 feet of the U1F module of processor core control module FPGA, 106 feet respectively for 1 foot, 2 feet, and the 3rd 3 feet of link block (J12), 4 feet, 5 feet, 6 feet, 7 feet, 8 feet, 9 feet, 10 feet, 11 feet, 12 feet, 13 feet, 14 feet, 15 feet are respectively Corresponding 110 feet of U1G module with processor core control module FPGA, 111 feet, 112 feet, 113 feet, 114 feet, 115 feet, 119 feet, 120 feet, 121 feet, 124 feet, 125 feet, 126 feet, 127 feet be connected, 16 feet of the 3rd link block (J12), 17 feet, 18 Foot, 19 feet correspond to and 128 feet of the U1H module of processor core control module FPGA, 129 feet, 132 feet, 133 foot phases respectively Even, 20 feet of the 3rd link block (J12), 21 feet, 22 feet are respectively connected on 5V power supply, and the 23 of the 3rd link block (J12) Foot, 24 feet, 25 feet, 26 feet are all grounded, and 1 foot of described 4th link block (J13), 2 feet, 3 feet, 4 feet, 5 feet, 6 feet, 7 feet divide Dui Ying not be connected with 1 foot of the U1A module of processor core control module FPGA, 2 feet, 3 feet, 4 feet, 7 feet, 10 feet, 11 feet, the 8 feet of four link blocks (J13), 9 feet, 10 feet, 11 feet, 12 feet, 13 feet correspond to and processor core control module FPGA respectively 28 feet of U1B module, 30 feet, 31 feet, 32 feet, 33 feet, 34 feet be connected；

14 feet of the 4th link block (J13), 15 feet, the 16 feet corresponding U1C mould with processor core control module FPGA respectively 38 feet of block, 39 feet, 42 feet are connected, and 17 feet of the 4th link block (J13), 18 feet, 19 feet, 20 feet are all grounded.

7. a kind of modularity machine carried memory read-write equipment according to claim 3 it is characterised in that：Indicating lamp module bag Include the 27th resistance (R27), the 28th resistance (R28), the 29th resistance (R29), the 30th resistance (R30), the 3rd 11 resistance (R31), the 32nd resistance (R32), the 33rd resistance (R33), the 34th resistance (R34), the 9th resistance (R9), the first LED (D1), the second LED (D19), the 3rd LED (D20), the 4th LED (D21), the 5th LED (D22), the 6th LED (D23), the 7th LED (D24), the 8th LED (D25), the 9th LED (D26), a described LED The negative pole of lamp (D1) is grounded after being concatenated with the 9th resistance (R9), and the positive pole of the first LED (D1) is linked on 5V power supply, and second The negative pole of LED (D19) accesses the U1H mould managing device kernel control module FPGA everywhere with the 27th resistance (R27) after concatenating On 135 feet of block, the negative pole of the 3rd LED (D20) is accessed reason device core everywhere and controls after being concatenated with the 28th resistance (R28) On 136 feet of the U1H module of module FPGA, the negative pole of the 4th LED (D21) is accessed after being concatenated with the 9th resistance (R9) and manages everywhere On 137 feet of the U1H module of device kernel control module FPGA, the negative pole of the 5th LED (D22) and the 30th resistance (R30) are gone here and there Access on 138 feet of U1H module managing device kernel control module FPGA everywhere after connecing, the negative pole and the 3rd of the 6th LED (D23) Access on 139 feet of U1H module managing device kernel control module FPGA everywhere after 11 resistance (R31) concatenation, the 7th LED (D24) negative pole accesses the U1H module managing device kernel control module FPGA everywhere with the 32nd resistance (R32) after concatenating On 140 feet, the negative pole of the 8th LED (D25) accesses reason device kernel control module everywhere with the 33rd resistance (R33) after concatenating On 141 feet of the U1H module of FPGA, the negative pole of the 9th LED (D26) is accessed everywhere after being concatenated with the 34th resistance (R34) On 142 feet of U1H module of reason device kernel control module FPGA, the second LED (D19), the 3rd LED (D20), the 4th LED Lamp (D21), the 5th LED (D22), the 6th LED (D23), the 7th LED (D24), the 8th LED (D25), the 9th LED (D26) positive pole is all linked on the VCCIO interface of power module.

8. a kind of modularity machine carried memory read-write equipment according to claim 1 it is characterised in that：Power module includes 3.3V power circuit, 2.5V power circuit and 1.2V power circuit, described 3.3V power circuit include the first power supply chip (U5), 32nd electric capacity (C32), the 33rd electric capacity (C33), the 34th electric capacity (C34), the 35th electric capacity (C35), button Switch two (J4), 1 foot ground connection, 3 feet of the first power supply chip (U5) and the 33rd electric capacity (C33) of the first power supply chip (U5) It is grounded after concatenation, the positive pole of the 32nd electric capacity (C32) is connected with 3 feet of the first power supply chip (U5), the 32nd electric capacity (C32) minus earth, 3 feet of the first power supply chip (U5) are linked on 5V power supply, 2 feet of the first power supply chip (U5) and It is grounded after 34 electric capacity (C34) concatenation, the positive pole of the 35th electric capacity (C35) is connected with 2 feet of the first power supply chip (U5), The minus earth of the 35th electric capacity (C35), 2 feet of the first power supply chip (U5) are formed after being concatenated with button switch two (J4) VCCIO interface；

2.5V power circuit include second source chip (U6), the 40th electric capacity (C40), the 41st electric capacity (C41), the 40th Two electric capacity (C42), the 43rd electric capacity (C43), button switch three (J5), 1 foot ground connection of described second source chip (U6), the The positive pole of 40 electric capacity (C40) is connected with 3 feet of second source chip (U6), the minus earth of the 40th electric capacity (C40), and second 3 feet of power supply chip (U6) are grounded after being concatenated with the 41st electric capacity (C41), and 3 feet of second source chip (U6) are linked into 5V On power supply, 2 feet of second source chip (U6) are grounded after being concatenated with the 42nd electric capacity (C42), the 43rd electric capacity (C43) Positive pole is connected with 2 feet of second source chip (U6), the minus earth of the 43rd electric capacity (C43), second source chip (U6) 2 feet concatenate with button switch three (J5) after formed VCCA interface；

1.2V power circuit include the 3rd power supply chip (U7), the 36th electric capacity (C36), the 37th electric capacity (C37), the 3rd 18 electric capacity (C38), the 39th electric capacity (C39), button switch four (J6), 1 foot ground connection of described 3rd power supply chip (U7), The positive pole of the 36th electric capacity (C36) is connected with 3 feet of the 3rd power supply chip (U7), and the negative pole of the 36th electric capacity (C36) connects Ground, 3 feet of the 3rd power supply chip (U7) concatenate with the 37th electric capacity (C37) after be grounded, 2 feet of the 3rd power supply chip (U7) and Ground connection, the positive pole of the 39th electric capacity (C39) and 2 foot phases of the 3rd power supply chip (U7) after 38th electric capacity (C38) concatenation Even, the minus earth of the 39th electric capacity (C39), 2 feet of the 3rd power supply chip (U7) concatenate with button switch four (J6) after shape Become VCCINT interface.