CN115587059A - Data conversion system - Google Patents
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- CN115587059A CN115587059A CN202211242360.3A CN202211242360A CN115587059A CN 115587059 A CN115587059 A CN 115587059A CN 202211242360 A CN202211242360 A CN 202211242360A CN 115587059 A CN115587059 A CN 115587059A
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- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/382—Information transfer, e.g. on bus using universal interface adapter
- G06F13/385—Information transfer, e.g. on bus using universal interface adapter for adaptation of a particular data processing system to different peripheral devices
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- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
- G06F13/4291—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus using a clocked protocol
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- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F2213/38—Universal adapter
- G06F2213/3852—Converter between protocols
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Abstract
The embodiment of the application relates to the technical field of communication and discloses a data conversion system. The data conversion system includes: a first conversion unit integrated in the master chip and a second conversion unit integrated in the slave chip; the first conversion unit is used for analyzing information received by an AHB bus in the main chip, acquiring read-write control information and data information, packaging and encoding the read-write control information and the data information into serial data, and transmitting the serial data to a slave chip indicated by a selection signal through a first transmission pin according to a main clock signal and the selection signal transmitted by the main chip through a first clock pin and a first selection pin; the second conversion unit is used for receiving serial data through the second transmission pin according to the master clock signal received through the second clock pin, converting the serial data into parallel data, unpacking the parallel data, recovering read-write control information and data information, and writing the data information into a storage position indicated by the read-write control information in the slave chip through an AHB bus in the slave chip.
Description
Technical Field
The embodiment of the application relates to the technical field of communication, in particular to a data conversion system.
Background
System on chip (SoC) designs integrate multiple components of a computer or other electronic device or system onto an integrated circuit chip. A typical SoC includes one or more microcontrollers, memory, peripherals, interfaces, clock sources, voltage regulators and power management circuits, and external interfaces.
At present, the access of external equipment to an internal bus of an SOC is mainly that a CPU controls a serial interface to receive or send data in an interruption or inquiry mode, and the CPU performs protocol analysis and data relocation on the data according to a related communication protocol in the process, so that whether each frame of data is acquired or data in the frame is acquired, a series of steps of interruption, inquiry, analysis, data relocation and the like all result in low data reading and writing efficiency of the CPU and high software overhead. In addition, when the data transmission rate is high, the software overhead of the CPU is further increased, and the CPU itself has other transactions and interrupts to be processed, so that data cannot be received or transmitted immediately, which results in large communication gaps and poor real-time performance.
Disclosure of Invention
An object of the embodiments of the present application is to provide a data conversion system, where a first conversion unit and a second conversion unit perform serial-to-parallel conversion and parallel-to-serial conversion on data, so that the requirement for reading and writing large quantities of data can be met by occupying at least 3 pins of a chip, thereby reducing software overhead and improving data exchange efficiency.
To solve the above technical problem, an embodiment of the present application provides a data conversion system, including: a first conversion unit integrated in the master chip and a second conversion unit integrated in the slave chip; the master chip comprises a first clock pin, a first transmission pin and at least one first selection pin corresponding to the number of slave chips; the slave chip comprises a second clock pin, a second transmission pin and a second selection pin; the first conversion unit is used for analyzing information received by an AHB (advanced high-performance bus) in a master chip, acquiring read-write control information and data information, packaging and encoding the read-write control information and the data information into serial data, and sending the serial data to a slave chip indicated by a selection signal through the first transmission pin according to a master clock signal and the selection signal sent through the first clock pin and the first selection pin; the second conversion unit is configured to receive the serial data through the second transmission pin according to the master clock signal received through the second clock pin, convert the serial data into parallel data, unpack the parallel data, recover read-write control information and data information, and write the data information into a storage location indicated by the read-write control information in a slave chip through an AHB bus in the slave chip.
An embodiment of the present application further provides a data conversion system, including: the first conversion unit is integrated in the master chip and the second conversion unit is integrated in the slave chip; the master chip comprises a first clock pin, a first transmission pin and at least one first selection pin corresponding to the number of slave chips; the slave chip comprises a second clock pin, a second transmission pin and a second selection pin; the first conversion unit is used for analyzing information received by an AHB bus in a main chip, acquiring read-write control information, packaging and coding the read-write control information into serial data, and sending the serial data to a slave chip indicated by a selection signal through a first transmission pin according to a main clock signal and the selection signal sent by the main chip through the first clock pin and the first selection pin; the second conversion unit is configured to read, according to the read-write control information received via the second transmission pin, data information indicated by the read-write control information via an AHB bus in a slave chip, package and encode the data information into serial data, and send the serial data to the master chip via the second transmission pin according to a slave clock signal sent via the second clock pin.
The data conversion system provided by the embodiment of the application comprises a first conversion unit integrated in a master chip and a second conversion unit integrated in a slave chip, wherein the master chip and the slave chip are communicated and interacted through a serial bus. The master chip comprises a first clock pin, a first transmission pin and at least one first selection pin corresponding to the number of the slave chips, and the slave chips comprise a second clock pin, a second transmission pin and a second selection pin. The first conversion unit sends a selection signal through the first selection pin to indicate a slave chip communicated with the master chip, sends a clock signal through the first clock pin to facilitate subsequent data sending according to the clock signal, analyzes information received through an AHB bus, packages and encodes the data into serial data, and sends the serial data to the slave chip through the first transmission pin. Similarly, the second conversion unit receives the selection signal through the second selection pin, receives the master clock signal through the second clock pin, receives the serial data through the second transmission pin, and converts the serial data into parallel data. That is to say, the main chip can realize the read-write requirement of mass data between chips by at least 3 pins and the slave chip only needs 3 pins, thereby reducing the software overhead, improving the data exchange efficiency and occupying fewer chip pins.
Drawings
One or more embodiments are illustrated by way of example in the accompanying drawings which correspond to and are not to be construed as limiting the embodiments, in which elements having the same reference numeral designations represent like elements throughout, and in which the drawings are not to be construed as limiting in scale unless otherwise specified.
FIG. 1 is a first schematic structural diagram of a data conversion system according to an embodiment of the present disclosure;
fig. 2 is a schematic structural diagram of a data conversion system according to an embodiment of the present application;
fig. 3 is a timing diagram of signals of serial data transmitted by a first conversion unit in the data conversion system according to the embodiment of the present application.
Detailed Description
To make the objects, technical solutions and advantages of the embodiments of the present application clearer, the embodiments of the present application will be described in detail below with reference to the accompanying drawings. However, it will be appreciated by those of ordinary skill in the art that in the various embodiments of the present application, numerous technical details are set forth in order to provide a better understanding of the present application. However, the technical solutions claimed in the present application can be implemented without these technical details and various changes and modifications based on the following embodiments.
At present, the access of external equipment to an internal bus of an SOC is mainly realized by that a CPU controls a serial interface to receive or send data in an interruption or inquiry mode, and the CPU carries out protocol analysis and data relocation on the data according to a related communication protocol in the process, so that the efficiency of reading and writing the data by the CPU is low and the software overhead is large no matter each frame of data or each frame of data is obtained, and a series of steps such as interruption, inquiry, analysis, data relocation and the like are caused. In addition, when the data transmission rate is high, the software overhead of the CPU is further increased, and the CPU itself has other transactions and interrupts to be processed, so that data cannot be received or transmitted immediately, which results in large communication gaps and poor real-time performance.
In addition, if data interaction is performed directly between chips (or between devices, or between chips and devices) through a parallel bus, such as an AHB bus, although the parallel bus has a fast communication speed and good real-time performance, it is not suitable for integrated and miniaturized products because the interface occupies many pins (the number of pins of the AHB bus interface exceeds 100).
The embodiment of the present application relates to a data exchange system, as shown in fig. 1, specifically including: a first conversion unit 101 integrated in the master chip and a second conversion unit 102 integrated in the slave chip; the master chip comprises a first clock pin CLK1, a first transmission pin SDIO1 and at least one first selection pin CSN1 corresponding to the number of slave chips; the slave chip includes a second clock pin CLK2, a second transmission pin SDIO2, and a second selection pin CSN2.
The master chip and the slave chip are communicated and interacted through a serial bus, for example: data interaction is performed between the master chip and the slave chip through a Serial Peripheral Interface (SPI) bus, a Universal Asynchronous Receiver/Transmitter (UART), or an Inter-Integrated Circuit (I2C) bus.
The first conversion unit 101 receives information sent by a CPU or other functional modules (such as DMA, DSP, etc.) in the main chip through an AHB bus, or the first conversion unit stores the received information to the corresponding functional module in the main chip through the AHB bus. Similarly, the second conversion unit 102 and the CPU or other functional modules in the slave chip also perform information interaction through the AHB bus.
It should be noted that the data conversion system of the present embodiment may be applied to a scenario with one master and one slave, and may also be applied to a scenario with one master and multiple slaves. When the method is applied to a master-slave scene, the number of pins of the master chip is 3, and the number of pins of the slave chip is also 3. When the method is applied to a master multi-slave scene, the number of pins of the master chip is 2+ n (n is the number of slave chips), and the number of pins of each slave chip is 3. As shown in fig. 2, the application scenario is that one master chip performs data communication with two slave chips. The master chip performs data communication with the slave chip 1 through the first clock pin CLK1, the first transmission pin SDIO1 and the first selection pin CSN11, and the master chip performs data communication with the slave chip 2 through the first clock pin CLK1, the first transmission pin SDIO1 and the first selection pin CSN 12. When the master chip performs a write operation to a plurality of slave chips, the first conversion unit 101 time-division multiplexes the first clock pin CLK1 and the first transmission pin SDIO1. Of course, a chip may be used as both a master chip and a slave chip, and the master and slave roles of the chips are not fixed.
When the master chip performs a write operation on the slave chip, the first conversion unit 101 is configured to parse information received via an AHB bus in the master chip, acquire read-write control information and data information, package and encode the read-write control information and the data information into serial data, and send the serial data to the slave chip indicated by the selection signal via the first transmission pin SDIO1 according to a master clock signal and the selection signal sent via the first clock pin CLK1 and the first selection pin CSN1; and the second conversion unit 102 is configured to receive serial data through the second transmission pin SDIO2 according to the master clock signal received through the second clock pin CLK2, convert the serial data into parallel data, unpack the parallel data, recover read-write control information and data information, and write the data information into a storage location indicated by the read-write control information in the slave chip through an AHB bus in the slave chip.
Specifically, the first conversion unit 101 parses information received via the AHB bus according to an on-chip bus protocol, that is, an AMBA protocol, to obtain read-write control information and data information, then packetizes and encodes the read-write control information and the data information into serial data, and transmits the serial data to the slave chip via the first transmission pin SDIO1. Of course, before sending the serial data to the slave chip, the first converting unit 101 needs to send a selection signal to the slave chip via the first selection pin CSN1 to indicate the slave chip to which the master chip where the first converting unit 101 is located performs a communication operation. The first conversion unit 101 then transmits a master clock signal via the first clock pin CLK1, and transmits serial data to the slave chip indicated by the selection signal according to the master clock signal.
Wherein, the read-write control information comprises: read-write identification information hwrite of 2 bits, address information addr of 32 bits, and byte size information hsize of 2 bits. Specifically, when the read-write identification information hwrite is 1, it indicates a write operation, and when the read-write identification information hwrite is 0, it indicates a read operation. When the byte size information hsize is 00, it indicates that 1byte of data is transmitted each time, when the byte size information hsize is 01, it indicates that 2 bytes of data is transmitted each time, when the byte size information hsize is 10, it indicates that 4 bytes of data is transmitted each time, and when the byte size information hsize is 11, it indicates that 8 bytes of data is transmitted each time.
In addition, the first conversion unit 101 shifts to output at a falling edge of the master clock signal when serial data is transmitted through the first transmission pin SDIO1 according to the master clock signal. The structure of the serial data includes: the read-write identification information hwrite, the address information addr, the byte size information hsize and the data information data are sequentially arranged. As shown in fig. 3, a signal timing diagram for transmitting serial data for the first conversion unit. As can be seen from fig. 3, during the write operation of the master chip to the slave chip, the selection signal CSN is kept at a low level all the time, and after the write operation is completed, the first conversion unit 101 sends a high-level selection signal through the first selection pin CSN1, which indicates that one data transmission is completed.
Specifically, after receiving the selection signal and the master clock signal through the second selection pin CSN2 and the second clock pin CLK2, the second conversion unit 102 samples and receives serial data across clock domains at a rising edge of the master clock signal, converts the serial data into parallel data, unpacks the parallel data, and recovers the read-write control and data information according to the AMBA protocol. The second conversion unit 102 writes the data information into the storage location indicated by the read-write control information in the slave chip through the AHB bus.
Further, the first conversion unit 101 is further configured to, when it is determined that the current address information and the previous address information are continuous according to the previous read-write control information and the current read-write control information, and the current byte size information is consistent with the previous byte size information, only perform packet transmission on the current data information; the second conversion unit 102 is further configured to determine the address information of this time according to the previous address information and the previous byte size information when the read-write control information of this time is not acquired.
Specifically, when the first conversion unit 101 determines that the current address information and the previous address information are continuous according to the previous read-write control information and the current read-write control information, and the current byte size information is consistent with the previous byte size information, it is determined that the operation is continuous write operation, at this time, only the current data information is packed and encoded into serial data to be transmitted to the slave chip, the read-write control information does not need to be retransmitted, the transmission time of the read-write control information is saved, and the data exchange efficiency is improved. When the second conversion unit 102 does not receive the current read-write control information, the address information of the current write operation is predicted according to the address information and the byte size information corresponding to the previous write operation, so that the address prediction of the continuous write operation is realized.
Such as: the address information of the last write operation is 0x3000_0000, the byte size information is 1byte, and if the write operation is continued this time, the address information of this time is 0x3000_0001, and the byte size information of this time is still 1byte. If the second conversion unit 102 does not receive the read/write control information, the second conversion unit predicts that the present address information is 0x3000 u 0001 based on the last address information and the byte size information. That is, the second conversion unit 102 may continue to implement the write operation according to the address prediction function when the read/write control information is not received.
The data conversion system provided by the embodiment occupies 3 pins of the chip, realizes efficient reading and writing between the chips, and has no additional software overhead. Meanwhile, multi-chip cascade can be realized, the master chip is managed in a coordinated mode, the external interface is unified, the passive receiving mode of the chip is adopted, scenes which cannot be solved by the single chip are covered, cost is reduced obviously through multi-chip cascade, and universality is improved.
The embodiment of the present application further relates to a data exchange system, which specifically includes: a first conversion unit 101 integrated in the master chip and a second conversion unit 102 integrated in the slave chip; the master chip includes a first clock pin CLK1, a first transmission pin SDIO1, and at least one first selection pin CSN1 corresponding to the number of slave chips; the slave chip includes a second clock pin CLK2, a second transmission pin SDIO2, and a second selection pin CSN2.
The data conversion system of the embodiment can be applied to a master-slave scenario and can also be applied to a master-slave scenario. When the method is applied to a master-slave scene, the number of pins of the master chip is 3, and the number of pins of the slave chip is also 3. When the method is applied to a master multi-slave scene, the number of pins of the master chip is 2+ n (n is the number of slave chips), and the number of pins of each slave chip is 3. When the master chip performs a read operation on a plurality of slave chips, the first conversion unit 101 time-division multiplexes the first clock pin CLK1 and the first transmission pin SDIO1. Of course, a chip may be used as both a master chip and a slave chip, and the master and slave roles of the chips are not fixed.
When the master chip reads the slave chip, the first conversion unit 101 is configured to parse information received via an AHB bus in the master chip to obtain read-write control information, package and encode the read-write control information into serial data, and send the serial data to the slave chip indicated by the selection signal via the first transmission pin SDIO1 according to a master clock signal and the selection signal sent by the master chip via the first clock pin CLK1 and the first selection pin CSN1; and the second conversion unit 102 is configured to read, according to the read-write control information received via the second transmission pin SDIO2, data information indicated by the read-write control information via an AHB bus in the slave chip, package and encode the data information into serial data, and send the serial data to the master chip via the second transmission pin according to a slave clock signal sent via the second clock pin CLK 2.
And the first conversion unit is also used for receiving serial data sent by the slave chip through the first transmission pin SDIO1 according to the slave clock signal received through the first clock pin CLK1, converting the serial data into parallel data, unpacking the parallel data to recover data information, and storing the data information to the master chip through an AHB bus in the master chip.
Wherein, the read-write control information comprises: read-write identification information hwrite of 2 bits, address information addr of 32 bits, and byte size information hsize of 2 bits. Specifically, when the read-write identification information hwrite is 1, it indicates a write operation, and when the read-write identification information hwrite is 0, it indicates a read operation. When the byte size information hsize is 00, it indicates that 1byte of data is transmitted each time, when the byte size information hsize is 01, it indicates that 2 bytes of data is transmitted each time, when the byte size information hsize is 10, it indicates that 4 bytes of data is transmitted each time, and when the byte size information hsize is 11, it indicates that 8 bytes of data is transmitted each time.
When the master chip performs a read operation on the slave chip, the first conversion unit 101 only packetizes and encodes the read-write control information into serial data (the structure of the serial data includes read-write identification information, address information, byte size information arranged in sequence) and sends the serial data to the slave chip, and the second conversion unit 102 reads data information indicated by the read-write control information through the AHB bus after receiving the read-write control information through the second transmission pin SDIO2 and packetizes and encodes the data information into the serial data and sends the serial data to the master chip. The first conversion unit 101 samples and receives serial data sent by the slave chip across the clock domain at the rising edge of the slave clock signal according to the slave clock signal, converts the serial data into parallel data, unpacks the parallel data, recovers data information, and stores the information of the data in the master chip through an AHN bus.
Further, the first conversion unit 101 is further configured to not perform packet transmission on the current read-write control information when it is determined that the current address information and the last address information are continuous according to the last read-write control information and the current read-write control information, and the current byte size information is consistent with the last byte size information; the second conversion unit 102 is configured to determine, when the read-write control information of this time is not acquired, address information of this time according to the previous address information and the previous byte size information.
Specifically, when the first conversion unit 101 determines that the current address information and the last address information are continuous and the current byte size information is consistent with the last byte size information, that is, the master chip performs continuous reading operation on the slave chip, at this time, the first conversion unit 101 does not need to transmit the current read-write control information, and when the current read-write control information is not acquired, the second conversion unit 102 directly determines the current address information according to the last address information and the last byte size information. Namely, the second conversion unit predicts the address information of the current reading operation according to the address information and the byte size information corresponding to the previous reading operation, and realizes the address prediction of the continuous reading operation.
Such as: the address information of the last read operation is 0x2000_0000, the byte size information is 4byte, if the read operation is continued this time, the address information of this time is 0x2000_0004, and the byte size information of this time is still 4byte. If the second conversion unit 102 does not receive the read/write control information, the second conversion unit predicts that the current address information is 0x2000 u 0004 according to the previous address information and byte size information. That is, when the second conversion unit 102 does not receive the read/write control information, it may continue to perform the read operation according to the address prediction function.
Further, the second conversion unit 102 is further configured to, when the address information is received and the byte size information is not received, read data information of a preset byte size in advance through an AHB bus in the slave chip according to the address information; after receiving the byte size information, acquiring the data information indicated by the byte size information from the data information read in advance, and packaging and encoding the data information indicated by the byte size information into serial data.
Specifically, when the first conversion unit 101 transmits the address information, but does not transmit the byte size information, the second conversion unit 102 already knows the read address because the read does not destroy the data, and immediately reads the data with the predetermined byte size back from the memory of the slave chip via the AHB bus, and if the predetermined byte size is 4 bytes, the second conversion unit reads the 4 bytes of data in advance according to the read address. After receiving the byte size information hsize, assuming that the byte size information hsize indicates to read 2-byte data, the second conversion unit 102 obtains 2-byte data from the pre-read 4-byte data, and packages and encodes the 2-byte data into serial data to be sent to the host chip. Therefore, the data pre-fetching function of the second conversion unit 102 can greatly improve the data reading efficiency, reduce the communication gap, and realize real-time data reading.
The data conversion system provided by the embodiment occupies 3 pins of the chip, realizes efficient reading and writing between the chips, and has no additional software overhead. Meanwhile, multi-chip cascade can be realized, the master chip is managed in a coordinated mode, the external interface is unified, the passive receiving mode of the slave chip covers scenes which cannot be solved by the single chip, the cost is reduced obviously through multi-chip cascade, and the universality is improved.
It will be understood by those of ordinary skill in the art that the foregoing embodiments are specific examples for carrying out the present application, and that various changes in form and details may be made therein without departing from the spirit and scope of the present application in practice.
Claims (10)
1. A data conversion system, comprising: the first conversion unit is integrated in the master chip and the second conversion unit is integrated in the slave chip; the master chip comprises a first clock pin, a first transmission pin and at least one first selection pin corresponding to the number of slave chips; the slave chip comprises a second clock pin, a second transmission pin and a second selection pin;
the first conversion unit is used for analyzing information received by an AHB (advanced high-performance bus) in a master chip, acquiring read-write control information and data information, packaging and encoding the read-write control information and the data information into serial data, and sending the serial data to a slave chip indicated by a selection signal through the first transmission pin according to a master clock signal and the selection signal sent through the first clock pin and the first selection pin;
the second conversion unit is configured to receive the serial data through the second transmission pin according to the master clock signal received through the second clock pin, convert the serial data into parallel data, unpack the parallel data, recover read-write control information and data information, and write the data information into a storage location indicated by the read-write control information in a slave chip through an AHB bus in the slave chip.
2. The data conversion system according to claim 1, wherein the read-write control information includes: reading and writing identification information, address information and byte size information; the structure of the serial data comprises: the read-write identification information, the address information, the byte size information and the data information are arranged in sequence.
3. The data conversion system of claim 2,
the first conversion unit is further used for only packaging and encoding the current data information into serial data when the current address information and the previous address information are determined to be continuous according to the previous read-write control information and the current byte size information is consistent with the previous byte size information;
the second conversion unit is further configured to determine the address information of this time according to the address information of the last time and the byte size information of the last time when the read-write control information of this time is not acquired.
4. The data conversion system according to any one of claims 1 to 3, wherein the first conversion unit time-multiplexes the first clock pin and the first transmission pin when the master chip performs a write operation to a plurality of slave chips.
5. A data conversion system, comprising: the first conversion unit is integrated in the master chip and the second conversion unit is integrated in the slave chip; the master chip comprises a first clock pin, a first transmission pin and at least one first selection pin corresponding to the number of slave chips; the slave chip comprises a second clock pin, a second transmission pin and a second selection pin;
the first conversion unit is used for analyzing information received by an AHB (advanced high-performance bus) in a main chip, acquiring read-write control information, packaging and encoding the read-write control information into serial data, and sending the serial data to a slave chip indicated by a selection signal through a first transmission pin according to a main clock signal and the selection signal sent by the main chip through the first clock pin and the first selection pin;
the second conversion unit is configured to read, according to the read-write control information received via the second transmission pin, data information indicated by the read-write control information via an AHB bus in a slave chip, package and encode the data information into serial data, and send the serial data to the master chip via the second transmission pin according to a slave clock signal sent via the second clock pin.
6. The data conversion system of claim 5,
the first conversion unit is further configured to receive serial data sent by the slave chip through the first transmission pin according to the slave clock signal received through the first clock pin, convert the serial data into parallel data, unpack the parallel data to recover data information, and store the data information to the master chip through an AHB bus in the master chip.
7. The data conversion system according to claim 5 or 6, wherein the read/write control information includes: and reading and writing identification information, address information and byte size information.
8. The data conversion system of claim 6,
the first conversion unit is further used for not packaging and transmitting the current read-write control information when the current address information and the previous address information are determined to be continuous according to the previous read-write control information and the current byte size information is consistent with the previous byte size information;
and the second conversion unit is used for determining the address information of the current time according to the address information of the last time and the byte size information of the last time when the read-write control information of the current time is not acquired.
9. The data conversion system of claim 6,
the second conversion unit is further configured to, when the address information is received and the byte size information is not received, read data information of a preset byte size in advance through an AHB bus in the slave chip according to the address information; and after receiving the byte size information, acquiring the data information indicated by the byte size information from the data information read in advance, and packaging and encoding the data information indicated by the byte size information into serial data.
10. The data conversion system of claim 5, wherein the first conversion unit time-multiplexes the first clock pin and the first transmission pin when the master chip reads from a plurality of slave chips.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN116662240A (en) * | 2023-05-12 | 2023-08-29 | 珠海妙存科技有限公司 | A protocol conversion circuit and method, chip, test device, storage medium |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN116662240A (en) * | 2023-05-12 | 2023-08-29 | 珠海妙存科技有限公司 | A protocol conversion circuit and method, chip, test device, storage medium |
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