CN209822106U

CN209822106U - Configuration device based on FPGA programmable device

Info

Publication number: CN209822106U
Application number: CN201920125529.4U
Authority: CN
Inventors: 雷霞
Original assignee: Ningbo City College of Vocational Technology
Current assignee: Ningbo City College of Vocational Technology
Priority date: 2019-01-25
Filing date: 2019-01-25
Publication date: 2019-12-20
Anticipated expiration: 2029-01-25

Abstract

The utility model provides a configuration device based on FPGA programmable device, including consecutive wireless transceiver module, main control module and the FPGA module of waiting to dispose, main control module is FPGA programmable device, and main control module includes consecutive clock generation module, data receiving module, random access memory and configuration module, and the output of configuration module links to each other with the input of the FPGA module of waiting to dispose; the data receiving module comprises a trigger, a bit counter, a shift register and a byte counter which are connected in sequence, wherein a completion signal port in the output end of the byte counter is connected with the input end of the configuration module, and the rest ports are connected with the input end of the random access memory. The utility model discloses well main control module is FPGA programmable device, and when treating the FPGA module of configuration and dispose, the probability of configuration failure is lower, the configuration efficiency is higher, convenient to use and editor simultaneously.

Description

Configuration device based on FPGA programmable device

Technical Field

The utility model relates to a device able to programme technical field based on FPGA especially relates to a configuration device based on FPGA device able to programme.

Background

The digital system design is a professional basic course for cultivating the comprehensive abilities of students to design, analyze, test, apply and develop the digital system in the electronic information major of colleges and universities, and the experimental teaching link of the course plays a vital role in mastering system knowledge and improving the practical ability and the innovation ability of the students. The structural block diagram of the existing digital circuit cloud experiment system is shown in fig. 1, and the existing digital circuit cloud experiment system mainly comprises a Web client, an ari cloud server and experiment terminal equipment, when a student performs an experiment, scheme determination, system design and simulation of an experiment project are completed on a computer by means of various EDA tools, then a designed program is downloaded to the experiment terminal equipment through a network, and the experiment terminal equipment returns an experiment result to the Web client used by the student in real time through the ari cloud server. The experimental mode breaks through the limitation on time and space, greatly improves the utilization rate of equipment, in the digital circuit cloud experimental system, the experimental terminal equipment generally comprises a wireless transceiver module, a main controller and an FPGA experimental board which are sequentially connected, the main controller receives and transmits signals through the wireless transceiver module, the main controller communicates with an Ali cloud server through the wireless transceiver module, a Web client sends a configuration file to the wireless transceiver module through a network, the wireless transceiver module is connected with the main controller end through a serial port, then a program is configured into the FPGA experimental board by the main controller, the configuration function of the main controller is very critical to the whole digital circuit cloud experimental system, the existing main controller generally adopts a single chip microcomputer for realizing the configuration function, but when a circuit built by using the configuration device of the type is configured on the FPGA experimental board, the situations of difficulty in downloading and driving, difficulty in installation or failure can occur, the configuration efficiency of the main controller is low, the stability of the whole digital circuit cloud experimental system is poor, and the digital circuit cloud experimental system is inconvenient to teach and use.

SUMMERY OF THE UTILITY MODEL

The utility model provides a configuration device based on FPGA programmable device, this configuration device's configuration efficiency is higher, and the stability of whole digital circuit cloud experimental system is better, and the teaching of being convenient for is used.

The utility model adopts the technical proposal that: a configuration device based on an FPGA programmable device is characterized by comprising a wireless transceiver module, a main control module and an FPGA module to be configured which are sequentially connected, wherein the main control module is the FPGA programmable device and comprises a clock generation module, a data receiving module, a random access memory and a configuration module which are sequentially connected, and the output end of the configuration module is connected with the input end of the FPGA module to be configured; the data receiving module comprises a trigger, a bit counter, a shift register and a byte counter which are connected in sequence, wherein a completion signal port in the output end of the byte counter is connected with the input end of the configuration module, and the rest ports are connected with the input end of the random access memory.

After the technical scheme more than adopting, compared with the prior art, the utility model has the following advantage:

the utility model discloses well main control module is FPGA programmable device, and this main control module can receive the configuration file that wireless transceiver module sent and dispose the FPGA module of treating the configuration in real time, when treating the FPGA module of configuration and dispose, the probability of configuration failure is lower, the reliability is higher, the configuration efficiency is higher, convenient to use and editor simultaneously.

As an improvement, the main control module is a Cyclone II series FPGA programmable device, and adopts PS mode configuration, so that the configuration is convenient.

As an improvement, the capacity of the main control module is 500 Kx8 bits, which is beneficial to reducing the cost.

As an improvement, the FPGA module to be configured comprises an output signal processing module, a clock source module, an equal-precision frequency meter, a multi-channel pulse signal source module, a DDS function signal generator and a DAC (digital-to-analog converter) for experiment, and is simple in structure and convenient to control.

As an improvement, the to-be-configured FPGA module further includes other experimental resource modules, so as to improve the universality of the to-be-configured FPGA module.

Drawings

FIG. 1 is a block diagram of a conventional digital circuit cloud experiment system

FIG. 2 is a block diagram of the overall structure of the present invention

FIG. 3 is a block diagram of a main controller

FIG. 4 is a block diagram of a data receiving module

FIG. 5 is a schematic diagram of the working state of the configuration module

Detailed Description

As shown in fig. 2 to 5, a configuration device based on an FPGA programmable device includes a wireless transceiver module, a main control module and an FPGA module to be configured, which are connected in sequence, wherein the main control module is a Cyclone II series FPGA programmable device and configures the FPGA module to be configured in a PS mode, the capacity of the main control module is 500K × 8 bits, the main control module includes a clock generation module, a data receiving module, a random access memory and a configuration module, which are connected in sequence, an output end of the configuration module is connected to an input end of the FPGA module to be configured, the clock generation module is used for generating a clock for serial port transceiving, and a frequency division coefficient thereof is set according to an actual baud rate; the random access memory adopts a double-port RAM; the input end of the data receiving module is connected with the wireless transceiving module and is used for receiving serial port data from the wireless transceiving module.

The data receiving module comprises a trigger, a bit counter, a shift register and a byte counter which are connected in sequence, a completion signal port done in the output end of the byte counter is connected with the input end of the configuration module, the rest ports are connected with the input end of the RAM, an AND gate is arranged on the front side of the trigger, an enable end en on the trigger is connected with the output end of the AND gate, the trigger further comprises a data end D and a clock end clk, an output end Q of the trigger is connected with the enable end en of the bit counter, the bit counter is also provided with a clock end, the output end of the bit counter is connected with the enable end en of the shift register, the shift register further comprises a data end D and a clock end, the output end of the shift register is connected with the input end of the byte counter, and clock signals generated by the clock module are sequentially connected with the clock end of the trigger, the clock end of the bit tech and the clock end of the shift register respectively, the output end of the slave wireless transceiving module is respectively connected with the data end of the trigger and the data end D of the shift register, and one input end of the AND gate is connected with the enabling end of the shift register. In the data receiving module, a trigger is used for detecting the initial position of a serial port, when the initial position is detected to change to start a bit counter to count, the bit counter can start a shift register to perform serial-to-parallel conversion operation on received data, after all bits of one byte are received, the shift register gives parallel data, a clock wrclk of a double-buckle RAM is written, and the clock wrclk acts on the byte counter to enable the byte counter to increment an address line wrad of the double-port RAM; after the data receiving module receives all the data of the configuration file, a done signal is generated to inform a configuration module at the rear stage to start configuration of the FPGA module to be configured. The dual-port RAM module is used for storing the configuration file data received from the data receiving module, and the system adopts a mode of firstly completing reception and then configuring, so that the dual-port RAM is required for caching the received configuration file data. The configuration module is implemented in the FPGA programmable device by using a state machine, where the state machine includes 8 states, which are S0 to S7 in sequence, as shown in fig. 5: in the figure, the condition of state transition is represented as "XX/XX", the left side of a slash represents a condition of state transition, the right side represents action, the whole configuration device is in an S0 state during initial power-on, a done signal is generated when the receiving of the data receiving module at the previous stage is completed, the signal triggers the state machine inside the configuration module to enter a next state S1, at this time, the configuration process is started, when the state S1 is entered, the configuration signal nConfig needs to be pulled down, the counter cnt is cleared, meanwhile, the data receiving function of the previous stage module is closed by a disable signal start, according to the requirements of the PS configuration specification of an Intel FPGA, the configuration signal nConfig needs to be pulled down for a certain time during configuration starting, and the clock overflow counter value N1 in the state machine represents; after pulling down for a period of time, proceeding to the S2 state, at this time, waiting for N2 time according to the specification, and then entering the S3 state; after the state of S3 is entered, the data are sequentially taken out from the dual-port RAM and transmitted to the signal wire according to the mode from low bit to high bit; in the S3 state, whether the total number of the currently written bytes is less than M or not needs to be judged, if the total number of the currently written bytes is less than M, all data are not configured, the RAM read address is increased progressively and the state S4 is switched to read the data in the RAM, then the state S5 is switched to transmit the data to the signal line bit by bit, and the states S5 and S6 are operations of sequentially transmitting 8 bits of 1 byte to the signal line according to the order of low-order priority; return to state S3 when transmission of all bits is complete; finally, when all data bytes are configured, delaying a period of time according to the specification requirement to wait for the interior of the FPGA module to be configured to complete the configuration process, wherein the waiting time is designated as N3 in a state machine; completing a configuration process after the waiting time; and then returns to state S0 to restart the start signal in preparation for the reception of the next profile.

The FPGA module to be configured comprises an output signal processing module, a clock source module, an equal-precision frequency meter, a multi-channel pulse signal source module, a DDS function signal generator, a DAC (digital-to-analog converter) for experiments and other experiment resource modules.

The utility model provides a configuration device adopts the programmable device based on FPGA, has overcome the drawback that current configuration device adopts the configuration success rate that the singlechip brought to be low, poor stability, can effectively improve configuration device's configuration efficiency and stability, convenient to use.

The above embodiments are only used to illustrate the technical solution of the present invention, and not to limit it. Although the present invention has been described in detail with reference to the foregoing embodiments, it should be understood by those skilled in the art that various changes and modifications can be made in the embodiments described in the foregoing embodiments, or equivalent changes and modifications can be made in the technical features of each part without departing from the scope of the embodiments of the present invention.

Claims

1. A configuration device based on an FPGA programmable device is characterized by comprising a wireless transceiver module, a main control module and an FPGA module to be configured which are sequentially connected, wherein the main control module is the FPGA programmable device and comprises a clock generation module, a data receiving module, a random access memory and a configuration module which are sequentially connected, and the output end of the configuration module is connected with the input end of the FPGA module to be configured; the data receiving module comprises a trigger, a bit counter, a shift register and a byte counter which are connected in sequence, wherein a completion signal port in the output end of the byte counter is connected with the input end of the configuration module, and the rest ports are connected with the input end of the random access memory.

2. The configuration device according to claim 1, wherein the main control module is a Cyclone II-series FPGA programmable device and is configured in a PS mode.

3. The configuration device based on FPGA programmable device of claim 2, wherein the capacity of the main control module is 500K x 8 bit.

4. The configuration device according to claim 1, wherein the FPGA module to be configured comprises an output signal processing module, a clock source module, an equal-precision frequency meter, a multi-channel pulse signal source module, a DDS function signal generator, and a DAC for experiment.

5. The configuration device based on the FPGA programmable device according to claim 4, wherein the FPGA module to be configured further comprises other experimental resource modules.