CN204595845U - A kind of one-way communication control device based on dual-wire bus - Google Patents
A kind of one-way communication control device based on dual-wire bus Download PDFInfo
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- CN204595845U CN204595845U CN201520218178.3U CN201520218178U CN204595845U CN 204595845 U CN204595845 U CN 204595845U CN 201520218178 U CN201520218178 U CN 201520218178U CN 204595845 U CN204595845 U CN 204595845U
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Abstract
The utility model provides a kind of one-way communication control device based on dual-wire bus, and main equipment 1 is connected by connection a and clock cable b from equipment 2 with multiple stage, and the data-signal that main equipment 1 produces comprises communication data, address date, pulse data; Clock signal comprises the 1st clock and the 2nd clock.Meter pulsing circuit 2a is comprised from equipment 2, condition judging circuit 2b, address comparison circuit 2c, latch cicuit 2d, data buffering circuit 2e, data-signal is sampled under the 1st clock signal, be transplanted on data buffering circuit to keep in, meter pulsing circuit number of pulses certificate under the 2nd clock counts, produce enable signal, address comparison circuit compares with temporary address the hardware address from equipment, produce judgment value, condition judging circuit is according to enable signal and judgment value, produce control signal, latch cicuit produces latch signal according to control signal and the 2nd clock signal, data buffering circuit is under the control of latch signal and the 2nd clock, temporary communication data is outputted to external equipment.
Description
Technical field
The utility model relates to a kind of one-way communication control device based on dual-wire bus, particularly relates to main equipment and multiple stage controls from the one-way communication between equipment.
Background technology
In order to realize the demand of main equipment connection control multiple stage from equipment, in prior art, be typically employed on main equipment as multiple stage is from interface corresponding to equipment de-sign, be connected with main equipment from equipment by corresponding interface, or designing microprocessor from equipment, knowledge method for distinguishing is being carried out to the control signal of main equipment.The former, main equipment mainboard needs multiple hardware interface, too much can take board area and microprocessor I/O resource like this; The latter, is needing design microprocessor and corresponding program from equipment, design that to implement more complicated loaded down with trivial details like this.No matter which kind of mode, all can increase design difficulty and maintenance cost.
The purpose of this utility model is to solve problems of the prior art, provides a kind of simplicity of design, is easy to the one-way communication device based on dual-wire bus safeguarded.
Utility model content
1st technical scheme of the present utility model is a kind of one-way communication control device based on dual-wire bus, it is characterized in that, comprise main equipment (1) and multiple stage from equipment (2), main equipment (1) is connected by common connection (a) and clock line (b) from equipment (2) with multiple stage, the data-signal that main equipment (1) produces and clock signal, each is sent to from equipment (2) by connection (a) and clock line (b), described data-signal comprises communication data, address date, pulse data, described clock comprises for communication data, 1st clock of address date sampling and the 2nd clock of paired pulses data counts, from equipment (2), there is different hardware addresss or identical hardware address described in each, or the described of a part has different hardware addresss from equipment (2), described comprising from equipment (2) counts pulsing circuit (2a), condition judging circuit (2b), address comparison circuit (2c), latch cicuit (2d), data buffering circuit (2e), described data buffering circuit (2e), to communication data under the control of the 1st clock, address date is sampled, the data of sampling are temporarily stored in the zones of different in described data buffering circuit (2e) respectively, the joint area of described address comparison circuit (2c) and the middle address data of described data buffering circuit (2e), to the address be temporarily stored in described data buffering circuit (2e) with compare from the hardware address of equipment (2), when both are consistent, (t1) produces judgment value, paired pulses data counts under the control of described meter pulsing circuit (2a) when the 2nd clock, when counting down to regulation figure place (t2), produce enable signal, described condition judging circuit (2b) produces judgment value at described address comparison circuit (2c), and when described meter pulsing circuit (2a) produces enable signal (t2), produce control signal, described latch cicuit (2d) is under the control of described 2nd clock, and when described condition judging circuit (2b) produces control signal (t2), produce latch signal, in described data buffering circuit (2e), the memory communicating region of data is connected with external equipment, when described latch cicuit (2d) produces latch signal (t2), temporary communication data is transported to described external equipment by described data buffering circuit (2e).
2nd technical scheme of the present utility model, based on the 1st technical scheme, is characterized in that, described 2nd clock is different from the 1st clock, and its state receiving the impulse duration maintenance logical one that connection (a) produces at meter pulsing circuit is constant.。
3rd technical scheme of the present utility model, based on the 2nd technical scheme, is characterized in that, described data buffering circuit (2e) carries out string and turns to described communication data, address date and change, memory communicating data, address date in a parallel fashion.
4th technical scheme of the present utility model is based on the 3rd technical scheme, it is characterized in that, described data buffering circuit (2e), according to the 1st clock signal that logical one and logical zero constantly convert, by described communication data and address date, be pushed to successively in buffering circuit, address date is at the low level of parallel data, communication data are positioned at a high position for parallel data, and low level is connected with described address comparison circuit (2c), and high-order and described external equipment is connected.
5th technical scheme of the present utility model is based on the 4th technical scheme, it is characterized in that, a part described from the hardware address of equipment (2) be the hardware address that can match or all described from the hardware address of equipment (2) be the hardware address that can match.
6th technical scheme of the present utility model is based on arbitrary technical scheme in the 1 to 5, and it is characterized in that, described external equipment is display device or control device, and described communication data are display data or control data.
Effect
According to the utility model, main equipment (1) and multiple stage adopt two-wire physical connection between equipment (2), main equipment (1) to coordinate hardware address from equipment (2) as long as send signal to connection (a) and clock line (b) with clock, can from multiple stage select to accept from equipment (2) its communication data sent from equipment (2), namely do not need to arrange on main equipment (1) respectively from the different interface from equipment connection, do not need from equipment (2), arranging the control microprocessor for identifying yet, there is the effect that design is easy and maintenance cost is low, and due to from equipment without the need to arranging the expensive device such as chip controlling microprocessor, decrease cost.
Accompanying drawing explanation
Fig. 1 is in the one-way communication control device based on dual-wire bus, main equipment and from the connection connection layout between equipment;
Fig. 2 is the structured flowchart from equipment;
Fig. 3 is the sequential chart of each signal.
Embodiment
As shown in Figure 1, the one-way communication control device based on dual-wire bus of the present utility model, be made up of from equipment 2 main equipment 1 and multiple stage, main equipment 1 and multiple stage adopt two-wire physical connection between equipment 2, and wherein, one is connection a, and another is clock line b.In the present embodiment, main equipment 1 is the control device in refuelling station's fuel charger, the various information that main equipment 1 produces in control procedure, needs to be shown by different display device.Each display device by different from equipment 2 (2 ', 2 " ...) with connection a; clock line b connects; to be sent to the clock signal the display signal of connection a and clock line b according to main equipment 1 from equipment 2; select display signal, be transported to connected display device and show.Each has the hardware address that can match from equipment 2, but also can be a part from equipment 2, there is the hardware address that can match.When hardware address is the mode that can match, the change of hardware address and upgrading are brought conveniently.Each hardware address from equipment 2 both can be the same or different also can a part different from the hardware address of equipment 2, can select as required.When different display device is needed to show same data, select identical hardware address, when not needing, select different hardware addresss.
Be provided with the microprocessor 1a producing signal and clock in main equipment 1, signal comprises display (communication) data, address date, pulse data; Clock comprises for communication data, the 1st clock of address date sampling and the 2nd clock of paired pulses data counts.The cycle of the 1st clock needs setting according to what sample, and the setting value that the 2nd clock counts according to number of pulses is arranged, and namely the 2nd clock keeps logical one state constant at meter impulse duration, and in the logical one period of state of the 2nd clock, pulse can be counted setting value.
Address date one bit table is shown with 2 kinds of address dates.
Count pulse is the Nth power of 2, and N is non-zero and N is integer.
Each from equipment 2 (2 ', 2 " ...) except hardware address, there is identical structure, be described according to Fig. 2 below.Meter pulsing circuit 2a is comprised, condition judging circuit 2b, address comparison circuit 2c, latch cicuit 2d, data buffering circuit 2e from equipment 2.
The following sequential chart according to Fig. 3, is described the duty from equipment 2.
In the t0 moment, connection a produces display data, generation the 1st clock on clock line b.Data buffering circuit 2e, shows data sampling according to the logical one of the 1st clock and the continuous transfer pair of logical zero, and the data of sampling are temporarily stored in data buffering circuit 2e to high position propelling movement by low level according to order.
After display data sampling completes, same under the control of the 1st clock to address data sampling, the data of sampling to be pushed to a high position by low level according to order and are temporarily stored in data buffering circuit 2e.After having sampled, display data are positioned at a high position for working storage, and address date is positioned at the low level of working storage, complete string and turn conversion also.A high position (storing the region of display data) for working storage is connected with display device in a parallel fashion, and the low level (region of address data) of working storage is connected with address comparison circuit 2c in a parallel fashion.Address comparison circuit 2c is connected with the storer stored from equipment 2 hardware address.
In address comparison circuit 2c, the address be temporarily stored in data buffering circuit 2e constantly compares with the hardware address from equipment 2, and produce judgment value during both consistent t1, this judgment value is transported to condition judging circuit 2b.
When the 1st clock, because the logic state of the 1st clock constantly converts, meter pulsing circuit 2a cannot effectively to the step-by-step counting (i.e. constantly counting and zero setting) showing data and address date, when the 2nd clock, the logical one period of state of the 2nd clock is arranged according to the setting value of count pulse quantity, logical one state when the 2nd clock counts under controlling that pulsing circuit 2a starts effective counting and the data of data buffering circuit 2e can not be affected, number of pulses certificate count down to setting time t2, meter pulsing circuit 2a produces enable signal, this enable signal is output to condition judging circuit 2b.
Now, condition judging circuit 2b produces control signal, and control signal is output to latch cicuit 2d.
Due to the logical one state that the clock on latch cicuit 2d is the 2nd clock, under the control of the 2nd clock, latch cicuit 2d produces latch signal, and this latch signal is output to data buffering circuit 2e.
Under the control of latch signal, the display certificate be temporarily stored in data buffering circuit 2e carries display device in a parallel fashion, shows.
In the t3 moment, the 2nd clock changes to logical zero by logical one state, and now, due to the count value zero setting of meter pulsing circuit 2a, the enable signal of meter pulsing circuit 2a, the control signal of condition judging circuit 2b and the latch signal of latch cicuit 2d stop exporting.
When the display data of next frame arrive, repeat above-mentioned process.Further, the data stored in data buffering circuit 2e can replaced by new data the renewal of data, in the process that address date upgrades, owing to producing inconsistent with the hardware address from equipment 2, the output of comparator circuit 2c stopping judgment value.
From illustrating above, the utility model, based on serial dual bus control technology, by cascade system, arranges the hardware address can joined from equipment, is realizing any one from the basis of equipment work, can expand realize multiple from equipment work.
Because main equipment 1 and multiple stage adopt two-wire physical connection between equipment 2, as long as main equipment sends data to connection a and clock cable b and clock can be selected to accept its display data sent from equipment, namely do not need main equipment 1 to have and corresponding interface is set respectively with from equipment, do not need from equipment 2 to arrange the microprocessor controlled yet, there is the effect that design is easy and maintenance cost is low, and due to from equipment without the need to expensive device such as control chips, decrease cost.
Further, owing to adopting the clock of two kinds of different cycles, meter pulsing circuit 2a does not need to distinguish display data, address date and pulse data and can number of pulses certificate count, and simplifies meter pulsing circuit 2a, reduce further cost.
The foregoing is only preferred embodiment of the present utility model; not in order to limit the utility model; as in the present embodiment; with the display data instance of refuelling station's fuel charger, the utility model is illustrated; but be not limited to refuelling station's fuel charger and display data; also can be used for the transmission of the control data in control device; as long as within spirit of the present utility model and principle; any amendment of doing, equivalent replacement, improvement etc., all should be included within protection domain of the present utility model.
Claims (6)
1. the one-way communication control device based on dual-wire bus, it is characterized in that, comprise main equipment (1) and multiple stage from equipment (2), main equipment (1) is connected by common connection (a) and clock line (b) from equipment (2) with multiple stage, the data-signal that main equipment (1) produces and clock signal, each is sent to from equipment (2) by connection (a) and clock line (b), described data-signal comprises communication data, address date, pulse data, described clock comprises for communication data, 1st clock of address date sampling and the 2nd clock of paired pulses data counts, from equipment (2), there is different hardware addresss or identical hardware address described in each, or the described of a part has different hardware addresss from equipment (2),
Described comprising from equipment (2) counts pulsing circuit (2a), condition judging circuit (2b), address comparison circuit (2c), latch cicuit (2d), data buffering circuit (2e),
Described data buffering circuit (2e), to communication data, address date sampling under the control of the 1st clock, the data of sampling are temporarily stored in the zones of different in described data buffering circuit (2e) respectively,
The joint area of described address comparison circuit (2c) and the middle address data of described data buffering circuit (2e), to the address be temporarily stored in described data buffering circuit (2e) with compare from the hardware address of equipment (2), when both are consistent, (t1) produces judgment value
Paired pulses data counts under the control of described meter pulsing circuit (2a) when the 2nd clock, when counting down to regulation figure place (t2), produces enable signal,
Described condition judging circuit (2b) produces judgment value at described address comparison circuit (2c), and when described meter pulsing circuit (2a) produces enable signal (t2), produces control signal,
Described latch cicuit (2d) under the control of described 2nd clock, and when described condition judging circuit (2b) produces control signal (t2), produces latch signal,
In described data buffering circuit (2e), the memory communicating region of data is connected with external equipment, when described latch cicuit (2d) produces latch signal (t2), temporary communication data is transported to described external equipment by described data buffering circuit (2e).
2. a kind of one-way communication control device based on dual-wire bus according to claim 1, it is characterized in that, described 2nd clock is different from the 1st clock, and its state receiving the impulse duration maintenance logical one that connection (a) produces at meter pulsing circuit is constant.
3. a kind of one-way communication control device based on dual-wire bus according to claim 2, it is characterized in that, described data buffering circuit (2e) carries out string and turns to described communication data, address date and change, memory communicating data, address date in a parallel fashion.
4. a kind of one-way communication control device based on dual-wire bus according to claim 3, it is characterized in that, described data buffering circuit (2e), according to the 1st clock signal that logical one and logical zero constantly convert, by described communication data and address date, be pushed to successively in buffering circuit, address date is at the low level of parallel data, communication data are positioned at a high position for parallel data, low level is connected with described address comparison circuit (2c), and high-order and described external equipment is connected.
5. a kind of one-way communication control device based on dual-wire bus according to claim 4, it is characterized in that, a part described from the hardware address of equipment (2) be the hardware address that can match or all described from the hardware address of equipment (2) be the hardware address that can match.
6. a kind of one-way communication control device based on dual-wire bus described any one of claim 1 to 5, it is characterized in that, described external equipment is display device or control device, and described communication data are display data or control data.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201520218178.3U CN204595845U (en) | 2015-04-10 | 2015-04-10 | A kind of one-way communication control device based on dual-wire bus |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201520218178.3U CN204595845U (en) | 2015-04-10 | 2015-04-10 | A kind of one-way communication control device based on dual-wire bus |
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| Publication Number | Publication Date |
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| CN204595845U true CN204595845U (en) | 2015-08-26 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN201520218178.3U Withdrawn - After Issue CN204595845U (en) | 2015-04-10 | 2015-04-10 | A kind of one-way communication control device based on dual-wire bus |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104750648A (en) * | 2015-04-10 | 2015-07-01 | 北京拓盛电子科技有限公司 | Unidirectional communication control device and method based on two-wire bus |
-
2015
- 2015-04-10 CN CN201520218178.3U patent/CN204595845U/en not_active Withdrawn - After Issue
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104750648A (en) * | 2015-04-10 | 2015-07-01 | 北京拓盛电子科技有限公司 | Unidirectional communication control device and method based on two-wire bus |
| CN104750648B (en) * | 2015-04-10 | 2017-07-21 | 北京拓盛电子科技有限公司 | One-way communication control device and method based on dual-wire bus |
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| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| AV01 | Patent right actively abandoned |
Granted publication date: 20150826 Effective date of abandoning: 20170721 |