CN205959200U - A latch circuit for I2C bus data transmission - Google Patents
A latch circuit for I2C bus data transmission Download PDFInfo
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- CN205959200U CN205959200U CN201620608245.7U CN201620608245U CN205959200U CN 205959200 U CN205959200 U CN 205959200U CN 201620608245 U CN201620608245 U CN 201620608245U CN 205959200 U CN205959200 U CN 205959200U
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Abstract
The utility model discloses a latch circuit for I2C bus data transmission, include: first comparator, SCL is connected with the serial clock line, exports a control signal, the second comparator is connected with SCL, serial data line SDA, exports the 2nd control signal, the logical gate is connected with SCL, SDA, second comparator, and according to SCL signal, the 3rd control signal of SDA signal and the 2nd control signal generation, the latch is with first comparator and switch door circuit connection, according to a control signal and the 3rd control signal output fourth control signal, the latch still sends fourth control signal to SDA, and fourth control signal is used for controlling the SDA signal and keeps the virgin state. The utility model discloses making the SDA signal latched when transmitting data, can not carrying out level fluctuation, it is unusual to prevent that the SDA transmission that the maloperation leads to from appearing in TCON or EEPROM.
Description
Technical field
This utility model belongs to technical field of integrated circuits, is used for I more particularly, to a kind of2C bus data transfer
Latch cicuit.
Background technology
I2C bus be by serial data line (Serial Data, SDA) and serial time clock line (Serial Clock Line,
SCL the universal serial bus) constituting, can send and receive data.Carry out bi-directionally transmitted between IC and IC, highest transfer rate
100kbps.There is unique address for each IC being connected in parallel in a bus.
I2C bus has two holding wires, and one is SDA (data wire), and one is SCL (clock line), clock signal be by
Master devices produce.I2C bus total three types signal in transmission data procedures, they are respectively：Commencing signal, end
Signal and answer signal.
Commencing signal：When SCL is high level, SDA is changed into low transition by high level, represents and starts to communicate.
End signal：When SCL is high level, SDA is changed into high level saltus step by low level, represents and terminates communication.
Answer signal：The IC of receiving data, after receiving a byte data, sends specifically to the IC sending data
Low level pulse, represents and has been received by data.
Beginning and end signal is all sent by main frame, and answer signal is sent by slave, and beginning and end communicates
The sequential of process is as shown in Figure 1.
In practical communication, I2When C bus carries out data transmission, the signal on clock line SCL is data between high period
Data on line SDA must keep stable, is between low period only in the signal on clock line SCL, the high electricity on data wire
Flat or low level state just allows change, and when only SCL signal is for high level the data transmitted is just effectively.
When maloperation in TCON or EEPROM, may cause when SCL signal is for high level, SDA signal is going out
Existing level jumping phenomena (as shown in Figure 2), leads to data transmission fault.
Utility model content
The purpose of this utility model is to provide one kind to be used for I2The latch cicuit of C bus data transfer.
According to one side of the present utility model, one kind is provided to be used for I2The latch cicuit of C bus data transfer, including：The
One comparator, is connected with serial time clock line SCL, for receiving SCL signal, and controls letter according to described SCL signal output first
Number；Second comparator, is connected with serial time clock line SCL, serial data line SDA, for receiving described SCL signal and SDA signal,
And the second control signal is exported according to described SCL signal and SDA signal；Logical gate, with described serial time clock line SCL, string
Row data wire SDA, the second comparator connect, for receiving SCL signal, SDA signal and the second control signal, and according to described
SCL signal, SDA signal and the second control signal generate the 3rd control signal, and latch, with described first comparator and institute
State logical gate to connect, for receiving the first control signal and the 3rd control signal, and according to described first control signal
Export the 4th control signal with the 3rd control signal；Wherein, described latch is also connected with serial data line SDA, for institute
State serial data line SDA and send the 4th control signal, described 4th control signal is used for controlling SDA signal to maintain the original state.
Preferably, described first comparator includes first input end, the second input and the first outfan, wherein, institute
State first input end to be connected with serial time clock line SCL, the second input end grounding, the first outfan is connected with described latch.
Preferably, described second comparator includes the 3rd input, the 4th input and the second outfan, wherein, institute
State the 3rd input to be connected with serial time clock line SCL, described 4th input is connected with serial data line SDA, described second is defeated
Go out end to be connected with described latch.
Preferably, described latch includes the 5th input, the 6th input and the 3rd outfan, wherein, described
Five inputs are connected with the first outfan of described first comparator.
Preferably, when described 3rd outfan is in-phase output end, described 3rd outfan and described serial data line SDA
Connect；When described 3rd outfan is reversed-phase output, described 3rd outfan passes through a logic inverter and described serial number
Connect according to line SDA.
Preferably, described logical gate includes：Enumerator, is connected with described serial time clock line SCL, for obtaining SCL
The high level number of times of signal；Circuit for detecting, is connected with described serial time clock line SCL, serial data line SDA, for detecting SCL letter
Number it is in whether SDA signal during high level occurs level to change, and the 5th control signal is generated according to detecting result；Logic or
Door, is connected with described second comparator and described circuit for detecting, for according to described second control signal and described 5th control
Signal generation the 3rd control signal；Wherein, described circuit for detecting is also connected with described enumerator, when described circuit for detecting detects
SCL signal is in high level and SDA signal occurs, when high level is to low level change, to start enumerator and start counting up.
Preferably, described logic sum gate is also connected with the 6th input of described latch, for described latch
6th input inputs the 3rd control signal.
Preferably, when described enumerator is in count status, described circuit for detecting stops detecting.
Preferably, described enumerator is N system Counter, when counting up to N, sends feedback letter to described circuit for detecting
Number.
Preferably, described circuit for detecting starts to detect according to described feedback signal.
This utility model provide for I2The latch cicuit of C bus data transfer quilt in transmission data by SDA signal
Latch it is impossible to enter line level change, prevent TCON or EEPROM from the SDA transmission abnormality that maloperation leads to occurring, meeting simultaneously
During to transmission abnormality problem, improve analyzing efficiency.
Brief description
By the description to this utility model embodiment referring to the drawings, of the present utility model above-mentioned and other mesh
, feature and advantage will be apparent from, in the accompanying drawings：
Fig. 1 shows I2C bus is from the normal timing waveform during terminating to communicate that starts to communicate to；
Fig. 2 shows I2C bus is from the abnormal timing waveform during terminating to communicate that starts to communicate to；
Fig. 3 a-3b shows according to the offer of this utility model embodiment for I2The latch cicuit of C bus data transfer
Structural representation；
Fig. 4 shows according to the offer of this utility model embodiment for I2The latch cicuit work of C bus data transfer
When I2C bus is from the timing waveform during terminating to communicate that starts to communicate to.
Specific embodiment
It is more fully described various embodiment of the present utility model hereinafter with reference to accompanying drawing.In various figures, identical
Element to be represented using same or similar reference.For the sake of clarity, the various pieces in accompanying drawing are not drawn to paint
System.
This utility model can present in a variety of manners, some of them example explained below.
Fig. 3 a- Fig. 3 b show this utility model embodiment provide for I2The latch cicuit of C bus data transfer
Structural representation.As shown in Figure 3 a-3b, described latch cicuit includes first comparator 101, the second comparator 102, switch gate electricity
Road 103 and latch 104.
Wherein, first comparator 101, are connected with serial time clock line SCL, for receiving SCL signal, and according to described SCL
Signal output first control signal.
In the present embodiment, described first comparator 101 includes first input end A, the second input B and the first output
End E, wherein, described first input end A is connected with serial time clock line SCL, second input B be grounded, the first outfan E with described
Latch 104 connects.
Wherein, first input end A input SCL signal, the second input B ground connection, that is, the second input B inputs low electricity always
Ordinary mail number；When the SCL signal of first input end A input is high level, the first control signal of the first outfan E output is low
Level signal；When the SCL signal of first input end A input is low level, the first control signal of the first outfan E output is
High level signal.
Second comparator 102, is connected with serial time clock line SCL, serial data line SDA, for receive described SCL signal and
SDA signal, and the second control signal is exported according to described SCL signal and SDA signal.
In the present embodiment, described second comparator 102 includes the 3rd input C, the 4th input D and the second output
End F, wherein, described 3rd input C is connected with serial time clock line SCL, and described 4th input D and serial data line SDA is even
Connect, described second outfan F is connected with described latch 104.
Wherein, the 3rd input C input SCL signal, the 4th input D input SDA signal；When the 3rd input C inputs
SCL signal be low level, the 4th input D input SDA signal be high level when, second outfan F output second control
Signal processed is high level signal；When the SCL signal of the 3rd input C input is high level, the SDA letter of the 4th input D input
Number whether high level or during low level, the second control signal of the second outfan F output is low level signal.
Logical gate 103, is connected with described serial time clock line SCL, serial data line SDA, the second comparator 102, uses
In reception SCL signal, SDA signal and the second control signal, and letter is controlled according to described SCL signal, SDA signal and second
Number generate the 3rd control signal.
In the present embodiment, described logical gate 103 includes enumerator 1031, circuit for detecting 1032 and logic sum gate
1033.
Wherein, described enumerator 1031 is connected with described serial time clock line SCL, for obtaining the high level of SCL signal
Number.
Described enumerator 1031 is N system Counter, and wherein, N represents the byte number of each periodic transfer.Work as SCL signal
High level occurs, then enumerator 1031 counts once, when counting down to N, carry, and sends to circuit for detecting 1032
Feedback signal.
Circuit for detecting 1032, is connected with described serial time clock line SCL, serial data line SDA, for detecting at SCL signal
When high level, whether SDA signal occurs level to change, and generates the 5th control signal according to detecting result.
In the present embodiment, circuit for detecting 1032 is connected with SCL line and SDA line respectively, for detecting SCL signal and SDA
Signal.When circuit for detecting 1032 detects SCL signal for high level, SDA signal does not occur from high level to low level
Change, then the 5th control signal exporting is high level signal；When circuit for detecting 1032 detect SCL signal be high level when and
SDA signal occurs from high level to low level change, then the 5th control signal exporting is low level signal.
Wherein, described circuit for detecting 1032 is also connected with described enumerator 1031, when described circuit for detecting 1032 detects
SCL signal is in high level and SDA signal occurs, when high level is to low level change, to start enumerator 1031 and start to count
Number.Now described enumerator 1031 is in count status, and described circuit for detecting 1032 stops detecting.
In a preferred embodiment, described circuit for detecting 1032 is receiving the feedback signal of enumerator 1031 transmission
When, start again to detect.
Logic sum gate 1033, is connected with described second comparator 102 and described circuit for detecting 1032, for according to described
Two control signals and described 5th control signal generate the 3rd control signal.
In the present embodiment, when the second control signal and the 5th control signal are low level signal, logic sum gate
3rd control signal of 1033 outputs is low level signal.
Latch 104, is connected with described first comparator 101 and described logical gate 103, for receiving the first control
Signal processed and the 3rd control signal, and the 4th control signal is exported according to described first control signal and the 3rd control signal.
In the present embodiment, described latch 104 includes the 5th input J, the 6th input K and the 3rd outfan,
Wherein, described 5th input J is connected with the first outfan E of described first comparator 101, and the 6th input K is opened with described
The outfan closing the logic sum gate 1033 in gate circuit 103 connects, for receiving the first control signal and the 3rd control signal.
When the first control signal and the 3rd control signal are low level signal, described latch 102 is operated in holding
State；Other states are invalid.Now, the 3rd outfan Q of described latch 104 exports the 4th control signal.
In a preferred embodiment, described latch 104 is also connected with serial data line SDA, for described string
Row data wire SDA sends the 4th control signal, and described 4th control signal is used for controlling SDA signal to maintain the original state it is impossible to send out
The change of raw level.
In a preferred embodiment, the 3rd outfan can be in-phase output end Q (as shown in Figure 3 a), described latch
3rd outfan of device 104 is connected with described serial data line SDA.
In a preferred embodiment, the 3rd outfan can also be reversed-phase output(as shown in Figure 3 b), now,
3rd outfan of described latch is connected with described serial data line SDA by a logic inverter 105.
Fig. 4 shows according to the offer of this utility model embodiment for I2The latch cicuit work of C bus data transfer
When I2, from the timing waveform during terminating to communicate that starts to communicate to, this circuit is by SDA signal in transmission data for C bus
It is latched it is impossible to enter line level change, prevent TCON or EEPROM from the SDA transmission abnormality that maloperation leads to occurring.
This utility model provide for I2The latch cicuit of C bus data transfer quilt in transmission data by SDA signal
Latch it is impossible to enter line level change, prevent TCON or EEPROM from the SDA transmission abnormality that maloperation leads to occurring, meeting simultaneously
During to transmission abnormality problem, improve analyzing efficiency.
According to embodiment of the present utility model as described above, these embodiments do not have all of details of detailed descriptionthe,
Do not limit the specific embodiment that this utility model is only described yet.Obviously, as described above, a lot of modifications and change can be made
Change.This specification is chosen and is specifically described these embodiments, is to preferably explain that principle of the present utility model and reality should
With so that skilled artisan can be well using this utility model and repairing on the basis of this utility model
Change use.Protection domain of the present utility model should be defined by the scope that this utility model claim is defined.
Claims (10)
1. one kind is used for I2The latch cicuit of C bus data transfer is it is characterised in that include：
First comparator, is connected with serial time clock line SCL, for receiving SCL signal, and exports first according to described SCL signal
Control signal；
Second comparator, is connected with serial time clock line SCL, serial data line SDA, for receiving described SCL signal and SDA letter
Number, and the second control signal is exported according to described SCL signal and SDA signal；
Logical gate, is connected with described serial time clock line SCL, serial data line SDA, the second comparator, for receiving SCL letter
Number, SDA signal and the second control signal, and generate the 3rd according to described SCL signal, SDA signal and the second control signal
Control signal,
Latch, is connected with described first comparator and described logical gate, for receiving the first control signal and
Three control signals, and the 4th control signal is exported according to described first control signal and the 3rd control signal；
Wherein, described latch is also connected with serial data line SDA, for sending the 4th control to described serial data line SDA
Signal, described 4th control signal is used for controlling SDA signal to maintain the original state.
2. latch cicuit according to claim 1 it is characterised in that described first comparator include first input end,
Two inputs and the first outfan, wherein, described first input end is connected with serial time clock line SCL, the second input end grounding,
First outfan is connected with described latch.
3. latch cicuit according to claim 2 it is characterised in that described second comparator include the 3rd input,
Four inputs and the second outfan, wherein, described 3rd input is connected with serial time clock line SCL, described 4th input
It is connected with serial data line SDA, described second outfan is connected with described latch.
4. latch cicuit according to claim 3 is it is characterised in that described latch includes the 5th input, the 6th defeated
Enter end and the 3rd outfan, wherein, described 5th input is connected with the first outfan of described first comparator.
5. latch cicuit according to claim 4 it is characterised in that described 3rd outfan be in-phase output end when, institute
State the 3rd outfan to be connected with described serial data line SDA；
When described 3rd outfan is reversed-phase output, described 3rd outfan passes through a logic inverter and described serial data line
SDA connects.
6. latch cicuit according to claim 5 is it is characterised in that described logical gate includes：
Enumerator, is connected with described serial time clock line SCL, for obtaining the high level number of times of SCL signal；
Circuit for detecting, is connected with described serial time clock line SCL, serial data line SDA, is in high level for detecting SCL signal
When SDA signal whether occur level change, and according to detecting result generate the 5th control signal；
Logic sum gate, is connected with described second comparator and described circuit for detecting, for according to described second control signal and institute
State the 5th control signal and generate the 3rd control signal；
Wherein, described circuit for detecting is also connected with described enumerator, is in high level when described circuit for detecting detects SCL signal
And SDA signal occurs, when high level is to low level change, to start enumerator and start counting up.
7. latch cicuit according to claim 6 it is characterised in that described logic sum gate also with described latch the 6th
Input connects, for inputting the 3rd control signal to the 6th input of described latch.
8. latch cicuit according to claim 7 is it is characterised in that when described enumerator is in count status, described detects
Slowdown monitoring circuit stops detecting.
9. latch cicuit according to claim 8 is it is characterised in that described enumerator is N system Counter, when counting up to
During N, send feedback signal to described circuit for detecting.
10. latch cicuit according to claim 9 is it is characterised in that described circuit for detecting is opened according to described feedback signal
Begin to detect.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201620608245.7U CN205959200U (en) | 2016-06-20 | 2016-06-20 | A latch circuit for I2C bus data transmission |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201620608245.7U CN205959200U (en) | 2016-06-20 | 2016-06-20 | A latch circuit for I2C bus data transmission |
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| CN205959200U true CN205959200U (en) | 2017-02-15 |
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Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106953735A (en) * | 2017-04-27 | 2017-07-14 | 珠海格力电器股份有限公司 | Iic bus unlocking method and the communication system based on iic bus |
| CN108563598A (en) * | 2018-03-02 | 2018-09-21 | 上海芯导电子科技有限公司 | A kind of I from wake-up2C communication architecture systems |
| CN112051890A (en) * | 2020-08-27 | 2020-12-08 | 海光信息技术有限公司 | Clock control method of I2C bus, master device and device system connected with I2C bus |
| CN112540943A (en) * | 2020-11-16 | 2021-03-23 | 北京中电华大电子设计有限责任公司 | Circuit structure and method for preventing I2C interface from mistakenly waking up SOC (system on chip) |
| CN114996196A (en) * | 2022-08-04 | 2022-09-02 | 北京数字光芯集成电路设计有限公司 | I2C communication drive circuit, micro display chip and electronic equipment |
| CN116340241A (en) * | 2023-05-19 | 2023-06-27 | 无锡国芯微高新技术有限公司 | Serial communication protection method, device, equipment and storage medium |
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2016
- 2016-06-20 CN CN201620608245.7U patent/CN205959200U/en active Active
Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106953735A (en) * | 2017-04-27 | 2017-07-14 | 珠海格力电器股份有限公司 | Iic bus unlocking method and the communication system based on iic bus |
| CN108563598A (en) * | 2018-03-02 | 2018-09-21 | 上海芯导电子科技有限公司 | A kind of I from wake-up2C communication architecture systems |
| CN112051890A (en) * | 2020-08-27 | 2020-12-08 | 海光信息技术有限公司 | Clock control method of I2C bus, master device and device system connected with I2C bus |
| CN112051890B (en) * | 2020-08-27 | 2022-07-26 | 海光信息技术股份有限公司 | Clock control method of I2C bus, master device and device system connected with I2C bus |
| CN112540943A (en) * | 2020-11-16 | 2021-03-23 | 北京中电华大电子设计有限责任公司 | Circuit structure and method for preventing I2C interface from mistakenly waking up SOC (system on chip) |
| CN112540943B (en) * | 2020-11-16 | 2023-10-10 | 北京中电华大电子设计有限责任公司 | Circuit structure and method for preventing I2C interface from waking up SOC system by mistake |
| CN114996196A (en) * | 2022-08-04 | 2022-09-02 | 北京数字光芯集成电路设计有限公司 | I2C communication drive circuit, micro display chip and electronic equipment |
| CN114996196B (en) * | 2022-08-04 | 2022-10-21 | 北京数字光芯集成电路设计有限公司 | I2C communication drive circuit, micro display chip and electronic equipment |
| CN116340241A (en) * | 2023-05-19 | 2023-06-27 | 无锡国芯微高新技术有限公司 | Serial communication protection method, device, equipment and storage medium |
| CN116340241B (en) * | 2023-05-19 | 2023-08-01 | 无锡国芯微高新技术有限公司 | Serial communication protection method, device, equipment and storage medium |
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| GR01 | Patent grant | ||
| CP01 | Change in the name or title of a patent holder |
Address after: 215301, 1, Longteng Road, Kunshan, Jiangsu, Suzhou Patentee after: Kunshan Longteng Au Optronics Co Address before: 215301, 1, Longteng Road, Kunshan, Jiangsu, Suzhou Patentee before: Kunshan Longteng Optronics Co., Ltd. |
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| CP01 | Change in the name or title of a patent holder |