CN101841542B - Method for realizing PROFIBUS master station communication protocol based on FPGA (Field Programmable Gate Array) technology - Google Patents
Method for realizing PROFIBUS master station communication protocol based on FPGA (Field Programmable Gate Array) technology Download PDFInfo
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Abstract
The invention relates to a method for realizing PROFIBUS master station communication protocol based on an FPGA (Field Programmable Gate Array)technology. In the method, firstly, a field programmable gate array (FPGA) waits for a micro control unit to send the master station information; secondly, the micro control unit sends the master station information to the FPGA; thirdly, the FPGA starts the bus message monitoring; fourthly, the FPGA receives and analyzes the message; fifthly, the micro control unit determines the message to be sent according to the field bus communication standard; sixthly, the FPGA sends the messages by package; and seventhly, the FPGA turns from a message sending state into a message receiving state; and then, the method returns to the step 4. The method realizes high-speed communication between a PROFIBUS master station and a PROFIBUS slave station by using the FPGA technology and increases the communication rate up to 12 Mbit/s.
Description
Technical field
The present invention relates to a kind ofly need not use the special-purpose PROFIBUS main website protocol chip (ASPC2) of Siemens Company, but realize the method for industrial field bus PROFIBUS master station communication protocol through on-site programmable gate array FPGA.This method can be applied to the design of PROFIBUS main website, realizes the communication cycle DPV0 of PROFIBUS and the communication function of acyclic communication DPV1.
Background technology
At present, existing two kinds of schemes can be selected when exploitation PROFIBUS main website: a kind of method is to adopt the solution of the special-purpose main website protocol chip of micro-control unit (MCU)+Siemens Company (ASPC2), and its agreement has cured among special chip (ASPC2).
Another kind method is to adopt the solution of micro-control unit (MCU)+software, utilizes software programming to realize fieldbus international standard PROFIBUS-DP master station communication protocol;
Stipulate that transmission rate reaches as high as 12Mbit/s in the industrial field bus PROFIBUS communication international standard.
Use first kind of scheme, can reach the specification requirement in the standard fully, but that special chip receives technology is underground, restrictions such as patent protection, also there is great risk in the chip supply that in market competition, relies on the rival.
Use second kind of scheme to realize the PROFIBUS-DP master station communication protocol; Because traffic rate receives the restriction transmission rate of micro-control unit (MCU) operating frequency to be up to 1.5Mbit/s; Micro-control unit also will receive the work of message, analytic message except confirming to send content of message according to the field bus communication standard, the waste bus time; Can not the fast processing data flow, thereby can't reach the highest 12Mbit/S of transmission rate.
Summary of the invention
For addressing the above problem; The purpose of this invention is to provide a kind of method that realizes the PROFIBUS master station communication protocol based on the FPGA technology; Come the data flow between the fast processing PROFIBUS master-salve station through the on-site programmable gate array FPGA technology; Shared the major part work of micro-control unit MCU, realized the high-speed communication of PROFIBUS main website and slave station, traffic rate can reach 12Mbit/s.
For realizing above-mentioned purpose, the present invention adopts following technical scheme:
The present invention is a kind of method based on FPGA technology realization PROFIBUS master station communication protocol, and it is characterized in that: this method may further comprise the steps:
Step is 1.: field programmable gate array waits for that in the back initialization that powers on micro-control unit sends master information;
Step is 2.: micro-control unit sends master information to the master information register of field programmable gate array, and master information is made up of main website station address, baud rate, timer time value;
Step is 3.: micro-control unit sends to field programmable gate array and is initialized to function signal, confirm that master information is sent to finish, receive be initialized to function signal after, field programmable gate array starts bus message to be monitored, and waits for that message receives;
Step is 4.: micro-control unit is opened the current timer in the field programmable gate array; Field programmable gate array is being waited for bus data in the timer time scope of front opening, and bus data is the message that receives of main website self or the message of slave station response;
If field programmable gate array does not receive bus data in the timer time scope; Then then produce interrupt request singal in the back at current timer; And interrupt request singal sent to micro-control unit; Simultaneously, the reception end signal position of the status register one of field programmable gate array remains on initial condition;
Micro-control unit reads the value of the reception end signal position of field programmable gate array internal state register one after receiving interrupt request singal, the value of this reception end signal position is 0, and then micro-control unit judges that this interrupt signal is that overtime nothing receives interruption;
If field programmable gate array receives bus data in the timer time scope; But heading is not one of 0x68,0x10,0xDC, 0xe5; Then then produce interrupt request singal in the back at current timer; And interrupt request singal sent to micro-control unit, simultaneously, the reception end signal position of the status register one of field programmable gate array remains on initial condition;
Micro-control unit reads the value of the reception end signal position of field programmable gate array internal state register one after receiving interrupt request singal, the value of this reception end signal position is 0, and then micro-control unit judges that this interrupt signal is that overtime nothing receives interruption;
If field programmable gate array receives bus data in the timer time scope; And heading is one of 0x68,0x10,0xDC, 0xe5, and then field programmable gate array stops current timer timing after receiving complete frame data; No longer because timer expiry sends interrupt request singal to micro-control unit; Simultaneously, the serial received processing module of field programmable gate array is judged the message kind according to the heading that receives, and resolves as follows respectively then:
If heading is 0x68; Field programmable gate array just judges through second, third byte that reads message whether message has size error: if second, third byte length equates; Just thinking does not have size error, with the Gao Siwei maintenance initial value of status register two; If second, third byte length is unequal, just thinking has size error, and high four positions of status register two are worth accordingly; Field programmable gate array has judged whether the type of message mistake through reading the 4th byte of message; If the 4th byte is identical with heading, just there is not the type of message mistake, with the Gao Siwei maintenance initial value of status register two; If the 4th byte and heading are inequality, the type of message mistake is just arranged, high four positions of status register two are worth accordingly; Field programmable gate array judges through reading the 5th byte whether this message issues this main website; If the 5th byte is identical with the main website address value that micro-control unit sends in the master information register; Just think that this message issues this main website; If the main website address value that the 5th byte and micro-control unit send in the master information register is inequality, just think that this message do not issue this main website; Field programmable gate array judges whether to be the message of transmitting-receiving certainly through reading the 6th byte, if the 6th byte is identical with the main website address value, just thinks from the message of receiving and dispatching; If the 6th byte and main website address value are inequality, just think the message that slave station is sent out; Field programmable gate array continues to read all the other bytes of the 6th byte back according to message length then; Field programmable gate array is done even parity check to the penult byte that receives and is judged; The even parity check judgment mode is: field programmable gate array with the check of the frame that calculates with the message that receives in the penult byte relatively judged whether check errors: if identical; Just judge no even parity check mistake, with the Gao Siwei maintenance initial value of status register two, if different; Just judging has the even parity check mistake, and high four positions of status register two are worth accordingly; Frame is checked and is since the 5th byte, until the arithmetic sum of 2 complement on n ns of third from the bottom byte, after field programmable gate array was received last byte 0x16, message received and finishes;
If heading is 0x10; Field programmable gate array judges through reading second byte whether this message issues this main website: if second byte is identical with the main website address value that micro-control unit sends in the master information register, just think that this message issues this main website; If the main website address value that second byte and micro-control unit send in the master information register is inequality, just think that this message do not issue this main website; Field programmable gate array judges whether to be the message of transmitting-receiving certainly through reading the 3rd byte: if the 3rd byte is identical with the main website address value, just think from the message of receiving and dispatching; If the 3rd byte and main website address value are inequality, just think the message that slave station is sent out; Field programmable gate array continues to read the 4th byte and the 5th byte then; Field programmable gate array is done even parity check to the 5th byte that receives and is judged; The even parity check judgment mode is: field programmable gate array with the check of the frame that calculates and with the message that receives in the 5th byte relatively; Judged whether check errors: if identical, just judge no even parity check mistake, with the Gao Siwei maintenance initial value of status register two; If different, just judging has the even parity check mistake, and high four positions of status register two are worth accordingly; Frame is checked and is since second byte, until the arithmetic sum of 2 complement on n ns of the 4th byte, after field programmable gate array was received the 6th byte, message received and finishes;
If heading is 0xDC; Field programmable gate array judges through reading second byte whether this message issues this main website; If second byte is identical with the main website address value that micro-control unit sends in the master information register, just think that this message issues this main website; If the main website address value that second byte and micro-control unit send in the master information register is inequality, just think that this message do not issue this main website; Field programmable gate array judges whether to be the message of transmitting-receiving certainly through reading the 3rd byte, if the 3rd byte is identical with the main website address value, just thinks from the message of receiving and dispatching; If the 3rd byte and main website address value are inequality, just think the message that slave station is sent out; After field programmable gate array was received the 3rd byte, message received and finishes;
If heading is 0xe5, then message receives and finishes,
After message received and finishes, field programmable gate array to input buffer module, sent interrupt request singal to micro-control unit with storage, and the reception stop bits with status register one is set to 1 simultaneously;
Step is 5.: after micro-control unit receives the interrupt request singal that field programmable gate array sends; Read the status register one of field programmable gate array, the value of status register two, judge to have or not message to receive, whether message is correct; And according to connecing the definite message that sends of field bus communication standard; Micro-control unit sends message information to field programmable gate array message information register then, if the message that sends has the data cell part, then micro-control unit sends the data cell part to the output buffer module of field programmable gate array simultaneously; Then, micro-control unit sends message to field programmable gate array and sends request signal;
Step is 6.: send request signal when field programmable gate array receives message, can read the transmission type of message in the inner message information of message information register;
If sending message is type one, field programmable gate array just reads the first seven byte of this message successively from the message information register, whenever read a byte; Just send a byte, when field programmable gate array reads the 5th byte, begin to calculate frame check with; When having sent the 7th byte; Field programmable gate array just sends data cell from output buffer module reading of data unit and through parallel serial conversion module, after data cell is sent and is finished, field programmable gate array stop to calculate the frame check with; Then transmit frame check with; The message-ending character of redispatching at last, frame check and be since the 5th byte is until the arithmetic sum of 2 complement on n ns of third from the bottom byte;
If sending message is type two, field programmable gate array just reads preceding nine bytes of this message successively from the message information register, whenever read a byte; Just send a byte, when field programmable gate array reads the 5th byte, begin to calculate frame check with; When having sent the 9th byte; Field programmable gate array just sends data cell from output buffer module reading of data unit and through parallel serial conversion module, after data cell is sent and is finished, field programmable gate array stop to calculate the frame check with; Then transmit frame check with; The message-ending character of redispatching at last, frame check and be since the 5th byte is until the arithmetic sum of 2 complement on n ns of third from the bottom byte;
If sending message is type three, field programmable gate array just reads preceding four bytes of this message successively from the message information register, whenever read a byte; Just send a byte, when field programmable gate array reads second byte, begin to calculate frame check with; When having sent the 4th byte; Field programmable gate array stops to calculate frame check and, the transmit frame check and, the message-ending character of redispatching at last then; Frame is checked and is since second byte, until the arithmetic sum of 2 complement on n ns of the 4th byte;
If sending message is type four, field programmable gate array just reads first three byte of this message successively from the message information register, whenever read a byte, just sends a byte;
If sending message is type five, field programmable gate array just directly sends 0xe5;
So far message sends and finishes, and field programmable gate array is set to 1 with the transmission stop bits in the status register one;
Step is 7.: micro-control unit is opened the current timer in the field programmable gate array, and field programmable gate array changes the reception message status over to by sending message status, returns step 4., waits for that message receives.
The present invention has following positive beneficial effect:
This method realizes transmission and the reception that bus data flows by on-site programmable gate array FPGA, alleviates the burden of micro-control unit MCU serial communication; By on-site programmable gate array FPGA identification PROFIBUS message data stream; And realize data between the PROFIBUS principal and subordinate string and with and the string conversion; On-site programmable gate array FPGA born and sent message, received message, whether complete to the message that receives, whether correctly analyze with verification and calculate; Therefore practice thrift bus time, improved bus communication speed; The present invention realizes the PROFIBUS master station communication through the on-site programmable gate array FPGA technology, can satisfy the specification requirement of international standard regulation fully.
Description of drawings
Fig. 1 is the hardware structure diagram of main website of the present invention.
Fig. 2 is through the software programming high-level schematic functional block diagram that forms of programmable gate array FPGA at the scene.
Fig. 3 is a workflow diagram of the present invention.
Embodiment
Please with reference to Fig. 1, in the present invention, main website hardware mainly comprises on-site programmable gate array FPGA chip and micro controller unit MCU, and wherein the main signal end of on-site programmable gate array FPGA chip use is:
TXD is sent in serial received RXD, serial, RTS, low address line ADD [7:0], high address line ADD [15:8], data wire DATA [7:0] and interrupt requests RE_OK are sent in request.
The main signal end that MCU uses is: read signal/RD, write signal/WR, address be low allow ALE,
Address date multiplexing line AD [7:0] and high address line A [15:8], initialization finish signal Init_ok with send request signal SEND_REQ.
The serial ports differential signal line A of IL485 chip, B are connected with slave station.
The design selects the on-site programmable gate array FPGA of the cyclone series of U.S. A Ertela Altera for use.Outside 485 networks send to on-site programmable gate array FPGA serial interface closing in RXD with signal through A and B line; On-site programmable gate array FPGA receives and converts serial data into parallel data; Reception finishes and sends interrupt request singal RE_OK to micro-control unit MCU; After micro-control unit MCU received this interrupt request singal RE_OK, the response interrupt requests was called corresponding interrupt requests program; Through/the RD reading of data, and whether decision sends transmission request signal SEND_REQ to on-site programmable gate array FPGA.
If micro-control unit MCU sends the transmission request signal to on-site programmable gate array FPGA; The packing data that on-site programmable gate array FPGA sends micro-control unit MCU also converts serial data into, sends signal TXD and RTS sends to external network with data through A and the B line of IL485 through serial ports.
The low address line ADD [7:0] that the address date multiplexing line AD [7:0] of micro-control unit MCU is connected to on-site programmable gate array FPGA through latch is as the address low; Low address line ADD [7:0] is connected to the data wire DATA [7:0] of on-site programmable gate array FPGA simultaneously; Under read signal/RD, write signal/WR control, as data-signal.
Please with reference to Fig. 2, in order to realize the communication between the PROFIBUS master-salve station, the present invention utilizes software that on-site programmable gate array FPGA is carried out the sub-module design, accomplishes each item function of interface, and internal module comprises:
Bus interface module: bus interface module is micro-control unit MCU and the mutual passage of on-site programmable gate array FPGA; Sequential requirement according to external random access memory (XRAM) expansion module of micro-control unit MCU; The EBI of design FPGA FPGA is to satisfy the implementing reading and writing of micro-control unit MCU to it.
Phase-locked loop module: the clock input frequency multiplication that is mainly used in the 48MHz of outside is 192MHz (working clock frequency that serial ports is the highest).
The serial clock generation module: this module is dynamically adjusted the frequency of serial ports sampling clock according to different baud rate settings, calibrates sampled point simultaneously.
Timer module: be used for the master station call duration time.
Also conversion of string (the serial input is handled) module: this module is to be used for realizing when FPGA receives data string and conversion, the end of judgment frame simultaneously (do not allow between the frame character of PROFIBUS-DP message at interval, have then think at interval frame end).
The serial received processing module: this module is according to the byte input after the conversion of serial input module and handles enable signal; Judge type of message, message length; Carry out frame check and FCS verification, open relevant timer, various reception false judgment, work at present state are judged; To receive data and write buffer memory, notice MCU.
Input buffer module: input-buffer is on-site programmable gate array FPGA storage inside (RAM) district, is used to deposit the data that receive.
The registers group module: it is inner that this module is integrated in on-site programmable gate array FPGA; Can be by the module of micro-control unit MCU read-write; Make on-site programmable gate array FPGA be in specific state thereby one side micro-control unit MCU can be provided with the on-site programmable gate array FPGA internal register, micro-control unit MCU can judge the operation of current needs according to the state of on-site programmable gate array FPGA internal register on the other hand.
The registers group module comprises: status register one, status register two, master information register, control register, message information register.
Output buffer module: output buffers also is the inner RAM district of on-site programmable gate array FPGA, is used for the temporary data that soon sent by on-site programmable gate array FPGA.
Send processing module: this module mainly comprises judges definition status and accepting state, according to type of message, message length and message information packing message, and carries out even parity check and calculates.
And string conversion (serial output) module: this module is mainly accomplished the also string conversion that will send data, exports to string line simultaneously by turn.
Please with reference to Fig. 3, the present invention is a kind of method based on FPGA technology realization PROFIBUS master station communication protocol, may further comprise the steps:
Step is 1.: on-site programmable gate array FPGA waits for that in the back initialization that powers on micro-control unit MCU sends master information,
Step is 2.: micro-control unit MCU sends master information to the master information register of on-site programmable gate array FPGA; Master information is made up of main website station address, baud rate, timer time value; The main website station address is the unique address that this main website communicates by letter on bus, and span is 0～126, in the present embodiment; The main website station address is 3
Baud rate be main website with from the traffic rate of point on bus, span is 9600～12Mbit/s, in the present embodiment, baud rate is 187.5Kbit/s,
The timer time value is to be used for the operating time that controlling bus is attend main website and slave station, in the present embodiment,
Timer time value=200tbit,
Step is 3.: micro-control unit MCU sends to on-site programmable gate array FPGA and is initialized to function signal Init_ok; Confirming that master information is sent finishes, receive be initialized to function signal Init_ok after, on-site programmable gate array FPGA starts bus message and monitors; The wait message receives
Step is 4.: micro-control unit MCU puts 1 with the control register of on-site programmable gate array FPGA; Thereby open the current timer in the on-site programmable gate array FPGA; On-site programmable gate array FPGA is being waited for bus data in the timer time scope of front opening, and bus data is the message that receives of main website self or the message of slave station response;
If on-site programmable gate array FPGA does not receive bus data in the timer time scope; Then then produce interrupt request singal RE_OK in the back at current timer; And interrupt request singal sent to micro-control unit MCU; Simultaneously, the reception end signal position RE_OV of the status register one of on-site programmable gate array FPGA remains on initial condition (value of initial condition is 0)
Eight positions are arranged in the status register one shown in form 1,
Zero-bit D0 is used for sign and receives end, and first D1 is used for the sign transmission and finishes second to the 7th reservation.
Form 1
Micro-control unit MCU is after receiving interrupt request singal RE_OK; Read the value of the reception end signal position RE_OV of on-site programmable gate array FPGA internal state register one; The value of this reception end signal position RE_OV is 0, and micro-control unit MCU judges that this interrupt signal is that overtime nothing receives interruption.
If field programmable gate array receives bus data in the timer time scope,
But heading is not one of 0x68,0x10,0xDC, 0xe5; Then then produce interrupt request singal in the back at current timer; And interrupt request singal RE_OK sent to micro-control unit; Simultaneously, the reception end signal position RE_OV of the status register one of field programmable gate array remains on initial condition
Micro-control unit MCU is after receiving interrupt request singal RE_OK; Read the value of the reception end signal position RE_OV of on-site programmable gate array FPGA internal state register one; The value of this reception end signal position is 0, and then micro-control unit MCU judges that this interrupt signal is that overtime nothing receives interruption
If on-site programmable gate array FPGA receives bus data in the timer time scope; And heading is one of 0x68,0x10,0xDC, 0xe5; Then on-site programmable gate array FPGA is after receiving complete frame data; Stop current timer timing, no longer because timer expiry sends interrupt request singal to micro-control unit MCU, simultaneously; The serial received processing module of on-site programmable gate array FPGA is judged the message kind according to the heading that receives, and resolves as follows respectively then:
If heading is 0x68, on-site programmable gate array FPGA just judges through second, third byte that reads message whether message has size error:
Heading is the message of 0x68, and its data structure can be shown in form 2:
Form 2
| 68 | x | X | 68 | DA | SA | FC | DSAP | SSAP | DU | FCS | 16 |
First byte is heading 0x68, and second, third byte is message length x, and the 4th byte is that message defines symbol 0x68; The 5th byte is destination address DA, and the 6th byte is source address SA, and the 7th byte is function code FC; The 8th byte is destination service access point DSAP; The 9th byte is source service access point SSAP, and the tenth byte to third from the bottom byte is data cell: the penult byte is frame check and FCS, and last byte is end mark 0x16.
Heading is the message of 0x68, and its data structure can also be shown in form 3:
Form 3
| 68 | x | X | 68 | DA | SA | FC | DU | FCS | 16 |
First byte is heading 0x68; Second, third byte is message length x, and the 4th byte is that message defines symbol 0x68, and the 5th byte is destination address DA; The 6th byte is source address SA; The 7th byte is function code FC, and the 8th byte to third from the bottom byte is data cell: the penult byte is frame check and FCS, and last byte is end mark 0x16.
For heading is two kinds of messages of 0x68, and on-site programmable gate array FPGA judges through second, third byte that reads message whether message has size error:
If second, third byte length equates that just thinking does not have size error, with the Gao Siwei maintenance initial value of status register two, initial value is 0.
If second, third byte length is unequal, just thinking has size error, high four positions of status register two are worth accordingly, and for example, be 2 with high four positions of status register two.
Eight positions are arranged in the status register two shown in form 4,
Form 4
Low four D0, D1, D2, D3 are used to indicate the timer state, and high four D4, D5, D6, D7 are used to indicate the message error type, for example:
The value of Gao Siwei is that 1 representative receives character even parity check mistake,
The value of Gao Siwei is that 2 representatives receive the message length mistake,
The value of Gao Siwei is 3 to represent the type of message mistake,
On-site programmable gate array FPGA has judged whether the type of message mistake through reading the 4th byte of message:
If the 4th byte is identical with heading, just there is not the type of message mistake, with the Gao Siwei maintenance initial value of status register two; Initial value is 0.
If the 4th byte and heading are inequality, the type of message mistake is just arranged, high four positions of status register two are worth accordingly, for example, be 3 with high four positions of status register two.On-site programmable gate array FPGA judges through reading the 5th byte (destination address DA) whether this message issues this main website:
If the 5th byte is identical with the main website address value that micro-control unit MCU sends in the master information register, just think that this message issues this main website;
If the main website address value that the 5th byte and micro-control unit MCU send in the master information register is inequality, just think that this message do not issue this main website;
On-site programmable gate array FPGA through read the 6th byte (source address SA) judge whether into certainly the transmitting-receiving message,
If the 6th byte is identical with the main website address value, just think message from transmitting-receiving,
If the 6th byte and main website address value are inequality, just think the message that slave station is sent out,
On-site programmable gate array FPGA continues to read all the other bytes of the 6th byte back according to message length then,
On-site programmable gate array FPGA is done even parity check to the penult byte that receives and is judged that the even parity check judgment mode is:
On-site programmable gate array FPGA with the check of the frame that calculates and with the message that receives in the penult byte relatively, judged whether check errors:
If identical, just judge no even parity check mistake, with the Gao Siwei maintenance initial value of status register two, initial value is 0,
If different, just judging has the even parity check mistake, and high four positions of status register two are worth accordingly, and this value is 1, and the frame check is since the 5th byte with FCS, up to the arithmetic sum of 2 complement on n ns of third from the bottom byte; For example:
Message length x=0x05
Destination address DA=0x03,
Source address SA=0x01,
Function code FC=0x7d,
Data cell DU has 2 bytes
First byte=0x12 of data cell DU
Second byte=0x34 of data cell DU
0x03+0x01+0x7d+0x12+0x34＝0xc7
Then frame is checked and FCS=0xc7
After on-site programmable gate array FPGA was received last byte 0x16, message received and finishes;
If heading is 0x10, on-site programmable gate array FPGA judges through reading second byte (destination address DA) whether this message issues this main website;
Heading be the data structure of 0x10 shown in form 5:
Form 5
| 10 | DA | SA | FC | FCS | 16 |
The implication of function code (FC) representative is shown in form 6
Form 6
| b5 | b4 | Note |
| 0 | 0 | Slave station |
| 0 | 1 | Do not prepare to get into the main website of logic token ring |
| 1 | 0 | Prepare to get into the main website of logic token ring |
| 1 | 1 | Main website in the logic token ring |
If second byte (destination address DA) is identical with the main website address value that micro-control unit MCU sends in the master information register, just think that this message issues this main website; If the main website address value that second byte (destination address DA) and micro-control unit MCU send in the master information register is inequality, just think that this message do not issue this main website;
On-site programmable gate array FPGA through read the 3rd byte (source address SA) judge whether into certainly the transmitting-receiving message,
If the 3rd byte (source address SA) is identical with the main website address value, just think message from transmitting-receiving;
If the 3rd byte (source address SA) is inequality with the main website address value, just think the message that slave station is sent out;
On-site programmable gate array FPGA continues to read the 4th byte (function code) and the 5th byte (frame check with) then, on-site programmable gate array FPGA to the 5th byte receiving (frame check with) do even parity check and judge that the even parity check judgment mode is:
On-site programmable gate array FPGA has judged whether check errors with the 5th byte comparison in the frame check that calculates and FCS and the message that receives:
If identical, just judge no even parity check mistake, with the Gao Siwei maintenance initial value of status register two; Initial value is 0,
If different, just judging has the even parity check mistake, and high four positions of status register two are worth accordingly; This value is 1, and frame check and FCS are since second byte, until the arithmetic sum of 2 complement on n ns of the 4th byte,
After on-site programmable gate array FPGA was received the 6th byte, message received and finishes,
If heading is 0xDC, its data structure shown in form 7,
Form 7
| DC | DA | SA |
If heading is 0xDC, on-site programmable gate array FPGA judges through reading second byte (destination address DA) whether this message issues this main website:
If second byte is identical with the main website address value that micro-control unit MCU sends in the master information register, just think that this message issues this main website,
If the main website address value that second byte and micro-control unit MCU send in the master information register is inequality, just think that this message do not issue this main website,
On-site programmable gate array FPGA through read the 3rd byte (source address SA) judge whether into certainly the transmitting-receiving message,
If the 3rd byte is identical with the main website address value, just think message from transmitting-receiving;
If the 3rd byte and main website address value are inequality, just think the message that slave station is sent out;
After on-site programmable gate array FPGA was received the 3rd byte source address SA, message received and finishes;
If heading is 0xe5, then receive and finish, heading be its data structure of 0xe5 shown in form 8,
Form 8
| E5 |
On-site programmable gate array FPGA all arrives input buffer module with storage after message receives end, MCU sends interrupt request singal to micro-control unit, and the reception stop bits with status register one is set to 1 simultaneously;
Step is 5.: after micro-control unit MCU receives the interrupt request singal RE_OK that on-site programmable gate array FPGA sends; Read the status register one of on-site programmable gate array FPGA, the value of status register two; Judge to have or not message to receive, whether message is correct, and confirms to send message according to the field bus communication standard; Micro-control unit MCU sends message information to on-site programmable gate array FPGA message information register then; If the message that sends has the data cell part, then micro-control unit MCU sends the data cell part to the output buffer module of on-site programmable gate array FPGA simultaneously, then; Micro-control unit MCU sends message to on-site programmable gate array FPGA and sends request signal SEND_REQ
Step is 6.: sends request signal SEND_REQ when on-site programmable gate array FPGA receives message, can read the transmission type of message in the inner message information of message information register,
If sending message is type one; On-site programmable gate array FPGA just reads the first seven byte of this message successively from the message information register, these seven bytes are represented respectively: heading 0x68, message length x, message length x, message define symbol 0x68, destination address DA, source address SA, function code FC, whenever read a byte, just send a byte; When on-site programmable gate array FPGA reads the 5th byte (destination address DA); Begin to calculate frame check and FCS, when having sent the 7th byte, on-site programmable gate array FPGA just sends data cell from output buffer module reading of data unit and through parallel serial conversion module; After data cell is sent and is finished; On-site programmable gate array FPGA stops to calculate frame check and FCS, and transmit frame is checked and FCS then, and message-ending character 0x16 at last redispatches; Frame check and FCS are since the 5th byte, until the arithmetic sum of 2 complement on n ns of third from the bottom byte;
The data structure of this message shown in form 9,
Form 9
| 68 | x | X | 68 | DA | SA | FC | DU | FCS | 16 |
If sending message is type two; On-site programmable gate array FPGA just reads preceding nine bytes of this message successively from the message information register; These nine bytes are represented respectively: heading 0x68, message length x, message length x, message define symbol 0x68, destination address DA, source address SA, function code FC, destination service access point DSAP, source service access point SSAP, whenever read a byte, just send a byte; When on-site programmable gate array FPGA reads the 5th byte; Begin to calculate frame check and FCS, when having sent the 9th byte, on-site programmable gate array FPGA just sends data cell from output buffer module reading of data unit and through parallel serial conversion module; After data cell is sent and is finished; On-site programmable gate array FPGA stops to calculate frame check and FCS, and transmit frame is checked and FCS then, and message-ending character 0x16 at last redispatches; Frame check and FCS are since the 5th byte, until the arithmetic sum of 2 complement on n ns of third from the bottom byte;
The data structure of this message shown in form 10,
Form 10
| 68 | x | X | 68 | DA | SA | FC | DSAP | SSAP | DU | FCS | 16 |
If sending message is type three,
On-site programmable gate array FPGA just reads preceding four bytes of this message successively from the message information register, these four bytes are represented respectively: heading 0x10, destination address DA, source address SA, function code FC, whenever read a byte, just send a byte; When on-site programmable gate array FPGA reads second byte; Begin to calculate frame check and FCS, when having sent the 4th byte, on-site programmable gate array FPGA stops to calculate frame check and FCS; Transmit frame is checked and FCS then; The message-ending character 0x16 that redispatches at last, the frame check is since second byte with FCS, up to the arithmetic sum of 2 complement on n ns of the 4th byte;
The data structure of this message shown in form 11,
Form 11
| 10 | DA | SA | FC | FCS | 16 |
If sending message is type four,
On-site programmable gate array FPGA just reads first three byte of this message successively from the message information register, these three bytes are represented respectively: heading 0xDC, destination address DA, source address SA, whenever read a byte, and just send a byte,
The data structure of this message shown in form 12,
Form 12
| DC | DA | SA |
If sending message is type five,
On-site programmable gate array FPGA just directly sends 0xe5,
The data structure of this message shown in form 13,
Form 13
| E5 |
So far message sends and finishes, and on-site programmable gate array FPGA is set to 1 with the transmission stop bits TR_OV in the status register one,
Step is 7.: micro-control unit MCU opens the current timer in the on-site programmable gate array FPGA, and on-site programmable gate array FPGA changes the reception message status over to by sending message status, returns step 4., waits for that message receives.
Claims (1)
1. the present invention is a kind of method based on FPGA technology realization PROFIBUS master station communication protocol, and it is characterized in that: this method may further comprise the steps:
Step is 1.: field programmable gate array waits for that in the back initialization that powers on micro-control unit sends master information;
Step is 2.: micro-control unit sends master information to the master information register of field programmable gate array, and master information is made up of main website station address, baud rate, timer time value;
Step is 3.: micro-control unit sends to field programmable gate array and is initialized to function signal, confirm that master information is sent to finish, receive be initialized to function signal after, field programmable gate array starts bus message to be monitored, and waits for that message receives;
Step is 4.: micro-control unit is opened the current timer in the field programmable gate array; Field programmable gate array is being waited for bus data in the timer time scope of front opening, and bus data is the message that receives of main website self or the message of slave station response;
If field programmable gate array does not receive bus data in the timer time scope; Then then produce interrupt request singal in the back at current timer; And interrupt request singal sent to micro-control unit; Simultaneously, the reception end signal position of the status register one of field programmable gate array remains on initial condition; Micro-control unit reads the value of the reception end signal position of field programmable gate array internal state register one after receiving interrupt request singal, the value of this reception end signal position is 0, and then micro-control unit judges that this interrupt signal is that overtime nothing receives interruption;
If field programmable gate array receives bus data in the timer time scope; But heading is not one of 0x68,0x10,0xDC, 0xe5; Then then produce interrupt request singal in the back at current timer; And interrupt request singal sent to micro-control unit, simultaneously, the reception end signal position of the status register one of field programmable gate array remains on initial condition; Micro-control unit reads the value of the reception end signal position of field programmable gate array internal state register one after receiving interrupt request singal, the value of this reception end signal position is 0, and then micro-control unit judges that this interrupt signal is that overtime nothing receives interruption;
If field programmable gate array receives bus data in the timer time scope; And heading is one of 0x68,0x10,0xDC, 0xe5, and then field programmable gate array stops current timer timing after receiving complete frame data; No longer because timer expiry sends interrupt request singal to micro-control unit; Simultaneously, the serial received processing module of field programmable gate array is judged the message kind according to the heading that receives, and resolves as follows respectively then:
If heading is 0x68; Field programmable gate array just judges through second, third byte that reads message whether message has size error: if second, third byte length equates; Just thinking does not have size error, with the Gao Siwei maintenance initial value of status register two; If second, third byte length is unequal, just thinking has size error, and high four value of status register two is changed to 2; Field programmable gate array has judged whether the type of message mistake through reading the 4th byte of message; If the 4th byte is identical with heading, just there is not the type of message mistake, with the Gao Siwei maintenance initial value of status register two; If the 4th byte and heading are inequality, the type of message mistake is just arranged, high four value of status register two is changed to 3; Field programmable gate array judges through reading the 5th byte whether this message issues this main website; If the 5th byte is identical with the main website address value that micro-control unit sends in the master information register; Just think that this message issues this main website; If the main website address value that the 5th byte and micro-control unit send in the master information register is inequality, just think that this message do not issue this main website; Field programmable gate array judges whether to be the message of transmitting-receiving certainly through reading the 6th byte, if the 6th byte is identical with the main website address value, just thinks from the message of receiving and dispatching; If the 6th byte and main website address value are inequality, just think the message that slave station is sent out; Field programmable gate array continues to read all the other bytes of the 6th byte back according to message length then; Field programmable gate array is done even parity check to the penult byte that receives and is judged; The even parity check judgment mode is: field programmable gate array with the check of the frame that calculates with the message that receives in the penult byte relatively judged whether check errors: if identical; Just judge no even parity check mistake, with the Gao Siwei maintenance initial value of status register two, if different; Just judging has the even parity check mistake, and high four value of status register two is changed to 1; Frame is checked and is since the 5th byte, until the arithmetic sum of 2 complement on n ns of third from the bottom byte, after field programmable gate array was received last byte 0x16, message received and finishes;
If heading is 0x10; Field programmable gate array judges through reading second byte whether this message issues this main website: if second byte is identical with the main website address value that micro-control unit sends in the master information register, just think that this message issues this main website; If the main website address value that second byte and micro-control unit send in the master information register is inequality, just think that this message do not issue this main website; Field programmable gate array judges whether to be the message of transmitting-receiving certainly through reading the 3rd byte: if the 3rd byte is identical with the main website address value, just think from the message of receiving and dispatching; If the 3rd byte and main website address value are inequality, just think the message that slave station is sent out; Field programmable gate array continues to read the 4th byte and the 5th byte then; Field programmable gate array is done even parity check to the 5th byte that receives and is judged; The even parity check judgment mode is: field programmable gate array with the check of the frame that calculates and with the message that receives in the 5th byte relatively; Judged whether check errors: if identical, just judge no even parity check mistake, with the Gao Siwei maintenance initial value of status register two; If different, just judging has the even parity check mistake, and high four value of status register two is changed to 1; Frame is checked and is since second byte, until the arithmetic sum of 2 complement on n ns of the 4th byte, after field programmable gate array was received the 6th byte, message received and finishes;
If heading is 0xDC; Field programmable gate array judges through reading second byte whether this message issues this main website; If second byte is identical with the main website address value that micro-control unit sends in the master information register, just think that this message issues this main website; If the main website address value that second byte and micro-control unit send in the master information register is inequality, just think that this message do not issue this main website; Field programmable gate array judges whether to be the message of transmitting-receiving certainly through reading the 3rd byte, if the 3rd byte is identical with the main website address value, just thinks from the message of receiving and dispatching; If the 3rd byte and main website address value are inequality, just think the message that slave station is sent out; After field programmable gate array was received the 3rd byte, message received and finishes;
If heading is 0xe5, then message receives and finishes,
After message received and finishes, field programmable gate array to input buffer module, sent interrupt request singal to micro-control unit with storage, and the reception stop bits with status register one is set to 1 simultaneously;
Step is 5.: after micro-control unit receives the interrupt request singal that field programmable gate array sends; Read the status register one of field programmable gate array, the value of status register two, judge to have or not message to receive, whether message is correct; And according to connecing the definite message that sends of field bus communication standard; Micro-control unit sends message information to field programmable gate array message information register then, if the message that sends has the data cell part, then micro-control unit sends the data cell part to the output buffer module of field programmable gate array simultaneously; Then, micro-control unit sends message to field programmable gate array and sends request signal;
Step is 6.: send request signal when field programmable gate array receives message, can read the transmission type of message in the inner message information of message information register;
If sending message is type one, field programmable gate array just reads the first seven byte of this message successively from the message information register, whenever read a byte; Just send a byte, when field programmable gate array reads the 5th byte, begin to calculate frame check with; When having sent the 7th byte; Field programmable gate array just sends data cell from output buffer module reading of data unit and through parallel serial conversion module, after data cell is sent and is finished, field programmable gate array stop to calculate the frame check with; Then transmit frame check with; Frame is checked and is since the 5th byte, until the arithmetic sum of 2 complement on n ns of third from the bottom byte, the message-ending character of redispatching at last;
If sending message is type two, field programmable gate array just reads preceding nine bytes of this message successively from the message information register, whenever read a byte; Just send a byte, when field programmable gate array reads the 5th byte, begin to calculate frame check with; When having sent the 9th byte; Field programmable gate array just sends data cell from output buffer module reading of data unit and through parallel serial conversion module, after data cell is sent and is finished, field programmable gate array stop to calculate the frame check with; Then transmit frame check with; Frame is checked and is since the 5th byte, until the arithmetic sum of 2 complement on n ns of third from the bottom byte, the message-ending character of redispatching at last;
If sending message is type three, field programmable gate array just reads preceding four bytes of this message successively from the message information register, whenever read a byte; Just send a byte, when field programmable gate array reads second byte, begin to calculate frame check with; When having sent the 4th byte; Field programmable gate array stop to calculate frame check with, the transmit frame check is with, frame check be since second byte then; Until the arithmetic sum of 2 complement on n ns of the 4th byte, the message-ending character of redispatching at last;
If sending message is type four, field programmable gate array just reads first three byte of this message successively from the message information register, whenever read a byte, just sends a byte;
If sending message is type five, field programmable gate array just directly sends 0xe5;
So far message sends and finishes, and field programmable gate array is set to 1 with the transmission stop bits in the status register one;
Step is 7.: micro-control unit is opened the current timer in the field programmable gate array, and field programmable gate array changes the reception message status over to by sending message status, returns step 4., waits for that message receives.
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| CN110519138B (en) * | 2019-08-12 | 2021-12-07 | 北京和利时系统工程有限公司 | Profibus-DP master station protocol implementation method and system |
| CN110687854B (en) * | 2019-11-05 | 2021-07-30 | 杭州和利时自动化有限公司 | PA bus controller and PA bus control system |
| CN111123760A (en) * | 2019-11-22 | 2020-05-08 | 北京讯风光通信技术开发有限责任公司 | Communication bus method for realizing master-slave automatic control by utilizing determined time sequence |
| CN112637248B (en) * | 2021-03-09 | 2021-05-18 | 厚普清洁能源股份有限公司 | Ship-end and shore-end equipment communication processing method for LNG filling wharf boat |
| CN113890785B (en) * | 2021-11-03 | 2022-12-27 | 西安热工研究院有限公司 | Communication system and method for field bus hybrid networking |
| CN114726674B (en) * | 2022-04-06 | 2023-12-29 | 北京鼎实创新科技股份有限公司 | PROFIBUS bus process data extraction method based on FPGA |
| CN116974233B (en) * | 2023-09-19 | 2024-01-19 | 西安热工研究院有限公司 | Dual-channel Profibus-DP master station system and design method |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101374115A (en) * | 2008-09-28 | 2009-02-25 | 北京鼎实创新科技有限公司 | Rapid discriminating multiport control method based on PROFIBUS packet |
| CN201274492Y (en) * | 2008-09-28 | 2009-07-15 | 北京鼎实创新科技有限公司 | PROFIBUS hub with relay function |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2002218000A (en) * | 2001-01-23 | 2002-08-02 | Mitsubishi Electric Corp | Data communication device and data communication method |
-
2010
- 2010-05-07 CN CN 201010165868 patent/CN101841542B/en active Active
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101374115A (en) * | 2008-09-28 | 2009-02-25 | 北京鼎实创新科技有限公司 | Rapid discriminating multiport control method based on PROFIBUS packet |
| CN201274492Y (en) * | 2008-09-28 | 2009-07-15 | 北京鼎实创新科技有限公司 | PROFIBUS hub with relay function |
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