CN104660462A - Packing system and method for 10-gigabit Ethernet test equipment - Google Patents
Packing system and method for 10-gigabit Ethernet test equipment Download PDFInfo
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Abstract
The invention discloses a packing system and method for 10-gigabit Ethernet test equipment. The system comprises an interface module, a dispatch module of at least one channel, a stream generating module and a channel mixing module, wherein the interface module is used for enabling FPGA to be in communication with CPU through a PCI bus; the dispatch module of the at least one channel comprises a dispatch control information storage unit, a stream number storage unit, a packet length storage unit which is used for configuring transmit speed of the CPU and generating dispatch pulses according to the transmit speed, wherein one message is generated, transmitted and output when one dispatch pulse is generated each time; the stream generating module is used for receiving data output by the dispatch module of the at least one channel and generating a data stream of the at least one channel which conforms to the Ethernet protocol; the channel mixing module is used for combining the data stream comprising the at least one channel. The packing system and method have the advantages that test traffic can be generated, transmitted and received at a line speed of 10 Gbps, the measurement of test statistics, generation of routing messages and message intercept can be completed, the randomness and instantaneity of data packages can be obviously improved.
Description
Technical field
The invention belongs to communication test field, relate to a kind of group packet system and method for ten thousand mbit ethernet testing equipments.
Background technology
Ten thousand mbit ethernets use IEEE 802.3 ethernet medium access-control protocol (MAC), IEEE802.3 ethernet frame format and IEEE802.3 is minimum and maximum frame size.Ten thousand mbit ethernets only operate in full duplex mode, and do not run half work mode, and will not re-use Carrier Sense Multiple Access/collision detection (CSMA/CD) mechanism.
At present, test packet production process for the group bag of ten thousand mbit ethernet testing equipments is application CPU, by software, the packet organized is write in memory, then by software read data packet from memory, due to the restriction by traffic rate between software and memory, test packet lacks randomness and real-time.
Summary of the invention
The object of the invention is to overcome above-mentioned deficiency, a kind of group bag method of ten thousand mbit ethernet testing equipments is provided, which increases significantly randomness and the real-time of packet.
To achieve these goals, the technical solution used in the present invention is: a kind of group packet system of ten thousand mbit ethernet testing equipments, is characterized in that, comprising:
Interface module, is communicated with CPU by pci bus for making FPGA;
The scheduler module of at least one passage, it comprises scheduling control information memory, stream number memory, bag long memory, for configuring CPU transmission rate, and according to transmission rate, produce scheduling pulse, often produce a scheduling pulse, then generate and send a message, then export;
Stream generation module, the data that the scheduler module for receiving at least one passage described exports, produce the data flow meeting Ethernet protocol of at least one passage;
Passage mixing module, for merging the described data flow comprising at least one passage.
Another object of the present invention is to a kind of group bag method that ten thousand mbit ethernet testing equipments are provided, it is characterized in that, comprising:
Interface module, makes FPGA be communicated with CPU by pci bus;
The scheduler module of at least one passage, it comprises scheduling control information memory, stream number memory, bag long memory, configuration CPU transmission rate, and according to transmission rate, produce scheduling pulse, often produce a scheduling pulse, then generate and send a message, then export;
Stream generation module, the data that the scheduler module receiving at least one passage described exports, produce the data flow meeting Ethernet protocol of at least one passage;
Passage mixing module, merges the described data flow comprising at least one passage.
Beneficial effect of the present invention is:
The first, structure is simple, comprises interface module; The scheduler module of at least one passage; Stream generation module, passage mixing module, multiple passage is adopted to package, overcome prior art to use CPU to produce message to have that to occupy cpu resource many, CPU process interrupt and time shared by process long, and the defect such as the low and performance of the efficiency of CPU deal with data is low, the generation of hardware implementing test packet can be used, significantly increase randomness and the real-time of packet.
Second, be widely used, scheduling control information memory adopts digital direct general formula fifo stores schedule information, in generation scheduling pulse process, obtain the stream number in stream number memory, long according to the bag that stream number reads in bag long memory, when producing scheduling pulse, stream number and bag progress row are stored, package when fifo state non-NULL, and by stream number current for fifo, bag progress line output, the type of real-time aligned data bag, can generate with 10Gbps linear speed, send and receive test traffic, complete the measurement of test statistics, the generation of route message and message intercept.
Accompanying drawing explanation
Accompanying drawing described herein is used to provide further understanding of the present application, and form a application's part, the schematic description and description of the application, for explaining the application, does not form the improper restriction to the application.In the accompanying drawings:
Fig. 1 is the example structure schematic diagram of the group packet system of ten thousand mbit ethernet testing equipments of the present invention;
Fig. 2 is another example structure schematic diagram of the group packet system of ten thousand mbit ethernet testing equipments of the present invention;
Fig. 3 is the application schematic diagram of the group packet system of ten thousand mbit ethernet testing equipments of the present invention;
Fig. 4 is the group bag method flow diagram of ten thousand mbit ethernet testing equipments of the present invention.
Embodiment
As employed some vocabulary to censure specific components in the middle of specification and claim.Those skilled in the art should understand, and hardware manufacturer may call same assembly with different noun.This specification and claims are not used as with the difference of title the mode distinguishing assembly, but are used as the criterion of differentiation with assembly difference functionally." comprising " as mentioned in the middle of specification and claim is in the whole text an open language, therefore should be construed to " comprise but be not limited to "." roughly " refer to that in receivable error range, those skilled in the art can solve the technical problem within the scope of certain error, reach described technique effect substantially.Specification subsequent descriptions is implement the better embodiment of the application, and right described description is for the purpose of the rule that the application is described, and is not used to the scope limiting the application.The protection range of the application is when being as the criterion depending on the claims person of defining.
Embodiment 1
Please refer to Fig. 1, the group packet system of ten thousand mbit ethernet testing equipments of the present invention comprises: interface module, is communicated with CPU by pci bus for making FPGA; The scheduler module of at least one passage, it comprises scheduling control information memory, stream number memory, bag long memory, for configuring CPU transmission rate, and according to transmission rate, produce scheduling pulse, often produce a scheduling pulse, then generate and send a message, then export; Stream generation module, the data that the scheduler module for receiving at least one passage described exports, produce the data flow meeting Ethernet protocol of at least one passage; Passage mixing module, for merging the described data flow comprising at least one passage.
Preferably, also comprise the interface module sending to mac, for the data flow that fetch channel mixing module merges, and send to mac according to transmission rate and the sequential meeting mac.
Preferably, described stream generation module comprises: configuration and statistical module, generates configuration data, and upgrade the statistics of this stream for the message corresponding from this stream number; The group bag module of at least one passage, it comprises data storage and control information memory, for being latched by the configuration data generated from described configuration and statistical module, according to set of configuration data bag, calculate the School Affairs of proprietary protocol, the School Affairs of IP bag, and the School Affairs of TCP/UDP bag, described School Affairs is added in the data after group bag, to generate the packet organized, deposit in described data storage by described group of complete packet, bag lives forever in described control information memory.
Preferably, described scheduling control information memory adopts digital direct general formula fifo stores schedule information, in generation scheduling pulse process, obtain the stream number in stream number memory, long according to the bag that stream number reads in bag long memory, when producing scheduling pulse, stream number and bag progress row are stored, package when fifo state non-NULL, and by stream number current for fifo, bag progress line output.
Preferably, described number of active lanes is 2.
As specific embodiment, comprising: passage 0 scheduler module, passage 1 scheduler module.
Preferably, each channel scheduling module comprises scheduling control information memory, stream number memory, bag long memory.
As specific embodiment, comprising: passage 0 group of bag module, passage 1 group of bag module.
Preferably, each passage group bag module comprises data storage and control information memory.
Preferably, the reference clock of each passage is 165.25Mhz, and the data bit width of process is 64bit.
Preferably, fpga chip mainly comprises: input-output unit able to programme, basic programmable logic cells, Clock Managing Unit, embedded block formula RAM, routing cell, embedded bottom functional unit and embedded application specific hardware modules.
Preferably, FPGA utilizes small-sized look-up table (16 × 1RAM) to realize combinational logic, each look-up table is connected to the input of a d type flip flop, trigger drives other logical circuits again or drives I/O, thus constitute and can realize the basic logic unit module that combination logic function can realize again sequential logic function, these intermodules utilize metal connecting line to be connected to each other or are connected to I/O module.
Preferably, the logic of FPGA loads programming data by internally static storage cell and realizes, store value in a memory cell and determine connected mode between the logic function of logical block and individual module or between module and I/O, and the connecting mode finally determined between the logic function of logical block and each module or between module and I/O, and the function finally determined achieved by FPGA, FPGA allows unlimited programming.
Preferably, described input-output unit able to programme is the interface section with external circuitry, for complete under different electrical characteristic to the driving of input/output signal with mate requirement, by the flexible configuration of software, can adaptive different electrical standard and I/O physical characteristic, the size of drive current can be adjusted.
Preferably, external input signal can be input to the inside of FPGA by input-output unit able to programme, also can directly input FPGA inside.
Preferably, basic programmable logic cells comprises a configurable switch matrix, and this matrix is made up of 4 or 6 inputs, some type selecting circuit (multiplexer etc.) and trigger.
Preferably, switch matrix is high flexible, can be configured so that treatment combination logic, shift register or RAM to it.
Preferably, each basic programmable logic cells not only may be used for realizing combinational logic, sequential logic, can also be configured to distributed RAM and distributed ROM.
Preferably, basic programmable logic cells is made up of two 4 functions inputted, carry logic, arithmetical logic, stored logic sum functions multiplexers.
Preferably, arithmetical logic comprises an XOR gate and one and door, and an XOR gate can realize the full add operation of 2bit, and carry logic is made up of carry signal sum functions multiplexer, for realizing arithmetic addition and subtraction operation fast; 4 input function generators are used for realizing 4 input LUT, distributed RAM or 16 bit shift register.
Preferably, described carry logic comprises two the Fast Carry Logics, for improving the processing speed of basic programmable logic cells.
Preferably, Clock Managing Unit is used for digital dock management and phase loop locking.Phase loop locking can provide accurate clock comprehensive, and can reduce shake, and realizes filtering function.
Preferably, embedded block formula RAM can be configured to the storage organizations such as single port RAM, two-port RAM, contents address memory and FIFO.
Preferably, have a Compare Logic in contents address memory each memory cell therein, the data in write CAM can compare with each inner data, and return to the address of all data identical with port data.
Preferably, routing cell is communicated with all unit of FPGA inside, is divided into the different classification of 4 classes according to the difference of technique, length, width and distributing position.The first kind is global routing's module, for the wiring of chip internal global clock and Global reset/set; Equations of The Second Kind is long wire module, in order to complete the wiring of high speed signal between chip Bank and the second global clock signal; 3rd class is short-term module, for completing logic interconnection between basic logic unit and wiring; 4th class is distributed interconnect module, for control signal wires such as proprietary clock, resets.
Preferably, embedded bottom functional unit comprises: DLL (Delay Locked Loop), PLL (Phase Locked Loop), DSP.For completing clock high accuracy, the frequency multiplication of low jitter and frequency division, and the function such as duty ratio adjustment and phase shift.
Preferably, the configuration mode that the present embodiment adopts, for FPGA is connected CPU, is programmed to FPGA by CPU.
Preferably, a slice FPGA also can be adopted to add the configuration mode of a slice EPROM.
Preferably, the configuration mode of a slice PROM programming multiple FPGA can also be adopted.
Preferably, the configuration mode of serial PROM programming FPGA can also be adopted.
Embodiment 2
Please refer to Fig. 2, the group packet system of the ten thousand mbit ethernet testing equipments of the present embodiment comprises: interface module, is communicated with CPU by pci bus for making FPGA; The scheduler module of at least one passage, it comprises scheduling control information memory, stream number memory, bag long memory, for configuring CPU transmission rate, and according to transmission rate, produce scheduling pulse, often produce a scheduling pulse, then generate and send a message, then export; Stream generation module, the data that the scheduler module for receiving at least one passage described exports, produce the data flow meeting Ethernet protocol of at least one passage; Passage mixing module, for merging the described data flow comprising at least one passage.
Preferably, also comprise the interface module sending to mac, for the data flow that fetch channel mixing module merges, and send to mac according to transmission rate and the sequential meeting mac.
Preferably, at the described input also connection data filtering module sending to the interface module of mac.
Preferably, described data filtering module comprises data storage and control information memory, and wherein, data storage, for the packet after stored filter; Control information memory, for storing bag long message, the coordinate of timestamp, the coordinate of proprietary protocol School Affairs, the coordinate of TCP/UDP School Affairs, the School Affairs of proprietary protocol, the TCP/UDP School Affairs of the packet after described filtration.
Preferably, described stream generation module comprises: configuration and statistical module, generates configuration data, and upgrade the statistics of this stream for the message corresponding from this stream number; The group bag module of at least one passage, it comprises data storage and control information memory, for being latched by the configuration data generated from described configuration and statistical module, according to set of configuration data bag, calculate the School Affairs of proprietary protocol, the School Affairs of IP bag, and the School Affairs of TCP/UDP bag, described School Affairs is added in the data after group bag, to generate the packet organized, deposit in described data storage by described group of complete packet, bag lives forever in described control information memory.
Preferably, described scheduling control information memory adopts digital direct general formula fifo stores schedule information, in generation scheduling pulse process, obtain the stream number in stream number memory, long according to the bag that stream number reads in bag long memory, when producing scheduling pulse, stream number and bag progress row are stored, package when fifo state non-NULL, and by stream number current for fifo, bag progress line output.
Preferably, described number of active lanes is 2.
As specific embodiment, comprising: passage 0 scheduler module, passage 1 scheduler module.
Preferably, each channel scheduling module comprises scheduling control information memory, stream number memory, bag long memory.
As specific embodiment, comprising: passage 0 group of bag module, passage 1 group of bag module.
Preferably, each passage group bag module comprises data storage and control information memory.
Preferably, the reference clock of each passage is 165.25Mhz, and the data bit width of process is 64bit.
Please refer to Fig. 3, the present embodiment is applied to ten thousand mbit ethernet test modules, ten thousand mbit ethernet interfaces are realized, the generation of transmitting portion logic realization ten thousand mbit ethernet data and sending function, receiving unit logic realization ten thousand mbit ethernet data receiver and analytic function based on FPGA
,fPGA integrated ten thousand mbit ethernet MAC and XAUI Core, XAUI core are mainly used in the physical layer protocol realizing Ethernet protocol transfer of data; MAC is mainly used in the data link layer protocol realizing Ethernet protocol transfer of data; CPU, by the pci interface module of FPGA, is configured FPGA, reads message analysis result.CPU uses I2C bus, for reading and writing FPGA external 10G optical module internal register.MGT Fast Ethernet transceiver, realizes the serioparallel exchange of data; Ten thousand mbit ethernet PHY chip realize the interface conversion between XAUI interface and ten thousand mbit ethernet optical modules (SFP).Optical module is used for opto-electronic conversion, and transmitting terminal converts light signal to the signal of telecommunication, and after being transmitted by optical fiber, receiving terminal converts the signal of telecommunication to light signal again.
Embodiment 3
The present embodiment provides a kind of group bag method of ten thousand mbit ethernet testing equipments, comprising: interface module, FPGA is communicated with CPU by pci bus; The scheduler module of at least one passage, it comprises scheduling control information memory, stream number memory, bag long memory, configuration CPU transmission rate, and according to transmission rate, produce scheduling pulse, often produce a scheduling pulse, then generate and send a message, then export; Stream generation module, the data that the scheduler module receiving at least one passage described exports, produce the data flow meeting Ethernet protocol of at least one passage; Passage mixing module, merges the described data flow comprising at least one passage.
Preferably, also comprise the data flow that fetch channel mixing module merges, and send to mac according to transmission rate and the sequential meeting mac.
Preferably, described scheduling control information memory adopts digital direct general formula fifo stores schedule information, in generation scheduling pulse process, obtain the stream number in stream number memory, long according to the bag that stream number reads in bag long memory, when producing scheduling pulse, stream number and bag progress row are stored, package when fifo state non-NULL, and by stream number current for fifo, bag progress line output.
Preferably, meet header information required in the packet structure of the data flow of Ethernet protocol, such as: source MAC, target MAC (Media Access Control) address, source IP address, object IP address.
Preferably, the frame format of Ethernet is: frame head+padding data+postamble, MAC destination address, uses hexadecimal representation usually.Destination address is used to the direction of transfer and the route that judge ethernet frame between devices.Each ethernet device is assigned with a unique MAC Address usually.
And some special MAC Address is retained, for representing some special functions, such as, the address (FF:FF:FF:FF:FF:FF) of complete 1 is for representing broadcast address.
Preferably, source address: 6 bytes, refers to the MAC Address of transmit leg.Usually hexadecimal representation is used.Source address is generally when producing, by production firm's write device, and first three byte representation vendor code of MAC Address, rear three byte representation equipment serial number.It should be noted that for some equipment, such as testing equipment, its MAC Address can be arranged at any time.
Preferably, length/type field: 2 bytes, this field is for the upper layer data protocol type of the length or encapsulation that represent frame.If this field is less than 05DC (HEX), then represent length, if be greater than 0600 (HEX), then represent the protocol type of data field.Such as: 0800HEX represents it is IP agreement.
Preferably, data field: 46 to 1500 bytes, is the application data needing transmission in data field, usually comprises upper layer protocol data, as IP data etc.
Preferably, FCS Frame Check Sequence: 4 bytes, transmit leg, by calculating each byte in frame, obtains Frame Check Sequence, and is inserted into the last transmission of frame.Recipient, in receiving course, can recalculate verification sequence, and with received frame in last 4 byte verification sequence compare.Wrong for Frame Check Sequence, or the ethernet frame lost, it can abandon by most equipment.
| Destination address | Source address | Length/type | Padding data territory | FCS |
Preferably, host-host protocol is TCP and UDP, is below the frame format of TCP bag:
| Destination address | Source address | Type | IP stem | TCP stem | Padding data | FCS |
IP stem structure:
Transmission Control Protocol stem structure:
UDP stem structure
| Source port (16) | Destination interface (16) | Length field (16) | School Affairs (16) |
Preferably, IP header checksum: only inspection IP data packet header, stem in units of 16, carries out complement of one's summation successively.
Preferably, tcp data bag School Affairs meets algorithm: TCP pseudo-stem+TCP stem+data; Wherein the pseudo-stem of TCP is: 32 source IP addresss, 32 object IP addresses, 8 bit protocols, 16 TCP length.
Preferably, UDP message bag School Affairs meets algorithm: UDP pseudo-stem+UDP stem+data; Wherein the pseudo-stem of UDP is: 32 source IP addresss, 32 object IP addresses, 8 bit protocols, 16 UDP length.
Beneficial effect of the present invention is:
The first, structure is simple, comprises interface module; The scheduler module of at least one passage; Stream generation module, passage mixing module, multiple passage is adopted to package, overcome prior art to use CPU to produce message to have that to occupy cpu resource many, CPU process interrupt and time shared by process long, and the defect such as the low and performance of the efficiency of CPU deal with data is low, the generation of hardware implementing test packet can be used, significantly increase randomness and the real-time of packet.
Second, be widely used, scheduling control information memory adopts digital direct general formula fifo stores schedule information, in generation scheduling pulse process, obtain the stream number in stream number memory, long according to the bag that stream number reads in bag long memory, when producing scheduling pulse, stream number and bag progress row are stored, when fifo state is for packaging time empty, when fifo state non-NULL, by the stream number of current for fifo output, bag progress line output, the type of real-time aligned data bag, can generate with 10Gbps linear speed, send and receive test traffic, complete the measurement of test statistics, the generation of route message and message intercept.
Above-mentioned explanation illustrate and describes some preferred embodiments of the application, but as previously mentioned, be to be understood that the application is not limited to the form disclosed by this paper, should not regard the eliminating to other embodiments as, and can be used for other combinations various, amendment and environment, and can in application contemplated scope described herein, changed by the technology of above-mentioned instruction or association area or knowledge.And the change that those skilled in the art carry out and change do not depart from the spirit and scope of the application, then all should in the protection range of the application's claims.
Claims (10)
1. a group packet system for ten thousand mbit ethernet testing equipments, is characterized in that, comprising:
Interface module, is communicated with CPU by pci bus for making FPGA;
The scheduler module of at least one passage, it comprises scheduling control information memory, stream number memory, bag long memory, for configuring CPU transmission rate, and according to transmission rate, produce scheduling pulse, often produce a scheduling pulse, then generate and send a message, then export;
Stream generation module, the data that the scheduler module for receiving at least one passage described exports, produce the data flow meeting Ethernet protocol of at least one passage;
Passage mixing module, for merging the described data flow comprising at least one passage.
2. the group packet system of ten thousand mbit ethernet testing equipments according to claim 1, it is characterized in that, also comprise the interface module sending to mac, for the data flow that fetch channel mixing module merges, and send to mac according to transmission rate and the sequential meeting mac.
3. the group packet system of ten thousand mbit ethernet testing equipments according to claim 1 and 2, is characterized in that, described stream generation module comprises:
Configuration and statistical module, generate configuration data for the message corresponding from this stream number, and upgrade the statistics of this stream;
The group bag module of at least one passage, it comprises data storage and control information memory, for being latched by the configuration data generated from described configuration and statistical module, according to set of configuration data bag, calculate the School Affairs of proprietary protocol, the School Affairs of IP bag, and the School Affairs of TCP/UDP bag, described School Affairs is added in the data after group bag, to generate the packet organized, deposit in described data storage by described group of complete packet, bag lives forever in described control information memory.
4. the group packet system of ten thousand mbit ethernet testing equipments according to claim 1, it is characterized in that, described scheduling control information memory adopts digital direct general formula fifo stores schedule information, in generation scheduling pulse process, obtains the stream number in stream number memory, long according to the bag that stream number reads in bag long memory, when producing scheduling pulse, stream number and bag progress row being stored, packages when fifo state non-NULL, and by stream number current for fifo, bag progress line output.
5. the group packet system of ten thousand mbit ethernet testing equipments according to claim 4, is characterized in that, at the described input also connection data filtering module sending to the interface module of mac.
6. the group packet system of ten thousand mbit ethernet testing equipments according to claim 1, is characterized in that, described number of active lanes is 2.
7. the group packet system of ten thousand mbit ethernet testing equipments according to claim 6, is characterized in that, the reference clock of each passage is 165.25Mhz, and the data bit width of process is 64bit.
8. a group bag method for ten thousand mbit ethernet testing equipments, is characterized in that, comprising:
Interface module, makes FPGA be communicated with CPU by pci bus;
The scheduler module of at least one passage, it comprises scheduling control information memory, stream number memory, bag long memory, configuration CPU transmission rate, and according to transmission rate, produce scheduling pulse, often produce a scheduling pulse, then generate and send a message, then export;
Stream generation module, the data that the scheduler module receiving at least one passage described exports, produce the data flow meeting Ethernet protocol of at least one passage;
Passage mixing module, merges the described data flow comprising at least one passage.
9. the group bag method of ten thousand mbit ethernets according to claim 8, is characterized in that, also comprises the step of the data flow that fetch channel mixing module merges, and sends to mac according to transmission rate and the sequential meeting mac.
10. the group bag method of ten thousand mbit ethernets according to claim 9, it is characterized in that, described scheduling control information memory adopts digital direct general formula fifo stores schedule information, in generation scheduling pulse process, obtains the stream number in stream number memory, long according to the bag that stream number reads in bag long memory, when producing scheduling pulse, stream number and bag progress row being stored, packages when fifo state non-NULL, and by stream number current for fifo, bag progress line output.
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| CN107786471A (en) * | 2017-10-23 | 2018-03-09 | 深圳市风云实业有限公司 | Data processing method and conversion equipment between more fpga chips |
| CN107786471B (en) * | 2017-10-23 | 2021-03-16 | 深圳市风云实业有限公司 | Data processing method and conversion device between multiple FPGA chips |
| CN111224773A (en) * | 2018-11-26 | 2020-06-02 | 山东量子科学技术研究院有限公司 | Quantum key management equipment |
| CN111224773B (en) * | 2018-11-26 | 2022-07-26 | 山东量子科学技术研究院有限公司 | Quantum key management equipment |
| CN111314242A (en) * | 2020-01-20 | 2020-06-19 | 烽火通信科技股份有限公司 | Multi-channel supported packet cache scheduling simulation verification method and system |
| CN111314242B (en) * | 2020-01-20 | 2022-05-13 | 烽火通信科技股份有限公司 | Multi-channel supporting packet cache scheduling simulation verification method and system |
| CN116707639A (en) * | 2023-07-10 | 2023-09-05 | 江苏信而泰智能装备有限公司 | 400G Ethernet flow testing device based on FPGA |
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