CN104702464B - The generation system of 100G ethernet test messages based on FPGA - Google Patents
The generation system of 100G ethernet test messages based on FPGA Download PDFInfo
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- CN104702464B CN104702464B CN201510020595.1A CN201510020595A CN104702464B CN 104702464 B CN104702464 B CN 104702464B CN 201510020595 A CN201510020595 A CN 201510020595A CN 104702464 B CN104702464 B CN 104702464B
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Abstract
This application discloses a kind of generation system and method for the 100G ethernet test messages based on FPGA, including：Interface module, for FPGA to be made to communicate by pci bus with CPU；Scheduler module for configuring CPU transmission rates, and according to transmission rate, generates scheduling pulse, often generates a scheduling pulse, then generate and send a message；Configuration and statistical module for reading stream number, bag length and frame period, then generate configuration data；Group bag and correction verification module for the configuration data received from the configuration and statistical module module to be latched, will be verified and be added in data packet；Passage mixes and mac adaptation modules, for data packet to be merged.It is an advantage of the invention that：It can be generated with 100Gbps linear speeds, send test flow, complete measurement, the generation for routeing message and the message intercept of test statistics, significantly increase the randomness and real-time of data packet.
Description
Technical field
The invention belongs to communication test fields, are related to a kind of generation system of the 100G ethernet test messages based on FPGA
And method.
Background technology
100G ethernet technologys are grown up on the basis of the rates ethernet technology such as 10/100Mb/s and 1/l0Gb/s
, using maximum defined in Ether frame specification defined in IEEE802.3 specifications and current 802.3 specifications of IEEE, most
Small frame is identical, and maximum media access control (MAC) frame length is 1518bytes, and minimum MAC is 64bytes, is mainly used at a high speed
The performance test of network interconnection device.
The generation process of prior art 100G ethernet test messages is：It generates to be sent out in advance according to ethernet format
Then the test packet sent is write into external memory or internal storage, generate scheduling signals and number is read from memory
According to bag, due to being limited by traffic rate, test packet lacks randomness and real-time.Exist in addition, generating message using CPU
Occupy that cpu resource is more, CPU processing is interrupted and the process occupied time is long and the efficiency of CPU processing data is low low with performance
The defects of.
The content of the invention
The purpose of the present invention is to overcome the above shortcomings and to provide a kind of lifes of the 100G ethernet test messages based on FPGA
Into system, which increases significantly the randomnesss and real-time of data packet.
To achieve these goals, the technical solution adopted by the present invention is：A kind of 100G ethernet tests based on FPGA
The generation system of message, which is characterized in that including：Interface module, for FPGA to be made to communicate by pci bus with CPU；At least
The scheduler module of one passage, including scheduling control information memory, stream number memory, bag long memory, for configuring CPU
Transmission rate, and according to transmission rate, generate scheduling pulse, often generate a scheduling pulse, then generate and send a message；
When dispatch pulse it is effective when, the stream number that is taken out from current stream number memory, according to stream number from bag long memory read data packet
Length, by stream number, bag is long and frame period write-in scheduling control information memory in；The configuration of at least one passage and statistics mould
Block for reading the stream number, bag length and frame period, then from the corresponding message generation configuration data of the stream number, and is updated and is somebody's turn to do
The statistics of stream；The group bag and correction verification module of at least one passage including data storage and control information memory, are used
In that will latch from the configuration data of the configuration and statistical module generation, according to set of configuration data bag, proprietary protocol is calculated
Verification and, the verification of IP bags and and TCP/UDP bags verification and, by the data for verifying and being added to group after wrapping,
With the complete data packet of generation group, described group of complete data packet is deposited into the data storage, bag is long and frame period deposits into institute
It states in control information memory；Passage mixes and mac adaptation modules, for data packet that will have been organized in the data storage into
Row merges.
Another object of the present invention is to provide a kind of generation system of the 100G ethernet test messages based on FPGA,
It is characterized in that, including：Interface module, for FPGA to be made to communicate by pci bus with CPU；The scheduling mould of at least one passage
Block, including scheduling control information memory, stream number memory, bag long memory, for configuring CPU transmission rates, and according to
Transmission rate, generates scheduling pulse, often generates a scheduling pulse, then generates and sends a message；When scheduling pulse is effective
When, the stream number that is taken out from current stream number memory, according to stream number from the length of bag long memory read data packet, by stream number,
Bag is long and frame period is write in scheduling control information memory；The configuration of at least one passage and statistical module, for reading
Stream number, bag length and frame period are stated, then from the corresponding message generation configuration data of the stream number, and updates the statistics of the stream；
The group bag and correction verification module of at least one passage, including data storage and control information memory, for that will match somebody with somebody from described
It puts and is latched with the configuration data of statistical module generation, according to set of configuration data bag, calculate the verification of proprietary protocol and IP bags
Verification and and TCP/UDP bags verification and, it is complete with generation group by the verification and the data being added to group after wrapping
Data packet deposits into described group of complete data packet in the data storage, and bag is long and frame period deposits into the control information and deposits
In reservoir；Loopback module for CPU to be made to set loopback mode, including receiving side looping back data memory, is set according to CPU
Loopback mode, receive message from receiving side looping back data memory, and after carrying out the exchanging of source/destination location, recalculate
The verification of the proprietary protocol and, the verification of IP bags and, the verification of TCP/UDP bags with, to generate looping back data bag, by the ring
It returns data packet and is saved in sending side looping back data memory；Passage mixes and mac adaptation modules, for directly reading the transmission
Side ring returns the message in data storage, and sends.
Another object of the present invention is to provide a kind of generation method of the 100G ethernet test messages based on FPGA,
It is characterized in that, including：Interface module makes FPGA communicate by pci bus with CPU；The scheduler module of at least one passage,
Including scheduling control information memory, stream number memory, bag long memory configures CPU transmission rates, and according to transmission rate,
Scheduling pulse is generated, a scheduling pulse is often generated, then generates and sends a message；When dispatch pulse it is effective when, from current
The stream number taken out in stream number memory, according to stream number from the length of bag long memory read data packet, by stream number, bag length and interframe
Every writing in scheduling control information memory；The configuration of at least one passage and statistical module read the stream number, bag length and frame
Interval then from the corresponding message generation configuration data of the stream number, and updates the statistics of the stream；The group of at least one passage
Bag and correction verification module including data storage and control information memory, are matched somebody with somebody what is generated from the configuration and statistical module
Data latch is put, according to set of configuration data bag, calculates the verification of proprietary protocol and the verification of IP bags and and TCP/UDP
The verification of bag and, by the verification and be added to group in the data after bag, with the complete data packet of generation group, by described group of complete number
It is deposited into according to bag in the data storage, bag is long and frame period is deposited into the control information memory；Passage mixes and mac is fitted
With module, the data packet organized in the data storage is merged.
A further purpose of the present invention is to provide a kind of generation method of the 100G ethernet test messages based on FPGA,
It is characterized in that, including：Interface module makes FPGA communicate by pci bus with CPU；The scheduler module of at least one passage,
Including scheduling control information memory, stream number memory, bag long memory configures CPU transmission rates, and according to transmission rate,
Scheduling pulse is generated, a scheduling pulse is often generated, then generates and sends a message；When dispatch pulse it is effective when, from current
The stream number taken out in stream number memory, according to stream number from the length of bag long memory read data packet, by stream number, bag length and interframe
Every writing in scheduling control information memory；The configuration of at least one passage and statistical module read the stream number, bag length and frame
Interval then from the corresponding message generation configuration data of the stream number, and updates the statistics of the stream；The group of at least one passage
Bag and correction verification module including data storage and control information memory, are matched somebody with somebody what is generated from the configuration and statistical module
Data latch is put, according to set of configuration data bag, calculates the verification of proprietary protocol and the verification of IP bags and and TCP/UDP
The verification of bag and, by the verification and be added to group in the data after bag, with the complete data packet of generation group, by described group of complete number
It is deposited into according to bag in the data storage, bag is long and frame period is deposited into the control information memory；Loopback module, makes CPU
Loopback mode is set, including receiving side looping back data memory, according to the loopback mode that CPU is set, from receiving side loopback number
Receive message according to memory, and after carrying out the exchanging of source/destination location, recalculate the proprietary protocol verification and, IP bags
Verification and, the verification of TCP/UDP bags with, to generate looping back data bag, the looping back data bag is saved in sending side loopback
Data storage；Passage mixes and mac adaptation modules, directly reads the message in the sending side looping back data memory, and
It sends.
Beneficial effects of the present invention are：
First, it is simple in structure, including interface module；The scheduler module of at least one passage；The configuration of at least one passage
And statistical module；The group bag and correction verification module of at least one passage, passage mixing and mac adaptation modules, using multiple passages into
Row group bag, the prior art is overcome to be generated using CPU, and message is more in the presence of cpu resource is occupied, and CPU processing is interrupted and process is occupied
Time is long and the low defects such as low with performance of the efficiency of CPU processing data, can using the generation of hardware realization test packet,
Significantly increase the randomness and real-time of data packet.
Second, it is widely used, loopback module makes CPU set loopback mode, including receiving side looping back data memory, root
According to the loopback mode that CPU is set, message is received from receiving side looping back data memory, and after carrying out the exchanging of source/destination location,
Recalculate proprietary protocol verification and, the verification of IP bags and, the verification of TCP/UDP bags with, to generate looping back data bag, general
Looping back data bag is saved in sending side looping back data memory.The type of real-time aligned data bag can be given birth to 100Gbps linear speeds
Into, send test flow, complete test statistics measurement, route message generation and message intercept.
Description of the drawings
Attached drawing described herein is used for providing further understanding of the present application, forms the part of the application, this Shen
Schematic description and description please does not form the improper restriction to the application for explaining the application.In the accompanying drawings：
Fig. 1 is the example structure signal of the generation system of the 100G ethernet test messages based on FPGA of the present invention
Figure；
Fig. 2 is that another example structure of the generation system of the 100G ethernet test messages based on FPGA of the present invention is shown
It is intended to；
Fig. 3 is the embodiment flow chart of the generation method of the 100G ethernet test messages based on FPGA of the present invention；
Fig. 4 is another embodiment flow of the generation method of the 100G ethernet test messages based on FPGA of the present invention
Figure.
Specific embodiment
Some vocabulary has such as been used to censure specific components among specification and claim.Those skilled in the art should
It is understood that hardware manufacturer may call same component with different nouns.This specification and claims are not with name
The difference of title is used as the mode for distinguishing component, but is used as the criterion of differentiation with the difference of component functionally.Such as logical
The "comprising" of piece specification and claim mentioned in is an open language, therefore should be construed to " include but do not limit
In "." substantially " refer in receivable error range, those skilled in the art can be described within a certain error range solution
Technical problem basically reaches the technique effect.Specification subsequent descriptions are so described to implement the better embodiment of the application
Description is for the purpose of the rule for illustrating the application, is not limited to scope of the present application.The protection domain of the application
When subject to appended claims institute defender.
Embodiment 1
Fig. 1 is refer to, the generation system of the 100G ethernet test messages of the invention based on FPGA includes：Interface mould
Block, for FPGA to be made to communicate by pci bus with CPU；The scheduler module of at least one passage, is deposited including scheduling control information
Reservoir, stream number memory, bag long memory for configuring CPU transmission rates, and according to transmission rate, generate scheduling pulse, often
A scheduling pulse is generated, then generates and sends a message；When scheduling pulse is effective, taken out from current stream number memory
Stream number, according to stream number from the length of bag long memory read data packet, by stream number, bag is long and frame period write-in scheduling controlling letter
It ceases in memory；The configuration of at least one passage and statistical module, for reading the stream number, bag length and frame period, Ran Houcong
The corresponding message generation configuration data of the stream number, and update the statistics of the stream；The group bag and calibration mode of at least one passage
Block, including data storage and control information memory, for the configuration data that will be generated from the configuration and statistical module
Latch is got up, according to set of configuration data bag, calculate proprietary protocol verification and, the verification of IP bags with and TCP/UDP bags school
Test and, by the verification and be added to group in the data after bag, with the complete data packet of generation group, described group of complete data packet deposited
Into in the data storage, bag is long and frame period is deposited into the control information memory；Passage mixes and mac is adapted to mould
Block, for the data packet organized in the data storage to be merged.
Preferably, high speed Ethernet interface module is further included, is mixed with the passage and mac adaptation modules is connected
It connects.
Preferably, the high speed Ethernet interface module includes：40G/100G Physical Coding Sublayers module and MAC module.
Preferably, the number of active lanes is 5.
As specific embodiment, including：0 scheduler module of passage, 1 scheduler module of passage, 2 scheduler module of passage, passage
3 scheduler modules, 4 scheduler module of passage.
Preferably, each channel scheduling module includes scheduling control information memory, stream number memory, bag long memory.
As specific embodiment, including：Passage 0 configures and statistical module, and passage 1 configures and statistical module, and passage 2 is matched somebody with somebody
It puts and statistical module, passage 3 configures and statistical module, and passage 4 configures and statistical module.
As specific embodiment, including：0 group of bag module of passage, 1 group of bag module of passage, 2 groups of bag modules of passage, passage
3 groups of bag modules, 4 groups of bag modules of passage.
Preferably, each passage group bag module includes data storage and control information memory.
As specific embodiment, described 0 group of bag module of passage, 1 group of bag module of passage, 2 groups of bag modules of passage, passage 3
Group bag module, 4 groups of bag module interface channel mixing of passage and mac adaptation modules, the passage mixing are connected with mac adaptation modules
High speed Ethernet interface module.
Preferably, the reference clock of each passage is 195.3125Mhz, and the data bit width of processing is 512bit.
Preferably, fpga chip mainly includes：Programmable input-output unit, basic programmable logic cells, clock pipe
Manage unit, embedded block formula RAM, routing cell, embedded bottom functional unit and embedded application specific hardware modules.
Preferably, FPGA realize combination logic using small-sized look-up table (16 × 1RAM), and each look-up table is connected to one
The input terminal of a d type flip flop, trigger drive other logic circuits or driving I/O, thus constitute and combination can be realized again
Logic function can realize the basic logic unit module of sequential logic function again, these intermodules are interconnected using metal connecting line
Or it is connected to I/O modules.
Preferably, the logic of FPGA loads programming data to realize by internally static storage cell, is stored in
Value in memory cell determine logic unit logic function and a module between or the connection side between module and I/O
Formula, and finally determine logic unit logic function and each module between or the connecting mode between module and I/O, it is and final
Determine the function achieved by FPGA, FPGA allows unlimited number of programming.
Preferably, the programmable input-output unit is the interface section with external circuitry, different electrical for completing
The driving of input/output signal with matching is required under characteristic, by the flexible configuration of software, different electrical standards can be adapted to
With I/O physical characteristics, the size of driving current can be adjusted.
Preferably, external input signal can be input to the inside of FPGA by may be programmed input-output unit, can also
It directly inputs inside FPGA.
Preferably, basic programmable logic cells include a configurable switch matrix, this matrix by 4 or 6 input,
Some type selecting circuits (multiplexer etc.) and trigger composition.
Preferably, switch matrix is high flexible, and processing combinational logic, shift LD can be configured to it
Device or RAM.
Preferably, each basic programmable logic cells can be not only used for realizeing combination logic, sequential logic, can be with
It is configured to distributed RAM and distribution ROM.
Preferably, basic programmable logic cells are by the function of two 4 inputs, carry logic, arithmetical logic, storage logic
It is formed with function multiplexer.
Preferably, arithmetical logic includes an XOR gate and one and door, and an XOR gate can realize that 2bit adds behaviour entirely
Make, carry logic is made of carry signal and function multiplexer, is used to implement quick arithmetic addition and subtraction operation；4 input functions
Generator is used to implement 4 input LUT, distribution RAM or 16 bit shift registers.
Preferably, the carry logic includes two the Fast Carry Logics, for improving the place of basic programmable logic cells
Manage speed.
Preferably, Clock Managing Unit locks for digital dock management and phase loop.Phase loop locking can carry
It is integrated for accurate clock, and shake can be reduced, and realize filtering function.
Preferably, embedded block formula RAM can be configured as single port RAM, two-port RAM, contents address memory and
The storage organizations such as FIFO.
Preferably, in each storage unit of contents address memory inside it CAM is write there are one CL Compare Logic
In data can and each internal data be compared, and return to the address of all data identical with port data.
Preferably, all units inside routing cell connection FPGA, according to technique, length, width and distributing position
It is different and be divided into the different classification of 4 classes.The first kind is global routing's module, is answered for chip internal global clock and the overall situation
The wiring of position/set；Second class is long wire module, to complete the high speed signal and the second global clock signal between chip Bank
Wiring；Three classes are short-term modules, for completing the logic interconnection between basic logic unit and wiring；4th class is distribution
The interconnection module of formula, for control signal wires such as proprietary clock, resets.
Preferably, embedded bottom functional unit includes：DLL (Delay Locked Loop), PLL (Phase
Locked Loop), DSP.For completing clock high-precision, the frequency multiplication of low jitter and frequency dividing and duty cycle adjustment and phase shift etc.
Function.
Preferably, the configuration mode that the present embodiment uses programs FPGA for FPGA is connected CPU, by CPU.
Preferably, the configuration mode that a piece of FPGA adds a piece of EPROM also can be used.
Preferably, the configuration mode of a piece of PROM programmings multiple FPGA also can be used.
Preferably, the configuration mode of serial PROM programmings FPGA also can be used.
Embodiment 2
It refer to Fig. 2, the generation system of the 100G ethernet test messages based on FPGA of the present embodiment, including：Interface
Module, for FPGA to be made to communicate by pci bus with CPU；The scheduler module of at least one passage, including scheduling control information
Memory, stream number memory, bag long memory, for configuring CPU transmission rates, and according to transmission rate, pulse is dispatched in generation,
A scheduling pulse is often generated, then generates and sends a message；When scheduling pulse is effective, taken from current stream number memory
The stream number gone out, according to stream number from the length of bag long memory read data packet, by stream number, bag is long and frame period writes scheduling controlling
In information-storing device；The configuration of at least one passage and statistical module, for reading the stream number, bag length and frame period, then
From the corresponding message generation configuration data of the stream number, and update the statistics of the stream；The group bag of at least one passage and verification
Module, including data storage and control information memory, for the configuration number that will be generated from the configuration and statistical module
According to latching, according to set of configuration data bag, the verification of proprietary protocol and the verification of IP bags and and TCP/UDP bags are calculated
Verification and, by the verification and be added to group in the data after bag, with the complete data packet of generation group, by described group of complete data
Bag is deposited into the data storage, and bag is long and frame period is deposited into the control information memory；Loopback module, for making
CPU sets loopback mode, including receiving side looping back data memory, according to the loopback mode that CPU is set, from receiving side loopback
Data storage receives message, and after carrying out the exchanging of source/destination location, recalculate the proprietary protocol verification and, IP
The verification of bag and, the verification of TCP/UDP bags with, to generate looping back data bag, the looping back data bag is saved in transmission side ring
Return data storage；Passage mixes and mac adaptation modules, for directly reading the report in the sending side looping back data memory
Text, and send.
Preferably, high speed Ethernet interface module is further included, is mixed with the passage and mac adaptation modules is connected
It connects.
Preferably, the high speed Ethernet interface module includes：40G/100G Physical Coding Sublayers module and MAC module.
Preferably, the number of active lanes is 5.
As specific embodiment, including：0 scheduler module of passage, 1 scheduler module of passage, 2 scheduler module of passage, passage
3 scheduler modules, 4 scheduler module of passage.
Preferably, each channel scheduling module includes scheduling control information memory, stream number memory, bag long memory.
As specific embodiment, including：Passage 0 configures and statistical module, and passage 1 configures and statistical module, and passage 2 is matched somebody with somebody
It puts and statistical module, passage 3 configures and statistical module, and passage 4 configures and statistical module.
As specific embodiment, including：0 group of bag module of passage, 1 group of bag module of passage, 2 groups of bag modules of passage, passage
3 groups of bag modules, 4 groups of bag modules of passage.
Preferably, each passage group bag module includes data storage and control information memory.
As specific embodiment, described 0 group of bag module of passage, 1 group of bag module of passage, 2 groups of bag modules of passage, passage 3
Group bag module, 4 groups of bag module interface channel mixing of passage and mac adaptation modules, the passage mixing are connected with mac adaptation modules
High speed Ethernet interface module.
Preferably, the reference clock of each passage is 195.3125Mhz, and the data bit width of processing is 512bit.
Embodiment 3
It refer to Fig. 3, the generation method of the 100G ethernet test messages based on FPGA of the present embodiment, including：Interface
Module makes FPGA communicate by pci bus with CPU；The scheduler module of at least one passage is stored including scheduling control information
Device, stream number memory, bag long memory configure CPU transmission rates, and according to transmission rate, generate scheduling pulse, often generate
One scheduling pulse, then generate and send a message；When dispatch pulse it is effective when, the stream that is taken out from current stream number memory
Number, according to stream number from the length of bag long memory read data packet, by stream number, bag is long and frame period write-in scheduling control information is deposited
In reservoir；The configuration of at least one passage and statistical module read the stream number, bag length and frame period, then from the stream number pair
The message generation configuration data answered, and update the statistics of the stream；The group bag and correction verification module of at least one passage, including
Data storage and control information memory will latch from the configuration data of the configuration and statistical module generation, according to
Set of configuration data bag, calculate proprietary protocol verification and, the verification of IP bags and and TCP/UDP bags verification with, by the school
It tests and is added in the data after group bag, with the complete data packet of generation group, described group of complete data packet is deposited into the data and is deposited
In reservoir, bag is long and frame period is deposited into the control information memory；Passage mixes and mac adaptation modules, by the data
The data packet organized in memory merges.
Preferably, configuration data is header information needed for Ethernet pack arrangement, such as：Source MAC addresses, purpose MAC
Address, source IP address, purpose IP address.
Preferably, the frame format of Ethernet is：Frame head+filling data+postamble, MAC destination addresses usually use hexadecimal
It represents.Destination address is used for the direction of transfer and the routing that judge ethernet frame between devices.Each ethernet device leads to
Often it is allocated a unique MAC Address.
And some special MAC Address are retained, for representing some special functions, for example, complete 1 address (FF:
FF:FF:FF:FF:FF) it is used to represent broadcast address.
Preferably, source address：6 bytes refer to the MAC Address of sender.Usually use hexadecimal representation.Source address is general
Be in production, by production firm's write device, first three byte representation vendor code of MAC Address, rear three table of bytes
Show equipment serial number.It should be noted that for some equipment, such as test equipment, its MAC Address is to set at any time
's.
Preferably, length/type field：2 bytes, this field are used to represent the length of frame or the upper layer data association of encapsulation
Discuss type.If the field is less than 05DC (HEX), then it represents that length, if greater than 0600 (HEX), then it represents that the association of data field
Discuss type.Such as:0800HEX expressions are IP agreements.
Preferably, data field：46 to 1500 bytes are to need the application data transmitted in data field, generally comprise upper strata
Protocol data, such as IP data.
Preferably, FCS Frame Check Sequences：4 bytes, sender obtain frame check by calculating each byte in frame
Sequence, and it is inserted into the last transmission of frame.Recipient can recalculate verification sequence in receive process, and in receiving frame
Last 4 byte verification sequence compares.For the ethernet frame that Frame Check Sequence is wrong or loses, most equipment can be by it
It abandons.
| Destination address | Source address | Length/type | Fill data field | FCS |
Preferably, transport protocol is TCP and UDP, is the frame format of TCP bags below：
| Destination address | Source address | Type | IP stems | TCP stems | Fill data | FCS |
IP stem structures：
Transmission Control Protocol stem structure：
UDP stem structures
| Source port (16) | Destination interface (16) | Length field (16) | Verification and (16) |
Preferably, IP header checks and：IP data packet headers are only examined, stem in units of 16, carry out two successively
Complement on n-1 n is summed.
Preferably, TCP data bag verifies and meets algorithm：TCP puppet stem+TCP stems+data；Wherein TCP puppets stem
For：32 source IP address, 32 purpose IP address, 8 bit protocols, 16 TCP length.
Preferably, UDP message bag verifies and meets algorithm：UDP puppet stem+UDP stems+data；Wherein UDP puppets stem
For：32 source IP address, 32 purpose IP address, 8 bit protocols, 16 UDP length.
Preferably, the step of merging includes the bag length being successively read in the control information memory of each passage and frame
Interval, according to the signal of the Bao Changyu frame periods and each passage of value generation reading data packet.
Preferably, counted using counter, reach the data packet that each passage is read with generation during value when counting
Signal.
Preferably, the number of active lanes is 5.
As specific embodiment, including：0 scheduler module of passage, 1 scheduler module of passage, 2 scheduler module of passage, passage
3 scheduler modules, 4 scheduler module of passage.
Preferably, each channel scheduling module includes scheduling control information memory, stream number memory, bag long memory.
As specific embodiment, including：Passage 0 configures and statistical module, and passage 1 configures and statistical module, and passage 2 is matched somebody with somebody
It puts and statistical module, passage 3 configures and statistical module, and passage 4 configures and statistical module.
As specific embodiment, including：0 group of bag module of passage, 1 group of bag module of passage, 2 groups of bag modules of passage, passage
3 groups of bag modules, 4 groups of bag modules of passage.
Preferably, each passage group bag module includes data storage and control information memory.
As specific embodiment, described 0 group of bag module of passage, 1 group of bag module of passage, 2 groups of bag modules of passage, passage 3
Group bag module, 4 groups of bag module interface channel mixing of passage and mac adaptation modules, the passage mixing are connected with mac adaptation modules
High speed Ethernet interface module.
Preferably, the reference clock of each passage is 195.3125Mhz, and the data bit width of processing is 512bit.
Embodiment 4
It refer to Fig. 4, the generation method of the 100G ethernet test messages based on FPGA of the present embodiment, including：Interface
Module makes FPGA communicate by pci bus with CPU；The scheduler module of at least one passage is stored including scheduling control information
Device, stream number memory, bag long memory configure CPU transmission rates, and according to transmission rate, generate scheduling pulse, often generate
One scheduling pulse, then generate and send a message；When dispatch pulse it is effective when, the stream that is taken out from current stream number memory
Number, according to stream number from the length of bag long memory read data packet, by stream number, bag is long and frame period write-in scheduling control information is deposited
In reservoir；The configuration of at least one passage and statistical module read the stream number, bag length and frame period, then from the stream number pair
The message generation configuration data answered, and update the statistics of the stream；The group bag and correction verification module of at least one passage, including
Data storage and control information memory will latch from the configuration data of the configuration and statistical module generation, according to
Set of configuration data bag, calculate proprietary protocol verification and, the verification of IP bags and and TCP/UDP bags verification with, by the school
It tests and is added in the data after group bag, with the complete data packet of generation group, described group of complete data packet is deposited into the data and is deposited
In reservoir, bag is long and frame period is deposited into the control information memory；Loopback module makes CPU set loopback mode, including
According to the loopback mode that CPU is set, message is received from receiving side looping back data memory for receiving side looping back data memory, and
After carrying out the exchanging of source/destination address, recalculate the proprietary protocol verification and, the verification of IP bags is with TCP/UDP bags
It verifies and to generate looping back data bag, the looping back data bag is saved in sending side looping back data memory；Passage mix and
Mac adaptation modules directly read the message in the sending side looping back data memory, and send.
Preferably, the number of active lanes is 5.
As specific embodiment, including：0 scheduler module of passage, 1 scheduler module of passage, 2 scheduler module of passage, passage
3 scheduler modules, 4 scheduler module of passage.
Preferably, each channel scheduling module includes scheduling control information memory, stream number memory, bag long memory.
As specific embodiment, including：Passage 0 configures and statistical module, and passage 1 configures and statistical module, and passage 2 is matched somebody with somebody
It puts and statistical module, passage 3 configures and statistical module, and passage 4 configures and statistical module.
As specific embodiment, including：0 group of bag module of passage, 1 group of bag module of passage, 2 groups of bag modules of passage, passage
3 groups of bag modules, 4 groups of bag modules of passage.
Preferably, each passage group bag module includes data storage and control information memory.
As specific embodiment, described 0 group of bag module of passage, 1 group of bag module of passage, 2 groups of bag modules of passage, passage 3
Group bag module, 4 groups of bag module interface channel mixing of passage and mac adaptation modules, the passage mixing are connected with mac adaptation modules
High speed Ethernet interface module.
Preferably, the reference clock of each passage is 195.3125Mhz, and the data bit width of processing is 512bit.
Beneficial effects of the present invention are：
First, it is simple in structure, including interface module；The scheduler module of at least one passage；The configuration of at least one passage
And statistical module；The group bag and correction verification module of at least one passage, passage mixing and mac adaptation modules, using multiple passages into
Row group bag, the prior art is overcome to be generated using CPU, and message is more in the presence of cpu resource is occupied, and CPU processing is interrupted and process is occupied
Time is long and the low defects such as low with performance of the efficiency of CPU processing data, can using the generation of hardware realization test packet,
Significantly increase the randomness and real-time of data packet.
Second, it is widely used, loopback module makes CPU set loopback mode, including receiving side looping back data memory, root
According to the loopback mode that CPU is set, message is received from receiving side looping back data memory, and after carrying out the exchanging of source/destination location,
Recalculate proprietary protocol verification and, the verification of IP bags and, the verification of TCP/UDP bags with, to generate looping back data bag, general
Looping back data bag is saved in the type of sending side looping back data memory real-time aligned data bag, can be generated with 100Gbps linear speeds,
Test flow is sent and received, completes measurement, the generation for routeing message and the message intercept of test statistics.
Several preferred embodiments of the application have shown and described in above description, but as previously described, it should be understood that the application
Be not limited to form disclosed herein, be not to be taken as the exclusion to other embodiment, and available for various other combinations,
Modification and environment, and above-mentioned introduction or the technology or knowledge of association area can be passed through in application contemplated scope described herein
It is modified.And changes and modifications made by those skilled in the art do not depart from spirit and scope, then it all should be in this Shen
It please be in the protection domain of appended claims.
Claims (6)
1. a kind of generation system of the 100G ethernet test messages based on FPGA, which is characterized in that including：
Interface module, for FPGA to be made to communicate by pci bus with CPU；
The scheduler module of at least one passage, including scheduling control information memory, stream number memory, bag long memory is used
In configuration CPU transmission rates, and according to transmission rate, scheduling pulse is generated, a scheduling pulse is often generated, then generates and sends
One message；When scheduling pulse is effective, stream number is taken out from current stream number memory, is read according to stream number from bag long memory
The length of data packet, by stream number, bag is long and frame period is write in scheduling control information memory；
The configuration of at least one passage and statistical module, for reading the stream number, bag is grown and frame period, then current stream number pair
The message generation configuration data answered, and update the statistics currently flowed；
The group bag and correction verification module of at least one passage, including data storage and control information memory, for by described in
The configuration data of configuration and statistical module generation latches, according to set of configuration data bag, calculate proprietary protocol verification and, IP
The verification of bag and and TCP or UDP bags verification and, it is complete with generation group by the verification and the data being added to group after wrapping
Data packet, described group of complete data packet is deposited into the data storage, bag is long and frame period deposits into the control information
In memory；
Passage mixes and mac adaptation modules, for the data packet organized in the data storage to be merged.
2. a kind of generation system of the 100G ethernet test messages based on FPGA, which is characterized in that including：
Interface module, for FPGA to be made to communicate by pci bus with CPU；
The scheduler module of at least one passage, including scheduling control information memory, stream number memory, bag long memory is used
In configuration CPU transmission rates, and according to transmission rate, scheduling pulse is generated, a scheduling pulse is often generated, then generates and sends
One message；When scheduling pulse is effective, stream number is taken out from current stream number memory, is read according to stream number from bag long memory
The length of data packet, by stream number, bag is long and frame period is write in scheduling control information memory；
The configuration of at least one passage and statistical module, for reading the stream number, bag is grown and frame period, then current stream number pair
The message generation configuration data answered, and update the statistics currently flowed；
The group bag and correction verification module of at least one passage, including data storage and control information memory, for by described in
The configuration data of configuration and statistical module generation latches, according to set of configuration data bag, calculate proprietary protocol verification and, IP
The verification of bag and and TCP or UDP bags verification and, it is complete with generation group by the verification and the data being added to group after wrapping
Data packet, described group of complete data packet is deposited into the data storage, bag is long and frame period deposits into the control information
In memory；
Loopback module, for CPU to be made to set loopback mode, including receiving side looping back data memory, the ring set according to CPU
The pattern of returning receives message from receiving side looping back data memory, and after carrying out the exchanging of source/destination location, recalculates described
The verification of proprietary protocol and, the verification of IP bags and, the verification of TCP/UDP bags with, to generate looping back data bag, by the loopback number
Sending side looping back data memory is saved according to bag；
Passage mixes and mac adaptation modules, for directly reading the looping back data bag in the sending side looping back data memory,
And it sends.
3. the generation system of the 100G ethernet test messages according to claim 1 or 2 based on FPGA, feature exist
In further including high speed Ethernet interface module, mixed with the passage and mac adaptation modules are attached.
4. the generation system of the 100G ethernet test messages according to claim 3 based on FPGA, which is characterized in that institute
Stating high speed Ethernet interface module includes：40G/100G Physical Coding Sublayers module and MAC module.
5. the generation system of the 100G ethernet test messages according to claim 1 or 2 based on FPGA, feature exist
In the number of active lanes is 5.
6. the generation system of the 100G ethernet test messages according to claim 5 based on FPGA, which is characterized in that every
The reference clock of a passage is 195.3125Mhz, and the data bit width of processing is 512bit.
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| CN116866301A (en) * | 2018-12-27 | 2023-10-10 | 达发科技(苏州)有限公司 | Hardware auxiliary speed measuring system |
| CN110210053A (en) * | 2019-04-24 | 2019-09-06 | 天津大学 | A kind of Design of Communication Interface method of the real-time digital solver based on FPGA |
| CN110086669A (en) * | 2019-04-29 | 2019-08-02 | 华东师范大学 | A kind of network based on ZYNQ is given out a contract for a project machine |
| CN110290020B (en) * | 2019-06-17 | 2020-10-13 | 北京挚友科技有限公司 | High-precision flow percentage generation method and device for Ethernet tester |
| CN111478825B (en) * | 2020-04-10 | 2023-04-18 | 深圳市风云实业有限公司 | Extensible network traffic generation and analysis method and system |
| CN112134757B (en) * | 2020-09-21 | 2022-08-19 | 北京信而泰科技股份有限公司 | Message generation method and device |
| CN116707639A (en) * | 2023-07-10 | 2023-09-05 | 江苏信而泰智能装备有限公司 | 400G Ethernet flow testing device based on FPGA |
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