CN111314242B - Multi-channel supporting packet cache scheduling simulation verification method and system - Google Patents
Multi-channel supporting packet cache scheduling simulation verification method and system Download PDFInfo
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- CN111314242B CN111314242B CN202010065237.3A CN202010065237A CN111314242B CN 111314242 B CN111314242 B CN 111314242B CN 202010065237 A CN202010065237 A CN 202010065237A CN 111314242 B CN111314242 B CN 111314242B
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L47/00—Traffic control in data switching networks
- H04L47/50—Queue scheduling
- H04L47/62—Queue scheduling characterised by scheduling criteria
- H04L47/6215—Individual queue per QOS, rate or priority
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
- H04L1/0078—Avoidance of errors by organising the transmitted data in a format specifically designed to deal with errors, e.g. location
- H04L1/0083—Formatting with frames or packets; Protocol or part of protocol for error control
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L47/00—Traffic control in data switching networks
- H04L47/10—Flow control; Congestion control
- H04L47/24—Traffic characterised by specific attributes, e.g. priority or QoS
Abstract
The invention discloses a simulation verification method and a system for packet buffer scheduling supporting multiple channels, which relate to the technical field of communication.
Description
Technical Field
The invention relates to the technical field of communication, in particular to a method and a system for simulating and verifying packet cache scheduling supporting multiple channels.
Background
With the rapid development of mobile communication and internet communication, operators have eagerly expected to realize 5G business. At present, 5G related technical research enters a system demonstration stage, and 5G test points are developed in multiple cities of Beijing, Shanghai and the like in China. The demand for higher bandwidth and lower latency of 5G has led to an increase in the transmission bandwidth of the core network. The POTN equipment with strong transmission capability and node scheduling capability is a fusion solution for meeting the high-capacity transmission requirement of a mobile 5G application trunk network. The CPB (Central packet buffer) module is a core module of the POTN device, and mainly completes unified centralized storage and forwarding of data, mixed scheduling of ethernet and OTN data, and supports bidirectional super-large bandwidth scheduling capability.
The CPB module is a brand-new module with special functions, and therefore, a verification model and method that can be compatible with a plurality of ports, two modes, and two directions at the same time is required, but at present, there is no verification model and method that can satisfy the test of the CPB module.
Disclosure of Invention
Aiming at the defects in the prior art, the invention aims to provide a method and a system for simulating and verifying packet cache scheduling supporting multiple channels, which are compatible with the verification requirements of multiple ports and two directions of a CPB module and have good universality and flexibility.
In order to achieve the above purposes, the technical scheme adopted by the invention is as follows: a simulation verification method for supporting multi-channel packet cache scheduling comprises the following steps:
the branch separation direction is used for mapping the data frames generated by each sequence generator to a unified data channel from each service channel according to the selection of the test mode, and scheduling the data frames through an ILK scheduler, or directly mapping the data frames generated by each sequence generator to a scheduler corresponding to each service type for scheduling; sending the bus time sequence to a to-be-tested central packet cache module for simulation processing; receiving the data frame after the simulation processing from the central packet cache module to be tested according to the bus time sequence, performing demodulation degree processing, and sending the data frame to the comparator modules corresponding to the sequence generators for comparison processing;
in the branch line integration direction, the data frames generated by each sequence generator are scheduled and sent to a central packet cache module to be tested according to the bus time sequence for simulation processing; and receiving the data frame after the simulation processing from the central packet cache module to be tested according to the bus time sequence, performing demodulation degree processing, demapping the data frame to each service channel, and sending the data frame to the comparator module corresponding to each sequence generator for comparison processing.
On the basis of the technical scheme, the method for mapping the data frames generated by each sequence generator to the unified data channel by each service channel specifically comprises the following steps:
controlling the total number of the service channels working simultaneously not to exceed the total number of the unified data channels;
and mapping the data frames of all the service channels to the unified data channels according to the channel mapping table, wherein each service channel corresponds to one unified data channel.
On the basis of the technical scheme, the data frame is scheduled and processed, and the data frame comprises a data packet mode and a data segmentation mode:
in the data packet mode, rate depiction is carried out on a data frame according to a channel, and the data frame is driven to a bus interface of a central packet cache module to be tested according to a channel scheduling table;
and under the data segmentation mode, firstly, the data frame is cut into packets, the rate of the data frame after the packets are cut is described according to the channel, and the data frame after the packets are cut is driven to a bus interface of the central packet cache module to be tested according to the channel scheduling table.
On the basis of the technical scheme, the data frame is processed by the demodulation degree, and the demodulation degree comprises a data packet mode and a data segmentation mode:
under the data packet mode, restoring the data frame to each service channel according to the channel scheduling table;
and under the data segmentation mode, detecting the correctness of the received data slice, encapsulating the data frame, and restoring the data frame to each service channel according to the channel scheduling table.
On the basis of the technical scheme, the bus timing sequence comprises four modes: a single-segment and inter-channel difference mode, a multi-segment and inter-channel difference mode, a single-segment and whole-packet mode, and a multi-segment and whole-packet mode;
the difference mode between the single segment and the channel is as follows: only one segment is arranged on the bus, and the channels can be mutually inserted;
the multi-segment and channel difference mode: the bus is provided with a plurality of segments, and channels can be mutually inserted;
single segment and whole packet mode: only one segment is arranged on the bus, and the channels cannot be mutually inserted;
multi-segment and whole packet mode: the bus has a plurality of segments, and the channels cannot be mutually inserted.
On the basis of the technical scheme, the comparator module performs comparison processing, and specifically comprises the following steps: the comparator module compares the data frame processed by the central packet cache module to be tested with the original data frame, and judges whether the simulation processing of the central packet cache module to be tested is correct.
The invention also provides a simulation verification system for supporting multi-channel packet buffer scheduling, which comprises a plurality of sequence generation and transmission modules, a channel mapper, a scheduler, a receiver, a channel demapper and data comparators in one-to-one correspondence with the sequence generation modules, wherein:
the sequence generation and transmission module is used for: generating data frames required by simulation, wherein each sequence generation and transmission module corresponds to one service channel and transmits the data frames to a channel mapper or a scheduler through each service channel;
the channel mapper is used for: uniformly mapping the data frames of all the service channels to a system channel and then sending the data frames to a scheduler;
the scheduler is configured to: scheduling the received data frame according to a set scheduling mode, and sending the data frame to a to-be-detected central packet cache module;
the receiver is used for: receiving data processed by the central packet cache module to be tested, recovering and encapsulating the data into data frames, and sending the data frames to a channel demapper or a data comparator;
the channel demapper is used for: demapping the data frames sent by the channel demodulator to each service channel, and sending the data frames to a data comparator corresponding to each service channel;
the data comparator is to: comparing the data frame required by simulation generated by the sequence generation module with the data frame processed by the central packet cache module to be tested, and judging whether the simulation processing is correct or not;
the link controller is configured to: and controlling the existence of the paths among the modules and the number of the service channels according to the test mode.
On the basis of the above technical solution, the scheduler includes a packet mode and a data segmentation mode:
in the data packet mode, rate depiction is carried out on a data frame according to a channel, and the data frame is driven to a bus interface of a central packet cache module to be tested according to a channel scheduling table;
under the data segmentation mode, firstly, a data frame is cut into packets, the rate of the data frame after the packets are cut is described according to a channel, and the data frame after the packets are cut is driven to a bus interface of a central packet cache module to be tested according to a channel scheduling table;
the receiver includes a packet mode and a data segment mode:
under the data packet mode, restoring the data frame to each service channel according to the channel scheduling table;
under the data segmentation mode, firstly, the correctness of the received data slice is detected, the data frame is encapsulated, and then the data frame is restored to each service channel according to the channel scheduling table.
On the basis of the technical scheme, the scheduler comprises an ILK scheduler and a scheduler corresponding to the service type, and the receiver comprises a receiver corresponding to the service type and an ILK receiver; the ILK dispatcher and the ILK receiver are connected through a uniform data channel, and the dispatcher corresponding to the service type and the receiver corresponding to the service type are connected through a multi-channel service channel.
On the basis of the technical scheme, the sequence generator is used for generating Sar data frames and Ethernet data frames, and the Sar data frames support all types of Oduk services.
Compared with the prior art, the invention has the advantages that:
the invention can realize the mapping and de-mapping of the data frames generated by each sequence generator on each service channel and a unified data channel, the bus driving and receiving can adapt to the time sequence requirements of various interfaces, each channel and the service channel thereof can be well managed through the link controller, thereby realizing the verification requirements of multiple ports and two directions of the CPB module which can be completely compatible, and having good universality and flexibility.
Drawings
Fig. 1 is a system block diagram of a simulation verification system for scheduling packet cache supporting multiple channels according to an embodiment of the present invention;
FIG. 2 is a cpb _ equations simulation verification architecture for mode A of an embodiment of the present invention;
FIG. 3 is a cpb _ ingress simulation verification architecture of mode A of the present invention;
FIG. 4 is a cpb _ equations simulation verification architecture for mode B of an embodiment of the present invention;
FIG. 5 is a block diagram of Sar data frame generation according to an embodiment of the present invention;
FIG. 6 is a block diagram of a channel mapper in accordance with an embodiment of the present invention;
fig. 7 is a block diagram of a scheduler of an embodiment of the invention.
Detailed Description
Embodiments of the present invention will be described in further detail below with reference to the accompanying drawings.
The embodiment of the invention provides a simulation verification method for supporting multi-channel packet cache scheduling, which comprises the following steps:
the branch separation direction is used for mapping the data frames generated by each sequence generator to a unified data channel from each service channel according to the selection of the test mode, and scheduling the data frames through an ILK scheduler, or directly mapping the data frames generated by each sequence generator to a scheduler corresponding to each service type for scheduling; receiving the data frame after the simulation processing from the central packet cache module to be tested according to the bus time sequence, performing demodulation degree processing, and sending the data frame to the comparator modules corresponding to the sequence generators for comparison processing;
in the branch line integration direction, the data frames generated by each sequence generator are scheduled and sent to a central packet cache module to be tested according to the bus time sequence for simulation processing; and receiving the data frame after the simulation processing from the central packet cache module to be tested according to the bus time sequence, performing demodulation degree processing, demapping the data frame to each service channel, and sending the data frame to the comparator module corresponding to each sequence generator for comparison processing.
In order to adapt to the simulation test of packet cache scheduling, the embodiment of the present invention may configure two scenarios: interlaken shares a single disc with Ethernet and Otn, and is named as mode A; ethernet shares a single disk with Otn, designated as mode B.
The embodiment of the invention also provides a simulation verification system for supporting the multi-channel packet buffer scheduling, which comprises a plurality of sequence generation and transmission modules, a channel mapper, a scheduler, a receiver, a channel demapper and data comparators in one-to-one correspondence with the sequence generation modules. Referring to fig. 1, the present invention provides a block diagram of a simulation verification system for packet buffer scheduling supporting multiple channels. The whole system comprises two modes, namely a mode A and a mode B. Mode A includes two directions of verification platforms, cpb _ egress and cpb _ ingress. Referring to FIG. 2, a cpb _ equations simulation verification architecture for mode A of the present invention is shown; referring to FIG. 3, a cpb _ ingress simulation verification architecture of mode A of the present invention is shown; referring to FIG. 4, a cpb _ equations simulation verification architecture for mode B of the present invention is shown. In the figure, LR is a line reception side, CT is a client transmission side, CR is a client reception side, and LT is a line transmission side. Wherein, the In teraken shares a single disc with the Ethernet and Otn, which is the mode a of the embodiment of the present invention:
the sequence generation and transmission module is used for: generating data frames required by simulation, wherein each sequence generation and transmission module corresponds to one service channel and transmits the data frames to a channel mapper or a scheduler through each service channel;
the channel mapper is used for: uniformly mapping the data frames of all the service channels to a system channel and then sending the data frames to a scheduler;
the scheduler is configured to: scheduling the received data frame according to a set scheduling mode, and sending the data frame to a to-be-detected central packet cache module;
the receiver is used for: receiving data processed by the central packet cache module to be tested, recovering and encapsulating the data into data frames, and sending the data frames to a channel demapper or a data comparator;
the channel demapper is used for: demapping the data frames sent by the channel demodulator to each service channel, and sending the data frames to a data comparator corresponding to each service channel;
the data comparator is to: comparing the data frame required by simulation generated by the sequence generation module with the data frame processed by the central packet cache module to be tested, and judging whether the simulation processing is correct or not;
the link controller is configured to: and controlling the existence of the paths among the modules and the number of the service channels according to the test mode.
In a preferred embodiment, the Sar data frame generated by the sequence generator can support all types of Oduk services. The sequence transmitter comprises a B value generator component, the parameters of the Oduk such as the service type, the speed, the Bnorm and the like are configured, the B value generator component calculates a T value and a D value to obtain a B value, then the sequence transmitter transmits the B value to the sequence generator, the sequence generator performs slicing processing on the Oduk service according to the B value, and finally the sliced Oduk data are loaded to the Sar data frame.
As a preferred embodiment, the channel mapper maps N1 services of the Sar channel, N2 services of the Mac1 channel, and N3 services of the Mac2 channel to N service channels of the system according to a channel mapping table, where N1+ N2+ N3> N, so that the total number of service channels in which Sar, Mac1, and Mac2 configured by the link controller simultaneously operate cannot exceed N; the channel demapper demaps the services on the system channel to the respective service channels of the Sar channel, the Mac1 channel and the Mac2 channel.
In a preferred embodiment, the packet processing of the scheduler is divided into SEG MENT and packet modes. Under the PACKAGE mode, the data frame firstly carries out rate portrayal according to the channel and then sends the service serial to the bus driving module according to the channel scheduling table. Compared with the PACKAGE mode, in the SEGMENT mode, slicing processing is required to be carried out before rate portrayal is carried out on a data frame; the channel de-scheduling module also supports SEGMENT and PACKAGE modes, serial data are distributed to corresponding channels according to channels, SEGMENT data of each channel are restored into a PACKAGE data frame in the SE GMENT mode, and correctness of received data slices is detected.
As a preferred embodiment, the slicing process of the data frame in the SEGMENT mode is a satisfied enhanced slice, and the parameters to be configured are BurstMax, BurstMi n, and BurstShort. The parameters are set as follows: FrameLength: the total length of the data frame; FrameRemainder: the length of the data frame that has not yet been transmitted; burst transfer: data length of the current slice. Enhanced slicing of data frames:
when the FrameRemainder is more than BurstMax + BurstMin, the length of the BurstTransfer is BurstMax;
when framenende > BurstMax and framenende% BurstMa x < ═ BurstMin, the length of BurstTransfer is BurstMax-BurstMin;
length of cut package under other conditions: the length of BurstTransfer is frameremander;
the minimum length of the data frame cannot be lower than the burst short.
As a preferred embodiment, the bus driving module drives the data packet to the bus according to the bus timing sequence, and the interface signal has a mode supporting: a single SEGMENT and channel interpolation mode, a multi-SEGMENT and channel interpolation mode, a single SEGMENT and whole packet mode, and a multi-SEGMENT and whole packet mode; the bus receiving module receives data on the bus, encapsulates a data packet and sends the data packet to a downstream module. The bus receiving module also supports 4 bus interface timing driven by the bus and checks illegal time slots of the bus.
In a preferred embodiment, the data comparator receives data from the sequence transmitter after the packet buffer scheduling process, and then compares the two data. The results of the comparison are divided into three categories: the comparison is passed; if the comparison fails, printing the wrong frame information; and (4) data is lost, and the lost frame information is printed. Each service channel corresponds to a comparator for comparing the data frame sent by the current channel with the received data frame. The packet buffer scheduling works in the B mode, and the service channels are crossed, so that the simulation environment carries out channel de-crossing processing after demodulation degree, and each data comparator is ensured to process the data of the current channel.
In a preferred embodiment, the link controller is configured to control the presence or absence of the Sar, Mac1, and Mac2 lanes and configure the number of lanes in a lane. To adapt the simulation test of packet buffer scheduling, two directions can be configured by the link controller: egr direction (branch split); ingress direction (branch line in one). Referring to FIG. 2, a cpb _ equations simulation verification architecture of mode A of the present invention is shown; referring to fig. 3, a cpb _ ingress simulation verification architecture of mode a of the present invention is shown. Referring to FIG. 4, the embodiment of the present invention further provides a cpb _ equations emulation verification architecture for mode B, in which the Ethernet and the Ot n share a single disk.
As a preferred embodiment, the scheduler includes an ILK scheduler and a scheduler corresponding to a service type, and the receiver includes a receiver corresponding to a service type and an ILK receiver; the ILK dispatcher and the ILK receiver are connected through a uniform data channel, and the dispatcher corresponding to the service type and the receiver corresponding to the service type are connected through a multi-channel service channel.
The cpb _ equations simulation verification architecture of mode a of the embodiment of the present invention will be described in detail with reference to the specific cases.
Step S1, configuring the mode of the simulation environment, and controlling the simulation environment to operate in cpb _ equations of mode a by the link controller, as shown in fig. 2. The path of cpb _ egr consists of three paths of data: the number of service paths of Sar is 100, the number of service paths of Mac1 is 50, and the number of service paths of Mac2 is 100.
S2, configuring services of a simulation environment, starting 40 paths of services by a Mac1, carrying Ethernet services with the speed of 5Gbps by each channel, and enabling the frame length range to be 64-9600; mac2 starts 60 paths of services, each channel carries Ethernet services with the speed of 5Gbps, and the frame length range is 64-9600; sar starts 100 traffic, each channel carries Odu0 traffic at a rate of 1.244Gbps, Bnorm is configured to 256.
Step S3, generating and sending data frame, taking Sar data frame as an example. Referring to fig. 5, a block diagram is generated for the Sar data frame of the present invention, comprising the steps of:
firstly, parameters such as an Oduk service type, a speed, a Bnorm and the like which need to be borne by Sar are configured;
the BGenerator module calculates information such as T and D values according to the parameters so as to determine a B value, and finally transmits the B value to the Sar generator module;
the Sar generator module determines the length of data carried by the Sar frame according to the B value, slices data of the Odu k according to the size of the B value, fills the data field of the Sar frame, obtains overhead information of the Sar according to a protocol, finally obtains a complete Sar data frame, and sends the generated Sar frame to the Sar transmitter;
and fourthly, the Sar transmitter respectively transmits the Sar data frame to the channel mapper module and the Sar comparator module through the pipeline.
Step S4, mapping of service channel, as shown in fig. 6, is a block diagram of the channel mapper of the present invention. The data sources of the path mapping module are Sar, Mac1 and Mac2, the total service channel of the three paths of data has 250 paths, and the system supports 200 paths of service processing, so that the 250 paths of services need to be subjected to path mapping, and at most 200 paths of signals of the 250 paths are effective.
Firstly, channel conversion is carried out on three services, unified numbering is carried out, the number of a service channel of Sar is unchanged, the number of a service channel of Mac1 is converted from 0-49 to 100-149, and the number of a service channel of Mac2 is converted from 0-99 to 150-249; and mapping the 250-path channel number to the 200-path channel number according to the channel mapping table.
According to the service type configured in step S2, the configuration of the mapping table may be: 100 paths of services of the Sar service can be mapped to service channel numbers 0-99 of the system; 40 paths of services of Mac1 can be mapped to system service channel numbers of 100-139; the 60 routes of traffic of Mac2 can be mapped to system traffic channel numbers 140-199.
Step S5, scheduling the service, as shown in fig. 7, is a block diagram of the scheduler of the present invention. The scheduler can support data receiving and processing of two modes, namely, PACAKGE and SEGMENT. And (3) data processing flow:
configuring a data receiving mode of a scheduler to be a PACAKGE mode, and a data processing mode to be an SEGMENT mode;
and secondly, according to the configuration of the first step, the received package data packet needs to be sliced. The slice parameters are configured to: BurstMax 256, BurstMin 128, and BurstShort 64. Enhanced slicing algorithm of data frame:
when the FrameRemainder is greater than BurstMax + BurstMin, the length of the BurstTransfer is BurstMax;
when the frameremainder > BurstMax and frameremainder% BurstMax < ═ BurstMin, the length of BurstTransfer is BurstMax-BurstMin;
other cases cut package length: the length of BurstTransfer is frameremander;
the minimum length of the data frame cannot be below the burst short.
Thirdly, rate drawing is carried out on the service of each channel through a rate drawing module, for example, the rate of each service of Sar is 1.244Gbps, and the rates of the service channels of Mac1 and Mac2 are 5 Gbps;
fourthly, caching the data processed in the second step to the third step according to the channel;
fifthly, according to the scheduling table, the services cached in the step IV are sequentially sent to the bus driving module.
Step S6, driving data onto the bus, and the working mode of the bus driving module is: single SEGMENT mode and channel interpolation mode, multiple SEGMENT mode and channel interpolation mode, single SEGMENT mode and whole packet mode, and multiple SEGMENT mode and whole packet mode.
The working mode of the bus driving module is configured to be 4 SEGMENT and whole packet mode. The bus interface signals corresponding to the 4 SEGMENT are as follows: data line (data: 256 × 4bit), valid control (valid: 4bit), packet start control (sop: 4bit), packet end control (eop: 4bit), slice start control (sob: 4bit), slice receive control (eob 4: bit), channel number (chan: 8 × 4bit), valid byte (sz: 8 × 4bit), error indication (err: 4 bit); the whole packet mode indicates that the data packet in the channel must be continuously transmitted with the introduction before the data of other channels can be transmitted.
Step S7, data processing of cpb _ equations module: the data is subjected to shared buffering, the input data needs to be subjected to bubble squeezing processing, an exception packet is discarded, and three services are sent to data receiving modules of SarRx, Mac1Tx and Mac2 Tx.
Step S8, bus data receiving processing, where the Sar, Mac1 and Mac2 bus receiving modules are configured to 4 SEGMENT and full packet modes as well. And receiving the data on the bus, packaging the data into data frames, and respectively sending the data frames to the corresponding demodulation modules.
Step S9, data de-scheduling processing, namely, the Sar, Mac1 and Mac2 de-scheduling modules send data to the comparator module corresponding to each channel according to the scheduling table;
and step S10, comparing and verifying the data, wherein the comparator module receives the data from the signal transmitter and the demodulator and compares the two parts of data according to the frame number. The results of the comparison are divided into three categories: the comparison is passed; if the comparison fails, printing the wrong frame information; and (4) data is lost, and the lost frame information is printed.
The data processing through steps S1-S10 provides only a verification method of the cpb _ egr module, and more functions of the cpb _ egr module can be verified by changing the configuration parameters.
It will be apparent to those skilled in the art that various changes and modifications may be made in the present invention without departing from the spirit and scope of the invention. Thus, if such modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include such modifications and variations.
Claims (10)
1. A simulation verification method for supporting multi-channel packet buffer scheduling is characterized by comprising the following steps:
the branch line separation direction is used for mapping the data frames generated by each sequence generator to a unified data channel from each service channel according to the selection of the test mode, and scheduling the data frames through an ILK scheduler, or directly mapping the data frames generated by each sequence generator to a scheduler corresponding to each service type for scheduling; sending the bus time sequence to a to-be-tested central packet cache module for simulation processing; receiving the data frame after the simulation processing from the central packet cache module to be tested according to the bus time sequence, performing demodulation degree processing, and sending the data frame to the comparator modules corresponding to the sequence generators for comparison processing;
in the branch line integration direction, the data frames generated by each sequence generator are scheduled and sent to a central packet cache module to be tested according to the bus time sequence for simulation processing; and receiving the data frame after the simulation processing from the central packet cache module to be tested according to the bus time sequence, performing demodulation degree processing, demapping the data frame to each service channel, and sending the data frame to the comparator module corresponding to each sequence generator for comparison processing.
2. The method of claim 1, wherein: mapping the data frames generated by each sequence generator to a uniform data channel from each service channel, specifically comprising the following steps:
controlling the total number of the service channels working simultaneously not to exceed the total number of the unified data channels;
and mapping the data frames of all the service channels to the unified data channels according to the channel mapping table, wherein each service channel corresponds to one unified data channel.
3. The method of claim 1, wherein: carrying out scheduling processing on the data frame, wherein the scheduling processing comprises a data packet mode and a data segmentation mode:
in the data packet mode, rate depiction is carried out on a data frame according to a channel, and the data frame is driven to a bus interface of a central packet cache module to be tested according to a channel scheduling table;
and under the data segmentation mode, firstly, the data frame is cut into packets, the rate of the data frame after the packets are cut is described according to the channel, and the data frame after the packets are cut is driven to a bus interface of the central packet cache module to be tested according to the channel scheduling table.
4. The method of claim 1, wherein: carrying out demodulation degree processing on the data frame, wherein the demodulation degree processing comprises a data packet mode and a data segmentation mode:
under the data packet mode, restoring the data frame to each service channel according to the channel scheduling table;
and under the data segmentation mode, detecting the correctness of the received data slice, encapsulating the data frame, and restoring the data frame to each service channel according to the channel scheduling table.
5. The method of claim 1, wherein: the bus timing includes four modes: a single-segment and inter-channel difference mode, a multi-segment and inter-channel difference mode, a single-segment and whole-packet mode, and a multi-segment and whole-packet mode;
the difference mode between the single segment and the channel is as follows: only one segment is arranged on the bus, and the channels can be mutually inserted;
the multi-segment and channel difference mode: the bus is provided with a plurality of segments, and channels can be mutually inserted;
single segment and whole packet mode: only one segment is arranged on the bus, and the channels cannot be mutually inserted;
multi-segment and whole packet mode: the bus has a plurality of segments, and the channels cannot be mutually inserted.
6. The method of claim 1, wherein: the comparator module performs comparison processing, and specifically comprises the following steps: the comparator module compares the data frame processed by the central packet cache module to be tested with the original data frame, and judges whether the simulation processing of the central packet cache module to be tested is correct.
7. A simulation verification system for supporting multi-channel packet buffer scheduling comprises a plurality of sequence generation and transmission modules, a channel mapper, a scheduler, a receiver, a channel demapper and data comparators corresponding to the sequence generation modules one by one, wherein:
the sequence generation and transmission module is used for: generating data frames required by simulation, wherein each sequence generation and transmission module corresponds to one service channel and transmits the data frames to a channel mapper or a scheduler through each service channel;
the channel mapper is used for: uniformly mapping the data frames of all the service channels to a system channel and then sending the data frames to a scheduler;
the scheduler is configured to: scheduling the received data frame according to a set scheduling mode, and sending the data frame to a to-be-detected central packet cache module;
the receiver is configured to: receiving data processed by the central packet cache module to be tested, recovering and encapsulating the data into data frames, and sending the data frames to a channel demapper or a data comparator;
the channel demapper is used for: demapping the data frames sent by the channel demodulator to each service channel, and sending the data frames to a data comparator corresponding to each service channel;
the data comparator is to: comparing the data frame required by simulation generated by the sequence generation module with the data frame processed by the central packet cache module to be tested, and judging whether the simulation processing is correct or not;
the link controller is configured to: and controlling the existence of the access among the modules and the number of the service channels according to the test mode.
8. The system of claim 7, wherein:
the scheduler includes a packet mode and a data segmentation mode:
in the data packet mode, rate depiction is carried out on a data frame according to a channel, and the data frame is driven to a bus interface of a central packet cache module to be tested according to a channel scheduling table;
under the data segmentation mode, firstly, a data frame is cut into packets, the rate of the data frame after the packets are cut is described according to a channel, and the data frame after the packets are cut is driven to a bus interface of a central packet cache module to be tested according to a channel scheduling table;
the receiver includes a packet mode and a data segment mode:
under the data packet mode, restoring the data frame to each service channel according to the channel scheduling table;
under the data segmentation mode, firstly, the correctness of the received data slice is detected, the data frame is encapsulated, and then the data frame is restored to each service channel according to the channel scheduling table.
9. The system of claim 7, wherein the scheduler comprises an ILK scheduler and a traffic type corresponding scheduler, and the receiver comprises a traffic type corresponding receiver and an ILK receiver; the ILK dispatcher and the ILK receiver are connected through a uniform data channel, and the dispatcher corresponding to the service type and the receiver corresponding to the service type are connected through a multi-channel service channel.
10. The system of claim 7, wherein the sequence generator is configured to generate Sar data frames and ethernet data frames, the Sar data frames supporting all types of Oduk services.
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