CN110687854B - PA bus controller and PA bus control system - Google Patents
PA bus controller and PA bus control system Download PDFInfo
- Publication number
- CN110687854B CN110687854B CN201911071505.6A CN201911071505A CN110687854B CN 110687854 B CN110687854 B CN 110687854B CN 201911071505 A CN201911071505 A CN 201911071505A CN 110687854 B CN110687854 B CN 110687854B
- Authority
- CN
- China
- Prior art keywords
- data
- fpga
- bus
- control chip
- control
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 230000003993 interaction Effects 0.000 claims description 28
- 238000000034 method Methods 0.000 claims description 25
- 230000008569 process Effects 0.000 claims description 21
- 230000005540 biological transmission Effects 0.000 claims description 8
- 238000003745 diagnosis Methods 0.000 claims description 4
- 230000009977 dual effect Effects 0.000 claims description 4
- 238000004806 packaging method and process Methods 0.000 claims description 4
- 238000004891 communication Methods 0.000 abstract description 18
- 230000006870 function Effects 0.000 abstract description 15
- 238000012545 processing Methods 0.000 abstract description 14
- 238000012423 maintenance Methods 0.000 abstract description 5
- 238000005457 optimization Methods 0.000 abstract description 3
- 230000009286 beneficial effect Effects 0.000 abstract description 2
- 238000010586 diagram Methods 0.000 description 7
- 238000013461 design Methods 0.000 description 3
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 230000005856 abnormality Effects 0.000 description 1
- 230000004913 activation Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 238000005314 correlation function Methods 0.000 description 1
- 238000001514 detection method Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000003999 initiator Substances 0.000 description 1
- 238000012544 monitoring process Methods 0.000 description 1
- 230000000737 periodic effect Effects 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 238000004886 process control Methods 0.000 description 1
- 230000000750 progressive effect Effects 0.000 description 1
Images
Classifications
-
- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
- G05B19/00—Programme-control systems
- G05B19/02—Programme-control systems electric
- G05B19/04—Programme control other than numerical control, i.e. in sequence controllers or logic controllers
- G05B19/042—Programme control other than numerical control, i.e. in sequence controllers or logic controllers using digital processors
- G05B19/0421—Multiprocessor system
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L12/00—Data switching networks
- H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
- H04L12/40—Bus networks
Landscapes
- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Automation & Control Theory (AREA)
- Information Transfer Systems (AREA)
- Bus Control (AREA)
Abstract
The invention discloses a PA bus controller, comprising: FPGA and CPU; a protocol stack of a PA physical layer and a data link layer is integrated in the FPGA; and the CPU is connected with the FPGA and is used for calling the FPGA to carry out bus scheduling control. The device calls the FPGA in the master station communication module, related functions of a PA physical layer and a data link layer are added in the original FPGA logic, a PA protocol stack is integrated in the original FPGA, a PA special chip is not needed, the use cost is reduced, flexible configuration and programming are realized, the optimization limitation of communication between a CPU and the protocol stack is reduced, hardware fault points are reduced, and the maintenance cost is reduced. And the CPU is realized by adopting a core architecture of 'FPGA + double control chips', so that the processing pressure during single-chip processing is reduced, and the high efficiency of task processing can be ensured. The invention also provides a PA bus control system, which has the beneficial effects.
Description
Technical Field
The invention relates to the technical field of PA (power amplifier) buses, in particular to a PA bus controller and a PA bus control system.
Background
The PA is short for Profibus-PA, which is an international, open, field bus standard independent of the device manufacturer. The PA connects automation and process control systems to field devices such as pressure, temperature and level transmitters and can be used in place of the 4-20mA analog technology. The PA bus has a master device (master station) and a slave device (slave station), and the master device is generally responsible for scheduling communication of the bus and the like, and is an active initiator of communication.
The current PA product is mainly PA slave equipment, and few manufacturers for realizing PA master equipment are available. In the existing product, the realization circuit is also generally realized by integrating a PA special chip, namely, the realization mode of 'CPU + PA special chip' is adopted, the chip cost is higher, the PA protocol stack is integrated on the special chip, a communication and configuration interface is provided for the CPU, the CPU only needs to be configured and programmed according to the interface, the communication between the CPU and the protocol stack has optimization limitation, the special chip has more pins, the hardware structure is more complex, the maintenance and replacement procedures are more complicated, and the maintenance cost is higher.
Therefore, how to reduce the use cost of the PA bus controller, simplify the hardware configuration, and improve the flexibility of the PA bus control implementation is a technical problem to be solved by those skilled in the art.
Disclosure of Invention
The invention aims to provide a PA bus controller, which can reduce the use cost of the PA bus controller, simplify the hardware configuration and improve the flexibility of the PA bus control; another object of the present invention is to provide a PA bus control system having the above-mentioned advantages.
To solve the above technical problem, the present invention provides a PA bus controller, including:
FPGA and CPU;
a protocol stack of a PA physical layer and a data link layer is integrated in the FPGA;
the CPU is connected with the FPGA and used for calling the FPGA to carry out bus scheduling control;
wherein the CPU comprises: the system comprises a first control chip and a second control chip; the first control chip is integrated with a PA main protocol stack and a user layer software protocol stack, and the second control chip is integrated with software for realizing other applications of the controller.
Optionally, the first control chip is a first ARM chip, and the second control chip is a second ARM chip.
Optionally, the FPGA includes a dual-port RAM, and the first control chip and the second control chip exchange data through the dual-port RAM implemented by the FPGA.
Optionally, the dual-port RAM includes control bytes for data interaction authority control: PAFlags and CPUFlags;
correspondingly, the first control chip is used for: reading the PAFlags, writing the CPUFlags, exchanging data of the dual-port RAM when the bits of the PAFlags and the CPUFlags are not equal, and negating the bits of the CPUFlags when the data exchange is finished;
the second control chip is used for: writing the PAFlags, reading the CPUFlags, exchanging data between an internal buffer area and the dual-port RAM when the phases of the PAFlags and the CPUFlags are equal, and negating the PAFlags when the data exchange is finished.
Optionally, the second control chip is configured to: and the first control chip carries out data interaction based on the double-port RAM, processes input and output data from an upper computer or a PA bus direction, processes state jump of a protocol state machine, and completes data interaction with the FPGA.
Optionally, the FPGA is configured to:
continuously intercepting data on the PA bus in a bit-by-bit manner, when the intercepted data is a lead code, carrying out Mansidester decoding on the received data, comparing a check code logically calculated by the receiving data with the received check code after the decoding is successful, discarding a message and giving an alarm if an error is detected, and writing the processed data into a receiving Buff for a second control chip to read if the check is correct; taking out data from the transmission Buff and packaging the data to generate transmission data, carrying out Mansidester coding on the transmission data to generate data to be output, and sequentially transmitting the data to be output to a PA hardware circuit in a bit-by-bit manner;
correspondingly, the second control chip is used for: and writing the downlink data into the sending Buff.
Optionally, the FPGA is further configured to: and reading back a sending message to perform link diagnosis while sending the data to be output.
The invention discloses a PA bus control system, comprising: the PA bus controller is connected with the PA bus controller through the PA bus.
Optionally, the PA bus control system further includes: and the upper computer is connected with the PA bus controller through the Ethernet.
The PA bus controller provided by the invention comprises: FPGA and CPU; a protocol stack of a PA physical layer and a data link layer is integrated in the FPGA; and the CPU is connected with the FPGA and is used for calling the FPGA to carry out bus scheduling control. The device calls the FPGA in the master station communication module. Increase in original FPGA logic and realize PA physical layer and data link layer correlation function, it is integrated at original FPGA with PA protocol stack, need not use PA special chip, the use cost of PA special chip has been reduced, compare simultaneously in the fixed configuration of PA special chip and programming mode, use FPGA can nimble activation configuration and programming, reduce the optimization restriction of communication between CPU and protocol stack, and FPGA compares in special chip pin few, maintenance and change process are comparatively loaded down with trivial details, hardware architecture is more greatly simplified when transferring original FPGA in the master station communication module, the hardware fault point has been reduced, the maintenance cost is reduced. The CPU is realized by adopting a core architecture of FPGA and double control chips, wherein one control chip realizes a PA main protocol stack and user layer software; and the other control chip realizes software related to other applications (such as control operation) of the controller. The control respectively processes the tasks with high and low time sequence requirements, so that the processing pressure during single-chip processing is reduced, and the high efficiency of task processing can be ensured.
The invention also provides a PA bus control system, which has the beneficial effects and is not described in detail herein.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the provided drawings without creative efforts.
Fig. 1 is a schematic structural diagram of a PA bus controller according to an embodiment of the present invention;
fig. 2 is a schematic diagram illustrating a dual-port RAM data interaction permission control according to an embodiment of the present invention;
FIG. 3 is a flowchart illustrating software control of a second control chip according to an embodiment of the present invention;
fig. 4 is a logic block diagram of the related functions of the physical layer and the data link layer of the PA protocol implemented by the FPGA logic according to the embodiment of the present invention;
fig. 5 is a schematic structural diagram of a PA bus control system according to an embodiment of the present invention.
Detailed Description
The core of the invention is to provide a PA bus controller, the device can reduce the use cost of the PA bus controller, simplify the hardware configuration, and improve the flexibility of the PA bus control; it is another object of the present invention to provide a PA bus control system.
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all, embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
The general master station communication module is provided with a CPU and an FPGA, even though PA communication is not considered, the CPU and the FPGA already exist, and if the related functions of a physical layer and a data link layer of a PA protocol can be realized in the existing FPGA through logic design, a PA special chip is not needed. The PA protocol is added in the mode, the protocol stack is integrated in the FPGA, the hardware is simple, the hardware fault points can be reduced, and the cost is saved.
The PA bus controller provided in this embodiment mainly includes: FPGA and CPU.
The FPGA is integrated with a protocol stack of a PA physical layer and a data link layer. In order to reduce hardware devices, the FPGA called in this embodiment may be the original FPGA in the master station communication module. The related functions of a PA physical layer (such as Manchester coding and decoding) and a data link layer are added in the original FPGA logic, a PA protocol stack is integrated in the original FPGA, the whole hardware is simple, the hardware fault points can be reduced, and the cost is saved.
And the CPU is connected with the FPGA and is used for calling the FPGA to carry out bus scheduling control.
In this embodiment, the control mode of the CPU for controlling the FPGA to perform bus scheduling control is not limited, and the CPU may be set with reference to the CPU controller in the original PA bus controller. Because the controller has tasks with high real-time requirements to be processed, and the PA protocol stack also needs to have certain periodic communication requirements, the software implementation is relatively complex, and in order to improve the efficiency of task processing and the reliability of device operation, preferably, the CPU specifically includes: the device comprises a first control chip and a second control chip.
The first control chip is integrated with a PA main protocol stack and a user layer software protocol stack, and the second control chip is integrated with software for realizing other applications of the controller.
The CPU is realized by adopting a core architecture of FPGA and double control chips, wherein one control chip realizes a PA main protocol stack and user layer software; and the other control chip realizes software related to other applications (such as control operation) of the controller. The control respectively processes the tasks with high and low time sequence requirements, so that the processing pressure during single-chip processing is reduced, and the high efficiency of task processing can be ensured.
It should be noted that the specific device type of the control chip is not limited, for example, the control chip may be a DSP, an ARM, and the like, and preferably, the first control chip may be a first ARM chip, and the second control chip may be a second ARM chip. In recent years, ARM is developed rapidly, and the occupancy rate in the market is higher and higher. In view of product economy and maintainability, the use of an ARM chip is preferred over the use of a DSP chip.
In addition, the dual control chip performs data interaction in the FPGA, and may use a serial port or a standard bus structure for communication, in this embodiment, the implementation manner of data interaction control of the FPGA when the dual control chip is used to implement bus scheduling control is not limited, and in order to adapt to the occasions with large amount of interaction data and high access rate, the bus control interface circuit is simplified at the same time.
The double-port RAM is designed and realized by logic codes in the FPGA and used for data interaction between a controller operation CPU and a PA main protocol stack CPU, two control chips exchange data through the double-port RAM realized by the FPGA, peripheral double-port RAM chips can be saved, hardware fault points can be reduced, cost is saved, meanwhile, stability under certain data transmission quantity can be guaranteed by performing double-port control through a double-port RAM module, access of the two control chips is relatively independent, high data access efficiency is guaranteed, and a data interaction interface between the logic codes and the CPU can be flexibly designed in the FPGA, so that the integrity and flexibility of the CPU codes can be better guaranteed. Specifically, the data exchange between the first control chip and the second control chip through the dual-port RAM implemented by the FPGA may specifically include: the second control chip completes communication with the upper computer through the dual-port RAM and the operation CPU, and a user can complete configuration downloading of PA engineering, read and write of equipment parameters on a PA bus and the like through the upper computer configuration tool.
Further, in order to alleviate the flow abnormality caused by the data processing collision of the dual ARM chip, a control byte for controlling the data interaction authority can be set in the dual-port RAM: PAFlags and CPUFlags; fig. 2 is a schematic diagram illustrating a data interaction authority control of a dual-port RAM, which implements a data interaction authority control function of a PA main protocol stack and a controller arithmetic CPU, and accordingly, the first control chip is configured to: reading PAFlags and writing CPUFlags, and when the positions of the PAFlags and the CPUFlags are different, performing data exchange on the dual-port RAM, and negating the CPUFlags when the data exchange is finished; the second control chip is used for: and writing PAFlags, reading CPUFlags, exchanging data between the internal buffer area and the dual-port RAM when the phases of the PAFlags and the CPUFlags are equal, and negating the PAFlags when the data exchange is finished.
2 bytes are defined in the dual-port RAM for data interaction authority control, and specifically, the data interaction authority control process of the dual-port RAM is as follows:
1) and after the CPU is operated and initialized by the controller, setting CPUFlags. NotRDY to indicate that the data in the output area is unavailable. The controller operates that the CPU has available output data and then copies the available output data to an output area of the dual-port RAM, and then clears CPUFlags.
2) And after the PA main protocol stack is electrified and initialized, setting PAFlags.
3) And the controller operates the CPU to write the configuration information of the downloading slave station into a corresponding area of the dual-port RAM for the PA main protocol stack, and sets the downloading identifier in the dual-port RAM. And (3) the PA main protocol stack inquires the downloading identification in the dual-port RAM, if non-zero indicates that new slave station downloading data exists, reading parameters and a configuration area in the dual-port RAM, and clearing 0 the dual-port downloading identification after acquiring the downloading data.
4) The PA main protocol stack analyzes the slave station configuration data to form a slave station data set, whether the CPU operated by the controller is set CPUFlags.NotRDY is inquired, if the CPUFlags.NotRDY is 0, the CPU operated by the controller is ready, the PA main protocol stack is set PAFlags.RUN, the PA main protocol stack enters an OPERATE state, and communication with the slave station is started. If cpuflags. notrdy is 1, it indicates that the controller arithmetic CPU is not ready, paflags. run is not set, and the PA master protocol stack is kept in the OFFLINE state.
5) And setting PAFlags.COM after the PA master protocol stack establishes data exchange with the slave station.
6) In each effective bus cycle, the PA main protocol stack and the controller operation CPU need to exchange data with the dual-port RAM. When the phases of paflags.pa _ NewDAT and cpuflags.cpu _ NewDAT are equal, the PA master protocol stack obtains access to process data in the dual-port RAM, data exchange between the internal buffer area and the dual-port RAM is performed, and when the data exchange is finished, the phases of paflags.pa _ NewDAT are inverted. When bits of PAFlags, PA _ NewDAT and CPUFlags, CPU _ NewDAT are unequal, the controller operation CPU obtains access right to the dual-port RAM, when the controller operation CPU completes data exchange with the dual-port RAM, the bits of the CPUFlags, CPU _ NewDAT of the DevFlags are inverted, at the moment, the values of the PAFlags, PA _ NewDAT and CPUFlags, CPU _ NewDAT are equal, and the PA main protocol stack obtains access right of the dual-port RAM again.
In this embodiment, the logic control process of the PA master protocol stack implemented by the second control chip is not limited, and preferably, the second control chip having the following functions may be specifically selected: and the first control chip carries out data interaction based on the dual-port RAM, processes input and output data from the upper computer or the PA bus direction, processes the state jump of the protocol state machine, and completes the data interaction with the FPGA. Correspondingly, the flow of calling the second control chip with the above functions to cooperate with the first control chip to perform software control operation is substantially as follows:
1) and the controller is in cold reset, the first control chip of the controller is initialized preferentially, and then the second control chip is guided to be initialized. The initialization work of the second control chip comprises memory allocation, initialization detection of FPGA logic, initialization of a PA protocol stack, starting of a timer and the like.
2) The first control chip processes the data packet from the upper computer and forwards configuration data related to the PA to the dual-port RAM.
3) And the second control chip performs configuration on the protocol stack and the equipment on the PA bus according to configuration information downloaded from the upper computer.
4) And the second control chip schedules and manages each PA device on the bus, and the bus enters a normal communication state and carries out data exchange.
5) The first control chip and the second control chip exchange data through the double-port RAM, and the data comprise input and output process data, alarm diagnosis information and the like.
A software control flow chart of the second control chip is shown in fig. 3, in which a PA main protocol stack is initialized first, and then enters a loop function, and the loop process works as follows: and the double-port RAM data interaction is carried out with a controller operation CPU, the input and output data from the upper computer or the PA bus direction are processed, the state jump of a protocol state machine is processed, and the data interaction with the FPGA is completed.
In addition, in this embodiment, the logic control process of the protocol stack for implementing the PA physical layer and the data link layer by the FPGA is not limited, and preferably, the FPGA having the following functions may be specifically selected: continuously monitoring data on the PA bus in a bit-by-bit mode, when the monitored data is a lead code, carrying out Mansidester decoding on the received data, comparing a check code logically calculated by the receiving data with the received check code after the decoding is successful, discarding a message and giving an alarm if an error is detected, writing the processed data into a receiving Buff if the check is correct, and enabling the processed data to be read by a second control chip through 'data interaction logic control'; taking out the data from the 'sending Buff' and packaging the data to generate sending data, carrying out Mansiderster coding on the sending data to generate data to be output, and sequentially sending the data to be output to a PA hardware circuit in a bit-by-bit manner;
accordingly, the second control chip is configured to: and writing the downlink data into the transmission Buff.
Specifically, the process of calling the FPGA with the above function to receive and transmit data is as follows:
the FPGA data receiving process comprises the following steps: the FPGA continuously monitors data on the PA bus in a bit-by-bit mode through data receiving control logic, when the monitored data is a lead code, Manchester (Mansidester) decoding is carried out on the received data, and if the decoding is successful, the FPGA enters into processing logic for receiving a message. The FPGA compares the check code logically calculated by the FPGA with the received check code, discards the message and gives an alarm if an error is detected, writes the processed data into a receiving Buff if the check is correct, and supplies the data to an ARM chip at the PA main protocol stack side for reading through data interaction logic control.
The FPGA data sending process comprises the following steps: and the second control chip writes the downlink data into the sending Buff through the 'data interaction logic control' in the FPGA. The FPGA takes out data from the sending Buff and performs packaging, performs packet header and packet tail processing to generate sending data, performs Mansiderster coding on the sending data, generates a lead code, an initial delimiter and the like, forms data to be output by the lead code, the initial delimiter and the sending data, and sequentially sends the data to be output to the PA hardware circuit bit by bit through a data sending control logic.
In this embodiment, only the above implementation process is described as an example, and other implementation flows can refer to the above description, which is not described herein again.
The PA main protocol stack program can perform data interaction with equipment on a PA bus through an FPGA logic program, in order to improve the operation stability in the data processing process, an FPGA which transmits data to be output and reads back a message for link diagnosis can be selected, and correspondingly, a logic block diagram of the related functions of a physical layer and a data link layer of the PA protocol is realized by the FPGA logic, and is shown in figure 4.
In the PA master station device provided in the introduction, a chip dedicated to a protocol stack is not used, logic design is performed in an FPGA to realize functions related to a physical layer and a data link layer of a PA protocol, a dual-port RAM can be realized in the FPGA by logic code design, and the dual-port RAM is used for data interaction between a controller operation CPU and a PA master protocol stack CPU, that is, the whole PA bus controller is realized by using an ARM software + FPGA logic core architecture mode, so that hardware fault points can be reduced, cost is saved, and the integrity and flexibility of a CPU code can be better ensured.
The present invention further provides a PA bus control system, which mainly includes the PA bus controller introduced in the above embodiment, and a PA meter connected to the PA bus controller through a PA bus, as shown in fig. 5, which is a schematic structural diagram of the PA bus control system.
One ARM chip in the PA bus controller realizes a PA master station protocol stack, and the other ARM chip realizes the operation of a relevant program of a CPU by the controller; and the two ARM chips carry out data interaction through a double-port RAM realized by the FPGA. After the protocol stack is initialized and operated normally, communication is established with the slave station through the FPGA logic and the PA bus, and data interaction is completed.
It should be noted that other logic modules in the PA bus controller refer to an FPGA original logic module, and the PA bus controller provided by the present invention does not include other logic modules when an original function module is used to call an original FPGA and when a new FPGA is added.
In addition, in this embodiment, other components included in the system are not limited. Optionally, the system may further include: and the upper computer is connected with the PA bus controller through the Ethernet. The upper computer is connected with the Ethernet through a logic interface of the PA bus controller.
The upper computer can realize configuration of the PA bus controller, after the system works normally, data of the PA can be sent to the upper computer through the Ethernet for display, and the upper computer can also manually input command data related to the PA and send the command data to the controller through the Ethernet. Configuration software of the upper computer can complete configuration of the PA main protocol stack through links such as an FPGA, an ARM chip and a dual-port RAM. The connection of other system components for function expansion or other functions is not limited in this embodiment, and is only described by taking the host computer as an example.
The embodiments are described in a progressive manner in the specification, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments are referred to each other. The device disclosed by the embodiment corresponds to the method disclosed by the embodiment, so that the description is simple, and the relevant points can be referred to the method part for description.
The PA bus controller and a server provided by the present invention are described in detail above. The principles and embodiments of the present invention are explained herein using specific examples, which are presented only to assist in understanding the method and its core concepts. It should be noted that, for those skilled in the art, it is possible to make various improvements and modifications to the present invention without departing from the principle of the present invention, and those improvements and modifications also fall within the scope of the claims of the present invention.
Claims (7)
1. A PA bus controller, comprising: FPGA and CPU; the CPU includes: the system comprises a first control chip and a second control chip;
a protocol stack of a PA physical layer and a data link layer is integrated in the FPGA; the FPGA comprises a double-port RAM, and the first control chip and the second control chip exchange data through the double-port RAM realized by the FPGA;
the CPU is connected with the FPGA and used for calling the FPGA to carry out bus scheduling control;
the first control chip is integrated with a PA main protocol stack and a user layer software protocol stack, and the second control chip is integrated with software for realizing other applications of the controller; the other application-related software is controller software except the PA main protocol stack and the user layer software and comprises control operation software; the second control chip is used for: and the first control chip carries out data interaction based on the double-port RAM, processes input and output data from an upper computer or a PA bus direction, processes state jump of a protocol state machine, and completes data interaction with the FPGA.
2. The PA bus controller of claim 1, wherein the first control chip is a first ARM chip and the second control chip is a second ARM chip.
3. The PA bus controller of claim 1, wherein the dual port RAM includes control bytes for data interaction permission control: PAFlags and CPUFlags;
correspondingly, the first control chip is used for: reading the PAFlags, writing the CPUFlags, exchanging data of the dual-port RAM when the bits of the PAFlags and the CPUFlags are not equal, and negating the bits of the CPUFlags when the data exchange is finished;
the second control chip is used for: writing the PAFlags, reading the CPUFlags, exchanging data between an internal buffer area and the dual-port RAM when the phases of the PAFlags and the CPUFlags are equal, and negating the PAFlags when the data exchange is finished.
4. The PA bus controller of claim 1, wherein the FPGA is to:
continuously intercepting data on the PA bus in a bit-by-bit manner, when the intercepted data is a lead code, carrying out Mansidester decoding on the received data, comparing a check code logically calculated by the receiving data with the received check code after the decoding is successful, discarding a message and giving an alarm if an error is detected, and writing the processed data into a receiving Buff for a second control chip to read if the check is correct; taking out data from the transmission Buff and packaging the data to generate transmission data, carrying out Mansidester coding on the transmission data to generate data to be output, and sequentially transmitting the data to be output to a PA hardware circuit in a bit-by-bit manner;
correspondingly, the second control chip is used for: and writing the downlink data into the sending Buff.
5. The PA bus controller of claim 4, wherein the FPGA is further to: and reading back a sending message to perform link diagnosis while sending the data to be output.
6. A PA bus control system, comprising: the PA bus controller of any of claims 1 to 5, and a PA meter connected to the PA bus controller via a PA bus.
7. The PA bus control system of claim 6, further comprising: and the upper computer is connected with the PA bus controller through the Ethernet.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201911071505.6A CN110687854B (en) | 2019-11-05 | 2019-11-05 | PA bus controller and PA bus control system |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201911071505.6A CN110687854B (en) | 2019-11-05 | 2019-11-05 | PA bus controller and PA bus control system |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN110687854A CN110687854A (en) | 2020-01-14 |
| CN110687854B true CN110687854B (en) | 2021-07-30 |
Family
ID=69116496
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201911071505.6A Active CN110687854B (en) | 2019-11-05 | 2019-11-05 | PA bus controller and PA bus control system |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN110687854B (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116974233B (en) * | 2023-09-19 | 2024-01-19 | 西安热工研究院有限公司 | Dual-channel Profibus-DP master station system and design method |
Citations (20)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1728120A (en) * | 2004-07-28 | 2006-02-01 | 三星电子株式会社 | Control system and bus connecting method with master controller and peripheral controllers |
| CN201017459Y (en) * | 2007-03-13 | 2008-02-06 | 同方威视技术股份有限公司 | Radiation image-forming data acquisition equipment |
| CN101346700A (en) * | 2005-12-26 | 2009-01-14 | 安泰科技有限公司 | Portable device and method for controlling shared memory in portable device |
| CN101841542A (en) * | 2010-05-07 | 2010-09-22 | 北京鼎实创新科技有限公司 | Method for realizing PROFIBUS master station communication protocol based on FPGA (Field Programmable Gate Array) technology |
| CN102231071A (en) * | 2011-05-16 | 2011-11-02 | 北京和利时系统工程有限公司 | Train control vehicle-mounted display device |
| CN202178790U (en) * | 2011-05-16 | 2012-03-28 | 上海华建电力设备股份有限公司 | Industrial bus interface supporting configurable protocol |
| CN102486755A (en) * | 2010-12-03 | 2012-06-06 | 罗伯特·博世有限公司 | Memory protection unit and method for controlling access to memory device |
| CN102789210A (en) * | 2011-05-16 | 2012-11-21 | 上海华建电力设备股份有限公司 | Configurable industrial bus interface supporting protocol |
| CN102833142A (en) * | 2012-09-10 | 2012-12-19 | 天津理工大学 | Profibus-DP slave station device on basis of FDGA (Field Programmable Gate Array) |
| CN103346943A (en) * | 2013-07-18 | 2013-10-09 | 杭州和利时自动化有限公司 | Method and system of data transmission |
| CN104021108A (en) * | 2014-05-28 | 2014-09-03 | 中山火炬职业技术学院 | Communication equipment based on PROFIBUS-DP protocol |
| CN105425681A (en) * | 2015-12-16 | 2016-03-23 | 中国电子信息产业集团有限公司第六研究所 | Multifunctional communication interface data diagnosis and signal driving card |
| CN106647500A (en) * | 2016-12-26 | 2017-05-10 | 上海振华重工电气有限公司 | ARM and FPGA based ship power positioning control system |
| CN106882657A (en) * | 2017-03-01 | 2017-06-23 | 南京理工大学 | A kind of multi-connected machine team control type lift driving and controlling system |
| CN107526537A (en) * | 2016-06-22 | 2017-12-29 | 伊姆西公司 | For locking the method and system of the storage region in storage system |
| CN108733315A (en) * | 2017-04-17 | 2018-11-02 | 伊姆西Ip控股有限责任公司 | Method, equipment and computer readable storage medium for storage management |
| CN109407578A (en) * | 2018-10-15 | 2019-03-01 | 杭州和利时自动化有限公司 | A kind of data processing method of Profibus-DP bus control unit |
| CN109901469A (en) * | 2019-03-12 | 2019-06-18 | 北京鼎实创新科技股份有限公司 | A method of PROFIBUS-PA bus communication is realized based on FPGA technology |
| CN109901954A (en) * | 2019-02-25 | 2019-06-18 | 浙江大华技术股份有限公司 | Store equipment and method for managing resource |
| CN110377221A (en) * | 2018-04-13 | 2019-10-25 | 北京忆恒创源科技有限公司 | Dual-port solid storage device and its data processing method |
Family Cites Families (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE10030329C1 (en) * | 2000-06-27 | 2002-01-24 | Siemens Ag | Redundant control system as well as control computer and peripheral unit for such a control system |
| CN201435738Y (en) * | 2009-05-22 | 2010-03-31 | 浙江天正电气股份有限公司 | PROFIBUS-DP and CAN field bus protocol converter |
| SG2013051982A (en) * | 2013-07-04 | 2015-02-27 | Pteris Global Ltd | Motor drive controller |
| CN103834934B (en) * | 2013-12-11 | 2016-05-11 | 南方科技大学 | Control system for plasma enhanced chemical vapor deposition |
| DE102015011296A1 (en) * | 2015-09-02 | 2017-03-02 | Wabco Gmbh | Electronically controllable pneumatic braking system in a utility vehicle and method for electronically controlling a pneumatic braking system |
| DE112017002494T5 (en) * | 2016-05-16 | 2019-02-28 | Fisher-Rosemount Systems, Inc. | MULTIPROTOCOL FIELD DEVICE IN PROCESS CONTROL SYSTEMS |
| US9847802B1 (en) * | 2016-08-16 | 2017-12-19 | Xilinx, Inc. | Reconfiguration of single-band transmit and receive paths to multi-band transmit and receive paths in an integrated circuit |
| CN107783447A (en) * | 2016-08-29 | 2018-03-09 | 李福霞 | A kind of electrohydraulic servo-controlling system based on PROFIBUS DP |
| EP3401742B1 (en) * | 2017-05-09 | 2020-09-02 | Siemens Aktiengesellschaft | Automation system and method for operating same |
| CN107168157A (en) * | 2017-05-17 | 2017-09-15 | 西安交通大学 | Opened industrial robot controller architecture based on dual processors+FPGA |
| CN107577183A (en) * | 2017-09-06 | 2018-01-12 | 太仓埃特奥数据科技有限公司 | A kind of chamber crop real time data processing analysis system |
| CN109347884B (en) * | 2018-12-05 | 2021-05-28 | 北京和利时系统工程有限公司 | Method and device for converting real-time Ethernet to field bus and storage medium |
-
2019
- 2019-11-05 CN CN201911071505.6A patent/CN110687854B/en active Active
Patent Citations (21)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1728120A (en) * | 2004-07-28 | 2006-02-01 | 三星电子株式会社 | Control system and bus connecting method with master controller and peripheral controllers |
| CN100392630C (en) * | 2004-07-28 | 2008-06-04 | 三星电子株式会社 | Control system having main controller peripheral controller and bus connection |
| CN101346700A (en) * | 2005-12-26 | 2009-01-14 | 安泰科技有限公司 | Portable device and method for controlling shared memory in portable device |
| CN201017459Y (en) * | 2007-03-13 | 2008-02-06 | 同方威视技术股份有限公司 | Radiation image-forming data acquisition equipment |
| CN101841542A (en) * | 2010-05-07 | 2010-09-22 | 北京鼎实创新科技有限公司 | Method for realizing PROFIBUS master station communication protocol based on FPGA (Field Programmable Gate Array) technology |
| CN102486755A (en) * | 2010-12-03 | 2012-06-06 | 罗伯特·博世有限公司 | Memory protection unit and method for controlling access to memory device |
| CN102231071A (en) * | 2011-05-16 | 2011-11-02 | 北京和利时系统工程有限公司 | Train control vehicle-mounted display device |
| CN202178790U (en) * | 2011-05-16 | 2012-03-28 | 上海华建电力设备股份有限公司 | Industrial bus interface supporting configurable protocol |
| CN102789210A (en) * | 2011-05-16 | 2012-11-21 | 上海华建电力设备股份有限公司 | Configurable industrial bus interface supporting protocol |
| CN102833142A (en) * | 2012-09-10 | 2012-12-19 | 天津理工大学 | Profibus-DP slave station device on basis of FDGA (Field Programmable Gate Array) |
| CN103346943A (en) * | 2013-07-18 | 2013-10-09 | 杭州和利时自动化有限公司 | Method and system of data transmission |
| CN104021108A (en) * | 2014-05-28 | 2014-09-03 | 中山火炬职业技术学院 | Communication equipment based on PROFIBUS-DP protocol |
| CN105425681A (en) * | 2015-12-16 | 2016-03-23 | 中国电子信息产业集团有限公司第六研究所 | Multifunctional communication interface data diagnosis and signal driving card |
| CN107526537A (en) * | 2016-06-22 | 2017-12-29 | 伊姆西公司 | For locking the method and system of the storage region in storage system |
| CN106647500A (en) * | 2016-12-26 | 2017-05-10 | 上海振华重工电气有限公司 | ARM and FPGA based ship power positioning control system |
| CN106882657A (en) * | 2017-03-01 | 2017-06-23 | 南京理工大学 | A kind of multi-connected machine team control type lift driving and controlling system |
| CN108733315A (en) * | 2017-04-17 | 2018-11-02 | 伊姆西Ip控股有限责任公司 | Method, equipment and computer readable storage medium for storage management |
| CN110377221A (en) * | 2018-04-13 | 2019-10-25 | 北京忆恒创源科技有限公司 | Dual-port solid storage device and its data processing method |
| CN109407578A (en) * | 2018-10-15 | 2019-03-01 | 杭州和利时自动化有限公司 | A kind of data processing method of Profibus-DP bus control unit |
| CN109901954A (en) * | 2019-02-25 | 2019-06-18 | 浙江大华技术股份有限公司 | Store equipment and method for managing resource |
| CN109901469A (en) * | 2019-03-12 | 2019-06-18 | 北京鼎实创新科技股份有限公司 | A method of PROFIBUS-PA bus communication is realized based on FPGA technology |
Non-Patent Citations (4)
| Title |
|---|
| "FPGA和ARM的Profibus-DP主站通信平台设计";孙倩华;《单片机与嵌入式系统应用》;20100228;第65-67页 * |
| "基于ARM与FPGA的PROFIBUS-DP智能主站设计与实现";李丽娜;《中国仪器仪表》;20111231;第80-83页 * |
| "基于FPGA的RPOFIBUS-DP从站IP软核的设计";莫太平;《计算机应用与软件》;20141031;第231-233页 * |
| 李丽娜."基于ARM与FPGA的PROFIBUS-DP智能主站设计与实现".《中国仪器仪表》.2011, * |
Also Published As
| Publication number | Publication date |
|---|---|
| CN110687854A (en) | 2020-01-14 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CA2019373C (en) | Interrupt structure for network interface circuit | |
| CN101957808B (en) | Communication method among various CPUs (Central Processing Units), system and CPU | |
| US20090129395A1 (en) | Method, communication network, and control unit for the cyclical transmission of data | |
| CN105117319A (en) | Method for realizing real-time monitoring of multi-channel MDIO (Management Data Input Output) devices based on FPGA | |
| JP2002149212A (en) | Redundant programmable controller for equalizing control data and equalization method | |
| CN115941102B (en) | Method for synchronous communication between controllers connected with MCU and FPGA by SPI | |
| CN112235127B (en) | Node fault reporting method and device, terminal equipment and storage medium | |
| CN112147927B (en) | Multi-axis motion control system for two-channel bus communication | |
| CN111108450B (en) | Circuit for coupling a field bus and a local bus | |
| US9208008B2 (en) | Method and apparatus for multi-chip reduced pin cross triggering to enhance debug experience | |
| US20130003754A1 (en) | Automation System | |
| KR20130111389A (en) | Communication system and method for debugging or programming one or more subscribers of the communication system | |
| CA2277560A1 (en) | Method of determining a uniform global view of the system status of a distributed computer network | |
| CN110687854B (en) | PA bus controller and PA bus control system | |
| CN110809002A (en) | Method for protocol conversion between robot and welding equipment and protocol conversion module | |
| WO2021136099A1 (en) | Data transmission method, apparatus, and device, and storage medium | |
| CN107992752B (en) | Data processing method and device and computer equipment | |
| CN106708701B (en) | Central maintenance device and method based on ARINC659 bus | |
| CN110430110B (en) | On-site bus gateway and protocol conversion method thereof | |
| RU2705421C1 (en) | Method of transmitting data over a bus, a communication system for realizing said method and an automatic protection device for preventing an emergency situation at a control object | |
| CN111737062B (en) | Backup processing method, device and system | |
| CN105591854A (en) | Interaction method, device and system based serial bus | |
| CN110784388A (en) | Debugging method of bus network | |
| US11757799B2 (en) | Line monitor device and network switch | |
| CN205486081U (en) | Embedded outside memory bus extension profinet bus device of CPU |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |