JP2002149212A - Redundant programmable controller for equalizing control data and equalization method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a programmable controller which has a mechanism for achieving equalization processing without disordering the fixed periodicity of a fixed-period task. SOLUTION: A task which performs equalization processing is divided into processing for gathering equalization data and processing for transmitting the gathered equalization data. The equalization data are transmitted to a standby- side CPU while divided into multiple equalization files. When the timing of the start of the fixed-period task is reached during the equalization processing, the fixed-period task is interposed. Frame No.s and serial No.s are put in the equated files to accurately perform the transmission and reception. An in- operation side CPU and a standby side CPU has the same transfer table and transfer systems for gathering and distribution are changed according to the arrangement of the data to be equalized.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an input / output control method in a programmable controller which is an industrial control device, and more particularly, to equalization of control data.

[0002]

2. Description of the Related Art At present, plants and factories use many programmable controllers (hereinafter, referred to as PCs) for sequence control of machines and devices to realize factory automation (FA).

FIG. 16 shows a general multi-CPU PC.
Here is an example. One PC is configured by connecting a plurality of CPU modules for executing programs, performing data arithmetic processing, and the like, a plurality of I / O modules for inputting and outputting process data to and from control devices, and a communication module (not shown).
These modules exchange data with each other via the system bus 101 and perform control processing of connected devices.

When the PC has a multi-CPU configuration including a plurality of CPU modules 102, each CPU module 10
2 operate individually. Therefore, in the input / output control method that has been conventionally performed, input / output processing for taking in process data from the I / O module 103 or the like by the CPU module 102 or outputting process data to the I / O module or the like is performed by each It is performed asynchronously between the CPU modules 102.

For this reason, processing using synchronized data is not performed between the CPU modules 102. Further, regarding the output of the process data to the I / O module 103, the output of the process data to the I / O module 103 is synchronized between the respective CPU modules 102 since each CPU module 102 outputs the output at its own timing. Not.

Each I / O module 103 outputs process data from a connected device in real time, and requires data from the CPU module 102 in real time. Therefore, when a plurality of CPU modules 102 perform processing in cooperation with each other,
If synchronization is not performed between tasks or tasks, different data may be recognized as the same data and processed.

In consideration of the above problems, it has been proposed that data can be exchanged synchronously between CPU modules or between tasks in multitask processing by Japanese Patent Application Laid-Open No. 11-338523 by the same applicant as the present application. No. "I / O control method in programmable controller" (hereinafter referred to as the prior application method).

In the method of the prior application, each CPU module 10
2, a tact interrupt is generated in the execution processor at a constant cycle at the same speed as the transfer speed of the system bus 101, and the execution processor in each CPU module 102 synchronizes with the generation cycle (tact cycle) of the tact interrupt. I /
By performing input / output processing with respect to the O module 103, synchronous processing between the CPU modules 102 is realized.

[0009]

Incidentally, in order to improve the reliability of the system, there is a case where the CPU module is provided with redundancy by using a duplex configuration. For example,
In the configuration of FIG.
102-3 is the operating side, and the CPU module 102-
2, 102-4 is the standby side. And C on the working side
When an error occurs in the PU module 102-1 or 101-3, the corresponding CPU module 102-2 or 1
CPU in which an error has occurred due to the switching of the operating state to 01-4
Acts instead of module 102.

In the case of such a duplex configuration, control data of the control data is sent from the active CPU modules 102-1, 102-3 to the standby CPU modules 102-2, 102-4 so that the processing can be taken over at the time of switching. Equalization is performed. In the configuration in which the PC transfers control data between CPU modules or IO modules in a specific cycle (tact cycle) as in the method of the prior application, and executes a task in synchronization with the tact cycle, When the equalization process is performed, there are the following problems. 1) FIG. 17 is a diagram showing the timing of the equalization processing.
As shown in the figure, when the equalization processing is performed by the method of the prior application, the system equalization processing is performed at the end of the default task (task end). While this equalization processing is being performed, the periodic task cannot perform processing, and waits for the CPU to become free. Therefore, if the time taken by the CPU for the equalization processing is long, the periodic task waits for the release of the CPU, and the periodicity of the processing is broken. 2) If the data for equalization processing stored in one frame is of a size that cannot be processed within one tact cycle, the tact cycle is extended. Therefore, the period of the fixed-period task executed in synchronization with the tact period also increases. 3) Since there is no information indicating the timing at which the equalized data is collected in the frame storing the data for the equalization processing, synchronization of the collected data cannot be guaranteed. 4) Although the synchronization of data collection for all frames must be guaranteed, if a normal frame is transmitted while data to be sent is being collected, indefinite data will be sent, and data synchronization will occur. I cannot guarantee it. 5) A transfer table is required for collecting the equalized data and distributing it to the application data area for each of the active CPU and the standby CPU, but a large amount of memory resources are required to prepare the transfer table. Consume it.

In view of the above problems, an object of the present invention is to provide a programmable controller having a mechanism for realizing equalization processing without breaking the periodicity of a periodic task, and an equalization method.

It is another object of the present invention to provide a programmable controller having a mechanism for preventing transmission of indefinite equalized data to a standby side and transmission of useless frames.

It is still another object of the present invention to provide a programmable controller having a mechanism for destroying data before distribution processing is completed with received data or distributing indefinite data to an application data area.

It is another object of the present invention to provide a programmable controller having a mechanism for effectively using resources and improving the performance of collecting and distributing equalized data. It is another object of the present invention to provide a programmable controller capable of performing control data equalization processing at high speed.

[0015]

In order to solve the above problems, a programmable controller according to the present invention has one or a plurality of sets of CPUs which are duplicated and have redundancy.
It is assumed that data equalization is performed between the active CPU and the standby CPU, and includes an equalized data collection unit, a periodic task execution unit, and an equalized data transmission unit.

[0016] The equalized data collecting means is provided by the operating side CP.
U collects data to be equalized. The equalized data transmitting means transmits the data collected by the equalized data collecting means to the standby CPU in an equalized frame.

The fixed-period task executing means, when it is time to start the fixed-period task during the collection processing by the equalized data collecting means, completes the data by the equalized data transmitting means after the completion of the collecting processing. The periodic task is executed before transmission starts.

With this configuration, the periodic task can be executed without waiting for the equalization process to be completed. Further, the equalized data transmitting means may be configured to transmit the data collected by the equalized data collecting means by dividing the data into a plurality of equalized frames. With this configuration, even if the amount of the equalized data is large, the cycle of the tact cycle is not broken. At this time, information for checking the consistency of the data in the equalized frame is stored in each equalized frame, and the information for checking the consistency of the equalized frame received by the standby CPU is checked. By distributing the equalized data only when the consistency is confirmed, only the equalized data with consistency is equalized.

Further, the equalized data collection means and the equalized data distribution means form a transfer method optimal for data transfer at the time of data collection and distribution based on the arrangement of data to be equalized. With such a configuration, high-speed equalization processing can be realized.

[0020]

FIG. 1 is a diagram showing the configuration of a PC according to this embodiment. The PC of the present embodiment has a network configuration in which a plurality of CPU modules 2, a plurality of I / O modules 3, and a communication module 4 are connected by a system bus 1 having a ring-type transmission topology. Each module connected to the system bus 1 is set with a station number for uniquely identifying each module as a communication station on the network. In addition, each CPU module 2
Is a one-to-one duplex configuration to provide redundancy. In FIG.
5 to the CPU 8 are standby sides that correspond one-to-one with each of the active sides.

For communication between modules, a module that performs data transmission transmits a frame on which a transmission destination is specified by a station number to the system bus 1. This frame circulates on the system bus 1 in a fixed direction, and each station on the system bus 1 sends the frame transmitted from the upstream station to the downstream station if it is not addressed to the own station, and sends the frame to the own station. If there is, take it in. As a result, the frame circulates on the system bus 1 in a certain direction.

In the present embodiment, the equalized data transmitted from the active CPU to the standby CPU is transferred by multicast data communication. Hereinafter, data transfer by the multicast method will be described.

In the multicast system, a free token for multicast communication is circulated on the system bus 1,
The station requesting the data transmission (the station where the transmission data to be output to the output device is prepared and the transmission permission setting of the transmission band is set) secures the free token and transmits the multicast frame instead. I do. The multicast frame circulates on the system bus 1, and the station on the network that has received the multicast frame relays and circulates it downstream, and fetches data based on the setting contents of the output data in the frame.

FIG. 2 is an explanatory diagram of communication by the multicast method. In the present embodiment, one of the stations of the system bus 1 is a ring master station, and the ring master station manages data transfer by the multicast method. In FIG. 2, Di indicates an input device in the I / O module 3, and Do indicates an output device.

In the multicast method, in addition to transmitting the equalized data from the active CPU module to the standby CPU module, the CPU module 2 outputs the data to the I / O module 3 to which the output device is connected. This is the data transfer method used when performing.

In the communication by the multicast method, first, a ring master station that manages only one network existing on the system bus 1 generates a free token for controlling the authority of data transfer and releases it on the system bus 1. . With the release of this free token,
Multicast communication is started.

The released free token is sequentially relayed by each station to downstream stations, and circulates on the system bus 1. CPU module 2 for which data is to be output
Receives this free token, secures it from the system bus 1 and becomes the master station.

The master station sends the prepared transmission data on the system bus 1 as a multicast frame in which data indicating that this frame is a multicast communication frame is set in the SD section. In FIG. 2, the master station replaces the held free token with Do1.
The output data for the two stations, the output data for the station (M-> Do1) and the output data for the Do2 station (M-> Do2), are output as multicast frames as the downstream station Do.
2 is sent.

The station that has received the multicast frame refers to the station number of the storage destination of the output data set in the output data in the frame, and if the output data is for its own station, fetches it. At the same time, the frame is directly transmitted to the downstream station. In FIG. 2, the Do2 station and Do1 station that have received the multicast frame respectively correspond to their own stations and output data (M->
Do2, M-> Do1), and the received frame is transmitted as it is to the adjacent downstream ring master station and master station.

When a frame makes one round, the master station that first transmitted the frame removes it from the system bus 1 and instead generates a free token and releases it on 1.

When the free token returns after making a round of the system bus 1, the ring master station checks the presence or absence of a data transmission request, and if so, transmits the transmission data. Thereafter, the ring master station removes the free token from the system bus 1 when the data frame transmitted by the own station returns to the own station after making a round of the system bus 1, thereby ending the multicast communication.

The data frame of the ring master station is always transmitted last on the system bus 1, not limited to the multicast communication. Next, an equalization process in the system according to the present embodiment will be described.

FIG. 3 shows an operating CPU in the present system.
FIG. 6 is a diagram showing a flow of equalized data between the CPU 11 and a standby CPU 12. FIG. 2 shows only a portion related to transmission and reception of the equalized data of the active CPU 11 and the standby CPU 12 corresponding to the active CPU 11. In the present embodiment, the equalized data is transmitted from the active CPU 11 to the standby CPU 12 via the system bus 1 by a multicast method.

The active CPU 11 performs a collection process as follows:
Only data requiring equalization is scanned from the application data area 14 and collected in the frame transmission / reception work area 15. Then, the collected equalized data is transmitted to the standby CPU 12 by a multicast method (a frame for transmitting the equalized data is hereinafter referred to as an equalized frame). At this time, if the number of equalized data is large and cannot be transmitted in one tact cycle, the data is divided into a plurality of frames and transmitted as described later. Frame transmission / reception area 15
Is divided into a plurality of frame areas, and each frame area is a place for storing data to be transmitted in one transmission frame. The active-side CPU 11 and the standby-side CPU 12 transmit the equalized data in a number of equalized frames by calculating an equalized frame size that can be transmitted in one tact cycle from the number of modules constituting the system at the time of initialization. Then, a corresponding area and a dummy area (the dummy area will be described later) are prepared in the frame transmission / reception work area 15.

The equalized data in the frame transmission / reception area 15 is stored in a multicast frame via the transmission buffer 17 in the bus controller 16 and transmitted on the system bus 1. The transmission pointer 18 moves to the next frame area every time data is transmitted with a pointer pointing to a frame area in which data to be transmitted next is stored.

The standby CPU 12 receives the multicast frame and stores it in the frame transmission / reception work area 15 via the reception buffer 19 in the bus controller 16 for each received frame. At this time, the storage position of the frame transmission / reception area 15 is pointed by the reception pointer 20, and the reception pointer 20 moves to the next frame area every time a frame is received. The equalized data stored in the frame transmission / reception work area 15 is stored in the application data area 1
4 is distributed and stored in such a manner that old equivalent data is overwritten. Then, when the standby CPU 12 is switched to the active side, the application program takes over the processing of the application program on the active side CPU 11 using the data in the application data area 14.

In the present system, a task for performing equalization processing (hereinafter, referred to as an equalization task) is divided into equalization data collection processing (equalization preparation) and transmission processing of equalization data. The collection processing is performed at the end of the task execution processing of the default task. Further, the equalized data transmission processing is performed independently of the task execution, and is performed in parallel with the periodic task. When the amount of the equalized data is large, the equalized data is divided into a plurality of frames and transmitted, and the transmission processing of each of the equalized frames is made independent. As described above, in the present embodiment, the equalization processing is divided into a plurality of fine processings, each of which is independent. Therefore, even if the periodic task has to be executed after the equalization process is started, the fixed-cycle task is divided between the subdivided processes without waiting for the equalization process to be completed. When the periodic task is completed, the process can return to the equalization process. With this configuration, even when the amount of the equalized data is large and the equalizing process takes a long time, the equalizing process can be performed without breaking the periodicity of the periodic task.

FIG. 4 is a timing chart showing the timing of collecting and transmitting the equalized data by the periodic task, the default task, and the equalization task. The vertical line in the figure indicates a tact interrupt, and one tact cycle is between tact interrupts. Each task process is divided into an IO data input process (shaded portion), an IO data output process (shaded portion), and a task execution process (solid portion) other than the input / output process such as a calculation process.

In FIG. 4, “default task end”, “default task start prohibition”, “default task O prohibition”, and “collection request” indicate changes in the status flags provided on the active CPU 11. The “transmission pointer” indicates which frame area the transmission pointer points to. "State of the Equalization Task"
Indicates the processing state of the task that performs the equalization processing.

The “default task end present” flag is a flag for creating a timing for collecting data to be equalized, and is set to “O” when the task execution processing of the default task ends.
It becomes N (1), and it becomes OFF (0) when the collection processing of the data to be equalized ends.

The "default task activation prohibition" flag is
This flag indicates the period during which the equalization processing is being performed. When the default task execution processing is completed and the “default task end present” flag is set to ON and a new tact cycle is entered, it is set to ON. When the transmission of the equalization data is completed and the equalization processing is completed, the signal is turned off. While this flag is ON, activation of the periodic task is permitted, but activation of the default task is prohibited.

The "default task O prohibition" flag is a flag that causes the start of output processing by the default task to wait until the equalization processing is completed. When the transmission of the frame is started, it becomes OFF. If this flag is O
After becoming FF, the default task starts IO data output processing.

The "collection request" is a flag indicating a period during which the task performing the equalization process can perform the collection process. The flag is turned on together with the "default task start prohibition" flag, and is turned off when the collection process is completed.

As shown at 41 in FIG. 4, the "default task end exists" flag is turned on in response to the end of the task execution processing of the default task. Thereby, the collection and transmission processing (system data processing) of the equalized data can be started. "Default task end"
When the flag is turned on, the “collection request flag” is turned on at the next tact interrupt. When the IO input processing of the periodic task is completed, the status of this “collection request flag” is
If so, the collection processing of the equalized data is started. When the collection process is completed, a process of transmitting the collected equalized data to the standby CPU is performed.

During the collection and transmission processing of the equalized data, the "default task O prohibition" flag is turned on to inhibit the output processing of the default task from interrupting the collection and transmission processing. However, during this period, the periodic task is permitted to be started by interrupting the processing. As a result, the periodic task can execute processing without breaking the periodicity.

Further, in this system, when the number of data to be equalized between the active CPU and the standby CPU is large and the amount of data to be transmitted to the standby CPU is large, within one tact cycle decided by the system. The equalized data is divided into a size that can be transmitted, these are divided into a plurality of equalized frames of a fixed size, stored, and transmitted one frame at a time in synchronization with the tact cycle. The portion 42 in FIG. 4 shows a case where the data is divided into N frames and the equalized data is transmitted.

FIG. 5 shows a configuration example of an equalization frame for transmitting the equalization data to the standby CPU. The equalized frame in FIG. 5 is a frame transmitted by the multicast method,
It is divided into a CPU multicast frame header part and a data part. Among them, the multicast frame header section between CPUs includes FC indicating the type of the frame, TS indicating the size of the frame, address SA of the own CPU module on the system bus 1, address DA of the standby CPU module which is the transmission destination, A size indicating the size of the equalized frame portion is stored. In the data part, in addition to the equalized data, the serial number and frame for checking the consistency of the equalized data in the received frame
No. is stored. This serial No. and frame N
o. will be described later.

The equalized frame has a fixed length, and has a size determined by the system from the maximum data size that can be transmitted within one tact cycle. FIG. 6 is a diagram illustrating data transmitted from the active CPU within one tact cycle. 1
In the tact period, in addition to the equalized data, system control data that is transmission data to other modules constituting the system such as the I / O module 3 and the communication module 4 is transmitted. The frames for transmitting the system control data include a control IO input / output frame including output data to the I / O module 3, a status frame including various statuses of the module, and a message frame including a message to the communication module.

The active CPU and the standby CPU variably control the number of equalized data to be stored in one frame in consideration of the maximum data size that can be transmitted within one tact cycle and the size of the system control data. . The active-side CPU and the standby-side CPU determine the size of the equalization frame from the type and number of modules constituting the system. Basically, the larger the system configuration, the more the frame can be transmitted in one frame. The value data size becomes smaller, and the smaller the system configuration is, the larger it becomes.

The size of the equalized data (the number of equalized data) that can be stored in the equalized frame is obtained from the number of system control data and the number of equalized data as shown in equation (1). Maximum data size that can be transmitted within one tact cycle = system control data size + equalized data size (1) In equation (1), the system control data size is the control IO of FIG.
The input / output data for the control I / O module 3 transmitted in the input / output frame, the status frame, and the message frame, the message data to the communication module 4, and the size of various statuses are added. Therefore,
The equalized data size is calculated from the data size of the largest frame that can be transferred in one tact cycle as shown in equation (2).
The system control data size is subtracted. Equalized data size = Maximum data size that can be transmitted within one tact cycle-System control data size ... (2) In the present embodiment, since the equalized data is divided into a plurality of frames and transmitted, this is received. A frame number and a serial number are inserted in the equalized frame for transmitting the equalized data so that the consistency of the received frame can be checked by the standby CPU.

FIG. 7 shows an example in which the equalized data is divided into three frames and transmitted. When the active CPU transmits a frame, and when the standby CPU receives a frame, the frame transmission / reception work area 15 is used. FIG. 3 is a diagram illustrating states of a transmission pointer 18 and a reception pointer 20.

In the active CPU, the equalized data collected by the collection processing is stored in the frame transmission / reception work area 15.
And stored in one frame area. Then, the data is sequentially stored in an equalized frame from the data in the frame area indicated by the transmission pointer 18 and transmitted. A frame number and a serial number are stored in these equalized frames, and x / y described in the system bus area of FIG.
Is the frame No. in each frame, and Ser.z is the serial No.
Is represented.

The frame No. is a number indicating the number of the equalized data divided into a plurality of parts. In FIG. 3, the number represented by x / y in FIG. Indicates the number of the data, and the x part indicates the number of the data. In the case of the figure, since the frame is divided into three frames, the frame No.
Takes a value of 1/3 to 3/3. This frame number is used by the standby CPU to check whether the equalized frame has arrived without being skipped.

The serial number indicates which equalization process the frame contains the equalized data. Each time the active CPU collects the equalized data, 1, 2,.・ The number is incremented. The serial number is used to guarantee the synchronization of the collected data, and the standby CPU uses the same serial number.
The frames marked with are recognized and processed as a part of the equalized data collected by the same processing.

When the collection processing is completed, the active CPU transmits the equalized data in the frame area indicated by the transmission pointer 18 in the frame transmission / reception work area 15 to the standby CPU by multicast transmission. At this time, the same serial number is stored in each of the equalized frames, and the frame numbers are set in the transmission order, for example, 1, 2,.
Is stored.

After the transmission of all the equalized data is completed, such as while collecting the equalized data from the application data area 14, until the next equalized data is transmitted, the operating CPU is equalized. A dummy frame containing no data is transmitted to the standby CPU. This dummy frame is set with a special number that is determined in advance as a serial number. When the standby CPU that has received the frame stores this number in the serial number of the received frame, this frame is identified. Recognize that the frame is a dummy frame. Then, the standby CPU receives the dummy frame,
The active CPU recognizes that transmission of all the equalized frames for transmitting the equalized data collected by one collection process has been completed. In the case of FIG. 7, 0 is stored as a serial number in the dummy frame.

The standby CPU distributes the equalized data to the application data area 14 only when all the equalized data transmitted by the operating CPU after being divided into a plurality of files are normally received. The consistency check of the received equalized data is performed based on the frame number and the serial number.

When the standby CPU receives the dummy frame, it determines that all the equalized data has been received, and matches the consistency of the equalized data received from the frame No. of all the equalized frames with the serial No. Find out. And if no problem,
The equalized data is distributed from the frame transmission / reception work area 15 to the application data area 14.

The standby CPU sends the frame number and the serial number of the equalized frame to be sent out by the active CPU and the frame number and the serial number of the actually received equalized frame. Compare. If they match, the data is distributed to the application data area 14. If they do not match, the received data is discarded because the frame has not arrived normally because the frame was lost due to a transmission error or the like.

In the case where the two coincide with each other at 71 in FIG. 7 and the received data is distributed to the application area 14 as the equalized data.
A case where the transmitted equalized data is discarded and the equalized data is not distributed to the application data area 14 is shown. In the case of FIG. 71, the serial numbers of the received equalized frames are all 1 and the frame numbers are 1/3 and 2
Since the order was / 3, 3/3, the received equalized data is distributed from the frame transmission / reception work area 15 to the application data area 14 as normal reception. Also 72
In the part, the received equalized frames include those with serial numbers 1 and 2, so the equalized data in these received frames is discarded without being distributed to the application data area 14.

Further, in order to guarantee synchronization of data collection of all frames, the active side CPU transmits all the equalized data until transmission of new equalized data is completed.
Transmit a dummy frame. If the equalized data is transmitted before the collection processing is completed, indefinite data will be sent. Therefore, the active CPU transmits the last equalized frame and then completes the next collection processing. During this period, the transmission pointer 18 is fixed to the dummy address which is the address of the dummy area, and the dummy frame is transmitted.

At this time, the standby CPU distributes the equalized data to the application data area 14, but the equalized data in the frame transmission / reception work area 15 is not overwritten by the data of the dummy frame. The reception pointer 20 is fixed at a dummy address in the frame transmission / reception work area 15 until this distribution processing is completed.
As a result, the received dummy frame is stored in the area where the equalized data indicated by the dummy address is not stored, and the frame transmission / reception work area 15 where the equalized data is stored.
Is not overwritten. When the distribution processing of the equalized data is completed, the reception pointer 20 is returned to the normal reception position of the equalized frame even if the received frame is a dummy frame. However, in this case, while the dummy frame is being received, the reception pointer 20 is not moved.

As shown at 73 in FIG.
U transmits a dummy frame to the standby CPU until the process of collecting the equalized data from the application data area 14 is completed. Since the special number 0, which is a predetermined number, is stored as a serial number in the dummy frame, the standby side C that has received the equalized frame has
The PU recognizes that this frame is a dummy frame by checking the serial number.

By transmitting the dummy frame, the active-side CPU causes the standby-side CPU to recognize that the active-side CPU has completed transmission of the equalized data and is preparing to transmit the next equalized data. . The data in the received frame is overwritten and stored in the frame transmission / reception work area 15, but during reception of the dummy frame, the data in the received dummy frame is overwritten in the same area by not moving the reception pointer 15. And store.

When transmitting the equalized data divided into a plurality of equalized frames, if the transmission error occurs during the transmission of the equalized frames in the middle, the operating CPU transmits the remaining frames. Stop. Then, the application data area 14 is immediately scanned to perform re-collection processing of the equalized data, and the equalization processing is continued. By stopping the transmission processing of the equalized data in which the transmission abnormality has occurred in this way, the processing of collecting new equalized data and the processing of transmitting the equalized data can be immediately started. FIG.
74, the first equalized frame (frame No.
Since a transmission error occurred during the transmission of a 1/3 frame, the subsequent frames (frame numbers of 2/3, 3/3)
Frame), and the collection process of the next equalized data is started. Until the re-collection processing of the equalized data is completed, the operating CPU transmits a dummy frame.

In this part 74, the timing of starting the collection processing and the processing by the periodic task overlap at the same time. In such a case, the IO input processing of the periodic task is performed first. After this is completed, the process of collecting the equalized data is performed, and thereafter, the process proceeds to the execution of the periodic task.

Next, the process of collecting the equalized data performed by the active CPU and the process of distributing the equalized data performed by the standby CPU will be described. Collection processing of equalized data from the application data area 14 to the frame transmission / reception work area 15 performed by the active CPU and the standby CPU
In the processing of distributing the equalized data from the frame transmission / reception work area 15 to the application data area 14 performed in the step (1), both the active CPU and the standby CPU use the same transfer table.

FIG. 8 shows a process of collecting the equalized data performed by the active CPU, and FIG. 9 shows a process of distributing the equalized data performed by the standby CPU. FIGS. 8 and 9 show an example in which the equalized data is divided into two equalized frames and transmitted. The frame transmission / reception work area 15 includes two frames to be transmitted and received in the multicast frame header section between the CPUs. A header section storing data and a data section storing data of the data section are shown.

In the process of collecting the equalized data performed by the operating CPU shown in FIG. 8, the equalized data is collected from the application data area 14 to the frame transmission / reception work area 15. This processing is performed in the application data area. The data of which position of the frame 14
The transfer table 3 which records where to collect in
0 is performed.

The transfer table 30 is created by the active CPU and the standby CPU by recognizing data to be equalized from an application program created by a user running on the CPU module when the CPU is initialized. . Since the same application program is installed in the active CPU and the corresponding standby CPU, the active CPU and the standby CP
In U, the equalization target data is the same, and the transfer method is also the same. Therefore, in the active CPU and the standby CPU,
Exactly the same transfer table 30 is created. The active CPU and the standby CPU implement both a transfer table for collecting equalized data and a transfer table for distribution to the application data area 14 in preparation for switching between operation and standby. Since collection and distribution can be performed using the transfer table, memory resources can be used effectively.

The transfer table 30 has the number of blocks N indicating how many frames to transmit the equalized data in,
The data transfer method between the application data area 14 and the frame transmission / reception work area 15 to be described later, the frame-side address indicating the number of blocks N of the frame transmission / reception work area 15 side, the number of data, and the application data area-side address are: It is recorded, and its configuration differs depending on the transfer method. When a plurality of transfer methods are performed in combination (for example, in FIG. 8, D1 to D5 are performed by block transfer, and D100 to D104 are performed by structure transfer), the transfer table 30 includes each transfer method. These pieces of information are recorded every time. In the collecting process of the equalized data performed by the active CPU, the equalized data is collected by using the address of the application data area of the transfer table 30 as the transfer source address and the frame side address as the transfer destination address.

The equalized data collected by the active CPU is stored in an equalized frame and transmitted to the standby CPU, and the standby CPU stores the received equalized frame in the frame transmission / reception work area 15. Then, the equalized data in the data section therein is distributed to the application data area 14 using the transfer table 30 as shown in FIG.

In this distribution processing, the transfer table 30 which is the same as the transfer table 30 used for the collection processing of the equalized data by the operating CPU is used in the reverse of the collection processing of FIG.
Data transfer is performed with the frame side address as the transmission source and the application data area side address as the transmission destination. As described above, by using the same transfer table 30 with the transfer source address and the transfer destination address reversed between the active CPU and the standby CPU, memory resources can be saved.

In the present embodiment, there are three transfer methods for transferring the equalized data between the application data area 14 and the frame transmission / reception work area 15: block transfer, word transfer, and structure-pair transfer. In the transfer table 30 used in each transfer method, the configuration of the address portion on the application data area side differs for each transfer method. The active CPU and the standby CPU select an optimal transfer method for data transfer at the time of data collection / distribution from the arrangement position of the application data area 14 for data to be equalized at the time of initialization, or as necessary. A corresponding transfer table 30 is created by combining a plurality of transfer methods.

FIG. 10 shows a configuration example of a transfer table used by the block transfer method. FIG. 11 and FIG.
FIG. 12 shows the case where the number of blocks N = 1, and when the number of blocks N is 2 or more, the transfer table 30 has a portion corresponding to the frame side address, the number, and the application data area side address for the number of blocks. become.

The block transfer method is a transfer method performed when all data in a certain area of the application data area 14 is equalized, and data is transferred in block units. In the transfer table of FIG. 10, the word number and the address of the set recorded in the number part as the application data area side address are recorded as a set.

At the time of block transfer, data corresponding to the number of words is transferred in block units from the address stored in the transfer table. For example, when the collection processing of the equalized data in FIG. 8 is performed by block transfer, the first address of D1 of the application data area 14 is stored in the address 1 of FIG. 10, and the total number of words of D1 is stored in the word number 1. The address 2 stores the start address of D2 of the application data area 14, and the word number 2 stores the total number of words of D2. During the process of collecting the equalized data, D
As 1, data is read from address 1 for one word, and stored in the address portion stored in the frame-side address of the frame transmission / reception work area 15. Next, as D2, data is read from address 2 for two words, and is stored after D1 of the frame transmission / reception work area 15 is stored. Thereafter, the same processing is performed for all addresses and the number of words recorded in the address part of the transfer table 30 on the application data area side.

In the distribution processing of the equalized data, data of one word is read from the position stored in the frame-side address of the frame transmission / reception work area 15 as D 1, and is read into the address 1 part of the application data area 14. Then, as the data D2, the data for two words is read from the continuation of reading the data D1 of the frame transmission / reception work area 15, and the read data is stored in the application data area
Is stored in the address 2 part. Thereafter, by performing the same processing for all data, the equalized data using the transfer table 30 can be distributed to the application data area 14.

Next, the word transfer system will be described. The word transfer method is a transfer method used when equalization is performed by controlling independently in units of one word. Data to be transferred is specified in the transfer table 30 in units of one word.

FIG. 11 shows a configuration example of a transfer table used by the word transfer method. In the transfer table of FIG. 11, the number of addresses recorded in the number portion in the address portion on the application data area side is recorded.

When collecting the equalized data by word transfer, one word is read from each address stored in the application data area side address portion of the application data area 14 and the frame side of the frame transmission / reception work area 15 is read out. The data is sequentially transferred to the part stored in the address. In the process of distributing the equalized data to the application data area 14, one word is sequentially read out from the address stored in the frame side address part of the frame transmission / reception work area 15, and is read out to the application data area side address part of the application data area 14. The data is transferred to the location of the stored address.

Next, structure transfer will be described. The structure transfer is a transfer method used when transferring data by specifying data at an irregular position, and has three types of modes.

FIG. 12 is a structural example of a transfer table used for structure transfer. In the transfer table of FIG. 12, one address is recorded in the number part in the address part on the application data area side. In the transfer method part, mode number 0 indicating which mode is used to transfer the structure
2 are recorded.

FIG. 13, FIG. 14 and FIG.
FIG. 6 is a diagram showing an example of the structure in FIGS. The word (R) in each figure is read from the application data area 14 as an equalization target, and the (M) portion is not set as an equalization target.

In the case of mode 1 with mode number 0, FIG.
As shown in (2), two words of the two-word structure are subjected to equalization. In the structure transfer of mode 1, for example, if the number is set to 3, 2 × 3 = 6 words of data consecutive from the address portion of the application data area side address are read and collected in the collection processing. At the time of the distribution process, data of 6 words read from the frame side address portion from the frame transmission / reception work area 15 is stored in the address value portion recorded in the above address.

In the case of mode 2 of mode number 1, FIG.
As shown in (1), data transfer is performed with the 3rd and 4th words of the 4-word structure as equalization targets. In this structure transfer in mode 2, if the number is set to 3, for example,
In the collection process, the data of the third, fourth, seventh and eighth words and the eleventh and twelfth words from the designated address portion of the application data area 14 are read and collected as equalized data. At the time of the distribution process, the 6-word data read from the position specified by the transfer table in the frame transmission / reception work area 15 is transferred to the third, fourth, and seventh words from the specified address in the application data area 14.
The data is stored at the positions of the 8th word and the 11th and 12th words.

In the case of mode 3 with mode number 2, as shown in FIG. 15, the first, second, fifth and sixth words of the eight-word structure are equalized. For example, if 2 is set for the number, the application data area 1
The data of the 1st, 2nd, 5th and 6th words and the 7th, 8th, 11th and 12th words from the designated address portion of No. 4 are read out and collected as equalized data. The 6-word data read from the position specified by (1), (2), (5), (6), and (7), (8), (11), and (12) words from the specified address in the application data area are stored.

As described above, according to the present embodiment, the optimum transfer method can be selected by combining the data to be equalized in the application data area 14, or a plurality of transfer methods can be combined. Collected in
The distribution process can be performed, and the control data can be equalized at high speed.

[0089]

As described above, according to the present invention, the equalizing process can be performed without breaking the periodicity of the periodic task performed by the active CPU.

Further, by transmitting the equalized data divided into a plurality of equalized frames, even if the amount of the equalized data is large, the cycle of the tact cycle is not broken. Furthermore, during the collection process, the active CPU does not transmit data before collection is completed by transmitting a dummy frame.

When a transmission error occurs during the transmission of a plurality of equalized frames, the subsequent transmission processing of the equalized data is stopped to collect new equalized data, and The transmission processing of the equalized data is immediately started.

Further, the standby CPU can check the consistency of the received equalized data. Further, the data being distributed is not overwritten by the data of the frame received during the distribution of the equalized data.

Further, by sharing the transfer table between the collection process and the distribution process, the memory resources can be made effective. Also, based on the arrangement of data to be equalized, select the optimal transfer method for data transfer during data collection and distribution,
By combining them as needed, high-speed equalization processing can be realized.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating a configuration of a PC according to an embodiment.

FIG. 2 is an explanatory diagram of communication by a multicast method.

FIG. 3 is a diagram showing a flow of equalized data between an active CPU and a standby CPU.

FIG. 4 is a timing chart showing timings of collecting and transmitting equalized data by a periodic task, a default task, and an equalization task.

FIG. 5 is a diagram illustrating a configuration example of an equalization frame.

FIG. 6 is a diagram showing data transmitted from an active CPU within one tact cycle.

FIG. 7 shows a state in which the active CPU transmits a frame and a standby C.
It is a figure which shows the state of the frame transmission / reception work area | region at the time of PU receiving a frame, and the transmission / reception pointer.

FIG. 8 is a diagram illustrating a process of collecting equalized data performed by an operating CPU.

FIG. 9 is a diagram illustrating a distribution process of equalized data performed by a standby CPU.

FIG. 10 is a diagram illustrating a configuration example of a transfer table used by a block transfer method.

FIG. 11 is a diagram illustrating a configuration example of a transfer table used by a word transfer method.

FIG. 12 is a diagram illustrating a configuration example of a transfer table used by a structure transfer method.

FIG. 13 is a diagram illustrating an example of a structure in mode 1;

FIG. 14 is a diagram illustrating an example of a structure of mode 2;

FIG. 15 is a diagram showing an example of a structure of mode 3;

FIG. 16 is a diagram illustrating an example of a PC having a general multi-CPU configuration.

FIG. 17 is a diagram showing the timing of the equalization processing.

[Explanation of symbols]

 1, 101 System bus 2, 102 CPU module 3, 103 I / O module 4 Communication module 11 Active CPU 12 Standby CPU 13 Executing processor 14 Application data area 15 Frame transmission / reception work area 16 Bus controller 17 Transmission buffer 18 Transmission pointer 19 Receive buffer 20 Receive pointer 30 Transfer table

Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat II (reference) G06F 13/42 350 G05B 19/05 SF term (reference) 5B034 BB02 DD06 5B077 AA17 AA18 BA03 BA09 FF01 GG02 GG16 5B083 AA05 CC04 CE01 DD08 GG09 5H209 EE11 GG04 GG11 HH37 HH40 SS01 SS04 SS08 5H220 BB10 CC09 CX03 EE07 EE10 HH04 JJ12 JJ16 JJ29 JJ38 KK01 KK03 MM08

Claims (13)

[Claims] 1. A programmable controller having one or a plurality of sets of CPUs, each of which has redundancy and has redundancy, and performs data equalization between an active CPU and a standby CPU, wherein: Is an equalization data collection unit that collects data to be equalized, and an equalization data transmission unit that transmits the data collected by the equalization data collection unit to the standby CPU by using an equalization frame. When it is time to start the periodic task during the collection process by the equalized data collection unit, the periodic task is started before the start of data transmission by the equalized data transmission unit after the collection process is completed. A programmable controller comprising: a fixed-period task executing unit that executes the task. 2. The programmable controller according to claim 1, wherein the equalized data transmitting unit transmits the data collected by the equalized data collecting unit by dividing the data into a plurality of equalized frames. . 3. The equalization data transmitting means adjusts the size of the equalization frame based on a configuration of a programmable controller.
4. The programmable controller according to 1. 4. The equalized data transmitting means stores information for checking consistency of data in the equalized frame in the equalized frame, and the standby-side CPU transmits the received equalized data. 4. The programmable memory according to claim 2, further comprising an equalized data distribution unit that checks information for checking the consistency of the frame and distributes the equalized data only when the consistency is confirmed. controller. 5. The information for checking the consistency includes a frame number indicating which data is equalized data by which collection processing and a serial number indicating the number of the equalized frame among the plurality of divided frames. The programmable controller according to claim 4, characterized in that: 6. The standby-side CPU transfers data in the equalized frame received while the equalized data distribution means distributes the data to a dummy area different from a storage area of the distributed data. 6. The programmable controller according to claim 4, further comprising a frame receiving unit for storing. 7. The equalized data transmitting means, after transmitting all the data collected by the equalized data collecting means, until the equalized data collecting means completes the next collection processing, the dummy data The programmable controller according to claim 1, wherein the programmable controller transmits a frame. 8. When the transmission error occurs during transmission of the equalized frame, the equalized frame transmitting means stops transmission of the remaining equalized frames, and transmits the same to the equalized data collecting means. The programmable controller according to any one of claims 2 to 7, which instructs the start of a collection process. 9. The apparatus according to claim 4, wherein said equalized data distribution means distributes data using the same transfer table as the transfer table used for data collection by said equalized data collection means. 9. The programmable controller according to any one of claims 1 to 8. 10. The equalization data collection means and the equalization data distribution means select a transfer method optimal for data transfer at the time of data collection and distribution based on the arrangement of data to be equalized. The programmable controller according to claim 4, wherein: 11. The programmable according to claim 1, wherein said equalized data collecting means determines the start timing of said collection processing based on the end timing of a default task. controller. 12. The equalization frame transmitting means, when the timing for starting the fixed-period task is reached while the equalization data transmitting unit is transmitting the equalization frame, transmits the equalization frame. 12. The programmable controller according to claim 1, wherein the fixed-cycle task is executed after completion and before transmission of a next equalized frame is started. 13. A method for equalizing data between an active CPU and a standby CPU in a programmable controller having one or more sets of CPUs provided with redundancy by redundancy. The active CPU collects the data to be equalized, transmits an equalized frame storing the collected data to the standby CPU, and it is time to start the periodic task during the collection. And performing the periodic task after the collection is completed and before transmitting the equalized frame.