CN108563598A - A kind of I from wake-up2C communication architecture systems - Google Patents
A kind of I from wake-up2C communication architecture systems Download PDFInfo
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- CN108563598A CN108563598A CN201810176187.9A CN201810176187A CN108563598A CN 108563598 A CN108563598 A CN 108563598A CN 201810176187 A CN201810176187 A CN 201810176187A CN 108563598 A CN108563598 A CN 108563598A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4004—Coupling between buses
- G06F13/4022—Coupling between buses using switching circuits, e.g. switching matrix, connection or expansion network
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4063—Device-to-bus coupling
- G06F13/4068—Electrical coupling
- G06F13/4072—Drivers or receivers
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F2213/0016—Inter-integrated circuit (I2C)
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Abstract
The present invention relates to electronic technology field more particularly to a kind of I from wake-up2C communication architecture systems, including：OSC circuits, the first Enable Pin are connect with an enable signal, are that one first pulse signal acts on lower startup OSC circuit output CLK signals, or closes OSC circuits under enable signal is the effect of one second pulse signal in enable signal；I2C protocol circuits start I under the action of enable signal is the first pulse signal2C protocol circuits, or in enable signal I is closed for the effect of the second pulse signal is lower2C protocol circuits；Self-detection circuit, with I2The serial time clock line signal end and serial data line signal end of C protocol circuits connect, for generating enable signal.The present invention realizes I by increasing a self-detection circuit2The real-time wake-up and suspend mode of C communications, in suspend mode, digital circuit remains off, and saves a large amount of unnecessary energy losses.
Description
Technical field
The present invention relates to electronic technology field more particularly to a kind of I2C communication architecture systems.
Background technology
I2C (Inter-Integrated Circuit) agreement is to communicate association by the plate grade that philip companies propose at first
View, is now widely used for the information exchange between chip and control, use scope is very wide.In I2In C frameworks, such as Fig. 1 institutes
In the network architecture shown, host and slave share an I2C buses, SCL (Serial Clock Line, serial time clock line),
SDA (Serial Data Line, serial data line) is pulled upward to common level by pull-up resistor respectively, and all devices pass through OD
(Open Drain, open-drain) drives I2C buses, and be a non-according to the interaction and control of certain protocol realization data
Chang Gaoxiao and widely used bus protocol.
Traditional I2In C protocol circuits, with reference to Fig. 2, I2C signal is transmitted using " start " and " stop " structure as agreement
Begin and end mark, the sequential relationship that centre passes through SDA and SCL according to agreement transmit information.Since all chips share one
Bus, does not know when other chips can open communication between each other, therefore all chips in bus must pass through digital electricity
Whether there is communication request in Lu Buting detection buses, this is also required to chip interior all the time simultaneously there will be a high-frequency clock electricity
Road is working, and to meet the promptness and validity of communication, consumes a large amount of unnecessary quiescent dissipations.
Invention content
For the I of the prior art2C protocol circuits need not stop to detect bus signals, the prodigious problem of quiescent dissipation, this hair
It is bright to provide a kind of I from wake-up2C communication architecture systems, concrete scheme are as follows：
A kind of I from wake-up2C communication architecture systems, including：
OSC circuits are equipped with the first Enable Pin and output terminal of clock, and first Enable Pin is connect with an enable signal, in
The enable signal is that the lower startup OSC circuits of one first pulse signal effect export CLK signal from the output terminal of clock,
Or the OSC circuits are closed for the effect of one second pulse signal is lower in the enable signal；
I2C protocol circuits are equipped with the second Enable Pin, clock signal terminal, serial time clock line signal end, serial data line signal
End, the clock signal terminal are connect with the output terminal of clock of the OSC circuits, and second Enable Pin connects with the enable signal
It connects, starts the I under the action of the enable signal is first pulse signal2C protocol circuits, or in the enabled letter
Number close the I for second pulse signal effect is lower2C protocol circuits；
Self-detection circuit, with the I2The serial time clock line signal end and serial data line signal end of C protocol circuits connect,
For generating the enable signal.
The I of the present invention2C communication architecture systems, the self-detection circuit include the first test section, first test section according to
Signal according to the serial time clock line signal end, which is the signal of high level and the serial data line signal end, to be produced when being failing edge
A raw high pulse signal is as commencing signal.
The I of the present invention2C communication architecture systems, the self-detection circuit include the second test section, second test section according to
Signal according to the serial time clock line signal end, which is the signal of high level and the serial data line signal end, to be produced when being rising edge
A raw high pulse signal is as end signal.
The I of the present invention2C communication architecture systems, the self-detection circuit include third test section, the third test section according to
According to the serial time clock line signal end and and the serial data line signal end simultaneously for low level signal and be more than setting time
When threshold value, a high pulse signal is generated as fault-signal.
The I of the present invention2C communication architecture systems, first test section include：
First phase inverter, is equipped with input terminal and output end, and the input terminal is connect with the serial data line signal end；
First D-latch is equipped with the first data signal end, the first D-latch Enable Pin, first the RESET input, first
Signal output end, first data signal end are connect with the serial time clock line signal end, the first D-latch Enable Pin
It is connect with the output end of first phase inverter, described first the RESET input connects a reset signal；
First monostable flipflop, be equipped with the first trigger signal input terminal and the first pulse signal output end, described first
Trigger signal input terminal is connect with first signal output end of first D-latch, first output of pulse signal
End exports the commencing signal.
The I of the present invention2C communication architecture systems, second test section include：
Second D-latch is equipped with the second data signal end, the second D-latch Enable Pin, second the RESET input, second
Signal output end, second data signal end are connect with the serial time clock line signal end, the second D-latch Enable Pin
It is connect with the serial data line signal end, described second the RESET input connects a reset signal；
Second monostable flipflop, be equipped with the second trigger signal input terminal and the second pulse signal output end, described second
Trigger signal input terminal is connect with the second signal output end of second D-latch, second output of pulse signal
End exports the end signal.
The I of the present invention2C communication architecture systems, the self-detection circuit includes enable signal generating unit, according to the beginning
Signal, the end signal, the fault-signal generate the enable signal.
The I of the present invention2C communication architecture systems, the enable signal generating unit is when there are the commencing signal, output one
High level signal starts the OSC circuits and the I as the enable signal2C protocol circuits；Or,
For the enable signal generating unit when there are the end signal, one low level signal of output is as the enabled letter
Number, close the OSC circuits and the I2C protocol circuits；Or,
For the enable signal generating unit when there are the fault-signal, one low level signal of output is as the enabled letter
Number, close the OSC circuits and the I2C protocol circuits.
The I of the present invention2C communication architecture systems, the enable signal generating unit use RS latch, the RS latch packet
It includes：
First NAND gate, be equipped with first input end, the second input terminal, the first output end, the first input end with it is described
Commencing signal connects；
Second NAND gate, is equipped with third input terminal, the 4th input terminal, the 5th input terminal, second output terminal, and the third is defeated
Enter end connection and connect first output end, the 4th input terminal connects the fault-signal, the 5th input terminal connection
The end signal is connected, the second output terminal connects second input terminal of first NAND gate；
First nor gate is equipped with the 6th input terminal, the 7th input terminal, third output end, the 6th input terminal connection institute
First output end of the first NAND gate is stated, the 7th input terminal connects a high level signal, and the third output end is defeated
Go out the enable signal.
The I of the present invention2C communication architecture systems, the setting time threshold value are no less than 500ms.
Advantageous effect：The present invention realizes I by increasing a self-detection circuit2The real-time wake-up and suspend mode of C communications, stop
Digital circuit remains off when dormancy, saves a large amount of unnecessary energy losses.
Description of the drawings
Fig. 1 is the I of the prior art2C network architecture schematic diagrams；
Fig. 2 is the timing diagram of the SDA and SCL of the prior art；
Fig. 3 is the system structure diagram of the present invention；
Fig. 4 is a kind of specific embodiment schematic diagram of the first test section of the present invention；
Fig. 5 is a kind of specific embodiment schematic diagram of the second test section of the present invention；
Fig. 6 is a kind of specific embodiment schematic diagram of the enable signal generating unit of the present invention.
Specific implementation mode
Following will be combined with the drawings in the embodiments of the present invention, and technical solution in the embodiment of the present invention carries out clear, complete
Site preparation describes, it is clear that described embodiments are only a part of the embodiments of the present invention, instead of all the embodiments.It is based on
Embodiment in the present invention, those of ordinary skill in the art obtained under the premise of not making creative work it is all its
His embodiment, shall fall within the protection scope of the present invention.
It should be noted that in the absence of conflict, the feature in embodiment and embodiment in the present invention can phase
Mutually combination.
The invention will be further described in the following with reference to the drawings and specific embodiments, but not as limiting to the invention.
I shown in Fig. 22In the data transmission sequence diagram of C buses, show that identification starts or restart condition
(Recognize START or REPEATED START Condition) generates ACK answer signals (Generate
ACKNOWLEDGE Signal), from the ACK answer signals (Acknowledgement Signal From Slave) of equipment, know
Other end signal restarts condition (Recognize Stop or Repeated START Condition), is processing terminal
And it drags down SCL and is inserted into the stand-by period (Clock Line Held Low While Interrupts are Serviced).
It is a kind of from the I waken up with reference to Fig. 32C communication architecture systems, including：
OSC circuits 1, are equipped with the first Enable Pin and output terminal of clock, and the first Enable Pin connects with an enable signal EN_digi
It connects, is that the lower OSC circuits 1 that start of one first pulse signal effect export CLK letters from output terminal of clock in enable signal EN_digi
Number, or in enable signal EN_digi OSC circuits 1 are closed for the effect of one second pulse signal is lower；
I2C protocol circuits 2 are equipped with the second Enable Pin, clock signal terminal, serial time clock line signal end SCL, serial data line
Signal end SDA, clock signal terminal are connect with the output terminal of clock of OSC circuits 1, and the second Enable Pin connects with enable signal EN_digi
It connects, starts I under the action of enable signal EN_digi is the first pulse signal2C protocol circuits 2, or in enable signal EN_
Digi, which is that the effect of the second pulse signal is lower, closes I2C protocol circuits 2；
Self-detection circuit 3, with I2The serial time clock line signal end SCL and serial data line signal end SDA of C protocol circuits 2
Connection, for generating enable signal EN_digi.
In I2Inside C protocol specifications when SCL is high level, the failing edge of SDA signal defines the beginning of agreement；SDA
The rising edge of signal defines the end of agreement；The present invention utilizes the two distinctive signals, by increasing a self-detection circuit
Realize I2The real-time wake-up and suspend mode of C communications, in suspend mode, digital circuit remains off, and is not influencing I2The condition of C communications
Under, reduce the quiescent dissipation of system.
OSC (oscillator) circuit of the present invention is pierce circuit.
The I of the present invention2C communication architecture systems, with reference to Fig. 3, self-detection circuit 3 includes the first test section 31, the first detection
Portion 31 is failing edge according to the signal that the signal of serial time clock line signal end SCL is high level and serial data line signal end SDA
When generate a high pulse signal as commencing signal.
As a kind of specific embodiment of the present invention, with reference to Fig. 4, the first test section 31 includes：
First phase inverter 311, is equipped with input terminal and output end, and input terminal is connect with serial data line signal end SDA；
First D-latch 312 is equipped with the first data signal end D, the first D-latch Enable Pin CP, first the RESET input
CDN, the first signal output end Q, the first data signal end D are connect with serial time clock line signal end SCL, and the first D-latch is enabled
End is connect with the output end of the first phase inverter 311, first the RESET input CDN connections, one reset signal resetn；
First monostable flipflop 313 is equipped with the first trigger signal input terminal IN and the first pulse signal output end OUT,
First trigger signal input terminal IN connect Q, the first pulse signal output end with the first signal output end of the first D-latch 312
OUT exports commencing signal start_digi.
Those skilled in the art are also an option that other circuits to replace above-described embodiment to realize same purpose.
The I of the present invention2C communication architecture systems, self-detection circuit 3 include the second test section 32,32 foundation of the second test section
The signal of serial time clock line signal end SCL, which is the signal of high level and serial data line signal end SDA, generates one when being rising edge
High pulse signal is as end signal stop_digi.
As a kind of specific embodiment of the present invention, with reference to Fig. 5, the second test section 32 includes,
Second D-latch 321 is equipped with the second data signal end D, the second D-latch Enable Pin CP, second the RESET input
CDN, second signal output end Q, the second data signal end D are connect with serial time clock line signal end SCL, and the second D-latch is enabled
End CP is connect with serial data line signal end SDA, second the RESET input CDN connections, one reset signal resetn；
Second monostable flipflop 322 is equipped with the second trigger signal input terminal IN and the second pulse signal output end OUT,
Second trigger signal input terminal IN is connect with the second signal output end Q of the second D-latch 322, the second pulse signal output end
OUT end of output signals stop_digi.
The I of the present invention2C communication architecture systems, self-detection circuit 3 include third test section 33,33 foundation of third test section
Serial time clock line signal end SCL and and serial data line signal end SDA simultaneously for low level signal and be more than setting time threshold value
When, a high pulse signal is generated as fault-signal I2C_error.
Judge I when judgement is high level and is more than setting time threshold value2C bus failures, also into suspend mode
Save system power dissipation.
The I of the present invention2C communication architecture systems preferably set time threshold and are no less than 500ms, can prevent from judging by accident.
The I of the present invention2C communication architecture systems, self-detection circuit 3 includes enable signal generating unit 34, according to commencing signal
Start_digi, end signal stop_digi, fault-signal I2C_error generate enable signal EN_digi.
The I of the present invention2C communication architecture systems, enable signal generating unit 34 are defeated when there are commencing signal start_digi
Go out a high level signal as enable signal EN_digi, starts OSC circuits 1 and I2C protocol circuits 2；Or,
For enable signal generating unit 34 when there are end signal stop_digi, one low level signal of output is as enabled letter
Number EN_digi closes OSC circuits 1 and I2C protocol circuits 2；Or,
For enable signal generating unit 34 when there are fault-signal I2C_error, one low level signal of output is as enabled letter
Number EN_digi closes OSC circuits 1 and I2C protocol circuits 2.
Under starting state of the present invention, OSC circuits start within 100ns and export stable CLK signal, under closed state
System power dissipation is saved into suspend mode.The first above-mentioned pulse signal is high level signal, and the second pulse signal signal is
Low level signal.
A kind of specific embodiment, with reference to Fig. 6, enable signal generating unit 34 includes using RS latch, RS latch：
First NAND gate I21 is equipped with first input end, the second input terminal, the first output end, first input end and starts letter
Number start_digi connections；
Second NAND gate I22, is equipped with third input terminal, the 4th input terminal, the 5th input terminal, second output terminal, and third is defeated
Enter end connection the first output end of connection, the 4th input terminal connecting fault signal I2C_error, the connection connection of the 5th input terminal terminates
Signal stop_digi, second output terminal connect the second input terminal of the first NAND gate I21；
First nor gate I20 is equipped with the 6th input terminal, the 7th input terminal, third output end, the 6th input terminal connection first
The first output end of NAND gate I21, the 7th input terminal connect a high level signal, and third output end exports enable signal EN_
digi。
OSC circuits, the I of the present invention2C protocol circuits, phase inverter, D-latch, monostable flipflop, logic gates etc.
It is respectively equipped with a high power supply voltage end AVDD and low supply voltage end AVSS.
The foregoing is merely preferred embodiments of the present invention, are not intended to limit embodiments of the present invention and protection model
It encloses, to those skilled in the art, should can appreciate that all with made by description of the invention and diagramatic content
Equivalent replacement and obviously change obtained scheme, should all be included within the scope of the present invention.
Claims (10)
1. a kind of from the I waken up2C communication architecture systems, which is characterized in that including：
OSC circuits are equipped with the first Enable Pin and output terminal of clock, and first Enable Pin is connect with an enable signal, in described
Enable signal, which is that the effect of one first pulse signal is lower, starts the OSC circuits from output terminal of clock output CLK signal, or in
The enable signal, which is that the effect of one second pulse signal is lower, closes the OSC circuits；
I2C protocol circuits are equipped with the second Enable Pin, clock signal terminal, serial time clock line signal end, serial data line signal end, institute
Clock signal terminal to be stated to connect with the output terminal of clock of the OSC circuits, second Enable Pin is connect with the enable signal, in
The enable signal be first pulse signal under the action of start the I2C protocol circuits, or be in the enable signal
The second pulse signal effect is lower to close the I2C protocol circuits；
Self-detection circuit, with the I2The serial time clock line signal end and serial data line signal end of C protocol circuits connect, and are used for
Generate the enable signal.
2. I according to claim 12C communication architecture systems, which is characterized in that the self-detection circuit includes the first detection
Portion, first test section are high level and the serial data line signal end according to the signal of the serial time clock line signal end
Signal be failing edge when generate a high pulse signal as commencing signal.
3. I according to claim 22C communication architecture systems, which is characterized in that the self-detection circuit includes the second detection
Portion, second test section are high level and the serial data line signal end according to the signal of the serial time clock line signal end
Signal be rising edge when generate a high pulse signal as end signal.
4. I according to claim 32C communication architecture systems, which is characterized in that the self-detection circuit includes third detection
Portion, the third test section according to the serial time clock line signal end and and the serial data line signal end simultaneously be low level
Signal and more than setting time threshold value when, generate a high pulse signal as fault-signal.
5. I according to claim 22C communication architecture systems, which is characterized in that first test section includes：
First phase inverter, is equipped with input terminal and output end, and the input terminal is connect with the serial data line signal end；
First D-latch is equipped with the first data signal end, the first D-latch Enable Pin, first the RESET input, the first signal
Output end, first data signal end are connect with the serial time clock line signal end, the first D-latch Enable Pin and institute
The output end connection of the first phase inverter is stated, described first the RESET input connects a reset signal；
First monostable flipflop is equipped with the first trigger signal input terminal and the first pulse signal output end, first triggering
Signal input part is connect with first signal output end of first D-latch, and first pulse signal output end is defeated
Go out the commencing signal.
6. I according to claim 32C communication architecture systems, which is characterized in that second test section includes：
Second D-latch is equipped with the second data signal end, the second D-latch Enable Pin, second the RESET input, second signal
Output end, second data signal end are connect with the serial time clock line signal end, the second D-latch Enable Pin and institute
The connection of serial data line signal end is stated, described second the RESET input connects a reset signal；
Second monostable flipflop is equipped with the second trigger signal input terminal and the second pulse signal output end, second triggering
Signal input part is connect with the second signal output end of second D-latch, and second pulse signal output end is defeated
Go out the end signal.
7. I according to claim 12C communication architecture systems, which is characterized in that the self-detection circuit includes enable signal
Generating unit generates the enable signal according to the commencing signal, the end signal, the fault-signal.
8. I according to claim 42C communication architecture systems, which is characterized in that
The enable signal generating unit when there are the commencing signal, one high level signal of output as the enable signal,
Start the OSC circuits and the I2C protocol circuits；Or,
The enable signal generating unit when there are the end signal, one low level signal of output as the enable signal,
Close the OSC circuits and the I2C protocol circuits；Or,
The enable signal generating unit when there are the fault-signal, one low level signal of output as the enable signal,
Close the OSC circuits and the I2C protocol circuits.
9. I according to claim 82C communication architecture systems, which is characterized in that the enable signal generating unit is locked using RS
Storage, the RS latch include：
First NAND gate is equipped with first input end, the second input terminal, the first output end, the first input end and the beginning
Signal connects；
Second NAND gate is equipped with third input terminal, the 4th input terminal, the 5th input terminal, second output terminal, the third input terminal
Connection connects first output end, and the 4th input terminal connects the fault-signal, the 5th input terminal connection connection
The end signal, the second output terminal connect second input terminal of first NAND gate；
First nor gate, is equipped with the 6th input terminal, the 7th input terminal, third output end, the 6th input terminal connection described the
First output end of one NAND gate, the 7th input terminal connect a high level signal, and the third output end exports institute
State enable signal.
10. I according to claim 42C communication architecture systems, which is characterized in that the setting time threshold value is no less than
500ms。
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| CN111382018A (en) * | 2018-12-29 | 2020-07-07 | 上海复控华龙微系统技术有限公司 | Fault detection method and device for serial communication and readable storage medium |
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| CN101937420A (en) * | 2009-06-29 | 2011-01-05 | 龙迅半导体科技(合肥)有限公司 | Low power consumption design for chip configuration register module |
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| CN111382018A (en) * | 2018-12-29 | 2020-07-07 | 上海复控华龙微系统技术有限公司 | Fault detection method and device for serial communication and readable storage medium |
| CN109884612A (en) * | 2019-03-07 | 2019-06-14 | 南京大学 | A kind of burst length compression method of multi-channel single photon avalanche diode detector |
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