CN100504831C - Method and apparatus for recovering I2C bus locked by slave device - Google Patents
Method and apparatus for recovering I2C bus locked by slave device Download PDFInfo
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- CN100504831C CN100504831C CNB2007100768336A CN200710076833A CN100504831C CN 100504831 C CN100504831 C CN 100504831C CN B2007100768336 A CNB2007100768336 A CN B2007100768336A CN 200710076833 A CN200710076833 A CN 200710076833A CN 100504831 C CN100504831 C CN 100504831C
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Abstract
The present invention relates to a resume device and a resume method when the I2C bus is locked by slave I2C components. The resume method when the I2C bus is locked by the I2C slave components is that using main I2C components to control the work power source of all the slave I2C components, when the main I2C components detects that the bus is locked, then the main I2C components cut off the work power source of the slave I2C components, and resume the power supply after a set time, and then the slave I2C components resume the initial state. The resume device includes main I2C components, slave I2C components and system power source, and a power source switch is also added, one end of the power source connects with the system power source, and the other end of the power source connects with the slave I2C components power sources which are connected together, and the main I2C components control the on-off of the poser source switch. With the participation of the main CPU, the resume problem of the bus after the slave I2C components lock the bus is solved, and the stability and the reliability of the system are improved.
Description
Technical field
The present invention relates to restoration methods and device after a kind of I2C bus is locked from device by I2C, belong to computing machine communication neck.
Background technology
I2C bus (Inter-IC BUS or IIC BUS, interconnect bus between integrated circuit) is an a kind of cover universal serial bus by the exploitation of Philip (PHILIPS) company, is used to connect microcontroller and peripherals thereof.The I2C bus has two signal wires: a clock line SCL, a bidirectional data line SDA.All clock line SCL that receive the device on the I2C bus all receive the SCL of bus, and its data line SDA is connected to the bidirectional data line sda line of bus.Bus uses software addressing to discern each device (as microcontroller, storer, lcd driver, clock chip and other I2C bus devices), has saved the chip select line of each device fully, thereby has made the wiring of system very simple.I2C has become important global industrywide standard at present, is admitted and uses by all main IC manufacturers.In computer network communication equipment, the device application with I2C bus interface is also more and more.In the I2C bus, when certain device generated the clock signal SCK on bus and initiates data transmission, the main device of being known as (also being transmitter), certain device during receiving control information, were called as from device (also being receiver) on bus.Main device is used to start bus, produces clock and transmits data, and this moment, any device that is addressed all was considered to from device.
During the work of I2C bus, SCL provides the clock sync signal pulse by the control of the main device on bus clock line, finishes data by bidirectional data line SDA and transmits.The data transfer rate of I2C bus is 100kbit/s under the standard operation mode, and under immediate mode, the highest transfer rate can reach 400kbit/s.In the I2C bussing technique standard, bus protocol has strict sequential requirement.
The data transfer format of I2C bus is: behind I2C bus commencing signal, first byte data of sending is address and the indication read-write operation that is used for selecting from device, wherein before 7bit be address code, 8bit is read-write zone bit (R/W).Zone bit for " 0 " expression be main device " writing " operation, promptly main device information be written to institute's addressing from device; Zone bit is " reading " operation of " 1 " expression main device.Behind the commencing signal, each device in the system compares oneself address and the address delivered on the bus of main device, if it is consistent with the address that main device sends on the bus, then this device is by the device of main device addressing, and its reception information still sends information and then determined by 8bit sign (R/W).The data word joint number of each transmission is unrestricted on the I2C bus, but each byte is necessary for 8, and the byte back of each transmission (the 9th), must follow an authorization bit from device, also is response bits (ACK, Acknowledge bit).
The operating rate of I2C bus generally is to depend on main device and from the performance of device, with reference to the bus specification of I2C, the frequency of operation of clock line SCL can be operated in 0Hz between the 100kHz.
In the I2C bussing technique standard, beginning and end signal (also claiming the initial sum stop signal) and answer signal are defined as follows:
Start signal (S): keep between high period at clock line SCL, the last appearance of bidirectional data line SDA to low level variation, is used to start the I2C bus by high level, is the start signal of I2C bus;
Stop signal (P): keep between high period at clock line SCL, bidirectional data line SDA goes up and occurs being used to stop the I2C bus by the variation of low level to high level, is the termination signal of I2C bus;
Answer signal (A): the 9th of each byte the SCL pulse correspondence response bits in I2C bus transfer process, if bidirectional data line SDA go up to show low level and then " reply (A) " for bus,, bidirectional data line SDA shows that high level then is bus " non-replying (/A) " if going up.
Because of having only main device to realize management and to detect, so commencing signal and end signal generally all are to be produced by main device to the I2C bus.During the transmission of I2C bus data, be between high period at clock line SCL, must maintain stable logic level state on the data line SDA, high level is represented data 1, and low level is represented data 0.Only when clock line SCL is low level, just allow the level state on the data line SDA to change.
Itself can not lock the I2C bus, if but exist interference or SDA or SCL to be pulled into low level on the bus by some specific factor, the I2C bus just produces locking, these situations are normally because external disturbance and cause from the inefficacy and the fault of device, generally speaking, when Printed Circuit Board Design,, be to avoid because of occurring disturbing the locking that causes bus on the bus through careful placement-and-routing.
In the computing machine communication apparatus, the main device on the I2C bus generally is CPU, is other device that is connected on the I2C bus from device, such as storer, sensor, real-time clock etc.If sda line is pulled into low level by a device on the bus, main device just can not produce initial, stop signal, carry out next step transmission, for example, main device (CPU) to I2C during the read operation of device, if CPU is reset suddenly (RESET), and a read operation cycle on this moment I2C bus does not also finish, I2C is from the device input pin that generally do not reset, also can't know the situation that main device is reset, see just that from device the SCL of bus stops to change, but the I2C bus allows clock line SCL to stop, and therefore can not think also that from device the main device of I2C bus breaks down.In the cpu reset process and after resetting, SCL often by on move high level to, keep stable, according to the standard of I2C bus, the data on the SDA data line must be stable between clock line SCL high period, if be " low " just at the right time at the bit that SDA exports this moment from device, therefore, will drive sda line all the time from device is low level, makes main device can't produce any initial, stop signal, thereby, cause the locking of I2C bus by from device locking sda line.Though this moment, main device generally can detect I2C bus appearance locking, can't realize next step data transmission, therefore must avoid occurring causing in such cases the fault of I2C bus by certain means.
After this situation occurs, if main device can be controlled SCK separately, can be by sending several SCK pulses, make from device and finish read operation cycle on the I2C bus, thereby avoid the locking of I2C bus, still, many CPU (main device) are arranged, its inner integrated I2C register does not generally provide direct control to SCK, therefore, can't adopt the way of output SCK pulse to solve.If the I2C bus generally can't only solve by (RESET) main device that resets after being locked by above-mentioned reason,, must re-power and to solve if there is not other suitable reliable solution.
Solution for the I2C bus after locked, different devices provides solution route separately.
MPC8541, MPC8560 series CPU in FreeScale company (U.S.'s one tame chip companies) the PowerPC processor, its inner integrated I2C bus control register, after finding that the I2C bus is locked, can make the I2C bus withdraw from lock-out state by reading and writing a series of I2C bus control register.
The MAX7500 series I2C of MAXIM company (U.S.'s one tame chip companies) is from device, and timeout feature that it is inner integrated provides the locking protection of I2C bus.If SCL does not change at 250ms internal clock line, the I2C that will finish this from device automatically operates, and gets back to original state, thereby has avoided from the locking of device to the I2C bus;
But, the device that connects on the I2C bus in the computing machine communication apparatus is often many, I2C main device (generally being CPU) not necessarily has the control register that solves I2C lock bus state, simultaneously, at present all on the I2C bus also can not all possess the function that withdraws from lock-out state automatically from device, therefore, must the design attachment device, avoid the aforementioned I2C bus may blocked problem.
Summary of the invention
Technical matters to be solved by this invention is, not necessarily has the control register that solves I2C lock bus state at present I2C main device, simultaneously on the I2C bus all from device also can not all possess the shortcoming that withdraws from the lock-out state function automatically and according to the I2C bus to it from the characteristics that device has control and detects, provide a kind of I2C bus to provide a kind of I2C bus by the recovery device after the device locking by the restoration methods after the device locking and on the basis of this method.
I2C bus of the present invention by the restoration methods after the device locking is: control the working power of all I2C from device with the I2C main device, when the I2C main device detects bus when locked, promptly disconnect the working power of I2C from device, restore electricity again after waiting for setting-up time, make I2C return to original state from device.
Described setting-up time span is 0.2 second～5 seconds.
I2C bus of the present invention is comprised that by the recovery device after the device locking I2C main device, I2C are from device and system power supply, also increased a power switch, described power switch one end links to each other with system power supply, one end links to each other from device power source with the I2C that links together, and controls its break-make by the I2C main device.
Described power switch is a relay.
Described power switch is a metal oxide semiconductor field effect tube.
Described power switch is controlled its break-make by the GPIO pin of I2C main device.
Described power switch is controlled its break-make by the I2C main device by outside programmable logic device (PLD).
Described power switch is controlled its break-make by the I2C main device by the outer lock storage.
Method and apparatus of the present invention by the participation of host CPU, has solved the recovery problem of bus when I2C causes the locking of bus from device after, has improved the stability and the reliability of system, and this present invention implements convenient, flexiblely, and hardware cost is low.
Description of drawings
Fig. 1 is the method for the invention process flow diagram;
Fig. 2 is the theory diagram of device of the present invention.
Embodiment
Be described in further detail below in conjunction with the enforcement of accompanying drawing technical scheme:
Shown in Figure 1 is the process flow diagram of the method for the invention, after system powers on, when the I2C main device detects the I2C bus by after the device locking, automatic cutout I2C is from the working power of device, restore electricity after waiting for setting-up time, this moment, I2C promptly returned to original state from device, thereby had solved from the locking of device to bus again, the length of above-mentioned setting-up time depends on the load size of I2C bus and the performance of I2C main device, and its span is 0.2 second～5 seconds.
Shown in Figure 2 is that I2C bus of the present invention is by a theory diagram of the recovery device after the device locking.Label be 201 be main device on the I2C bus, be the CPU processor in the present embodiment; Label be 202 be in the I2C bus from device, generally have a plurality ofly on the I2C bus from device, but only illustrate from device in the present embodiment with one; Label be 203 be to be used for I2C is controlled power switch from the working power of device, power switch 203 1 ends link to each other with system power supply, an end links to each other from device power source with the I2C that links together; 204 are used for controlling power switch 203, and for the CPU that general input and output (GPIO) arranged, 204 are one of them GPIO pin; For the CPU that does not have the GPIO pin, can realize that also can realize by the latch that adds, promptly CPU can realize control to power switch 203 by the register of PLD inside by outside programmable logic device (PLD) (PLD).By power switch 203 and 204 collaborative works, can realize that the main device of I2C is controlled from the working power of device I2C, solve the situation of I2C from device locking bus.
This device is system design, principle diagram design stage of (veneer) in the unit, can link together all I2C from the working power of device, and the I2C that links together is connected with the power supply of system by a power switch from the device working power.The fundamental purpose of power switch is that I2C is carried out break-make from the working power of device, and (MetalOxide SemicoductorField Effect Transistor MOSFET) realizes can to pass through relay or metal oxide semiconductor field effect tube.To the control of power switch, consider according to its type, if relay will be considered the realization of drive current; If MOSFET will consider to control control and the realization of voltage Vgs; Also can adopt the power switch of alternate manner, as long as can realize break-make by CPU control power switch.
CPU201 in this enforcement block diagram has the GPIO pin, and power switch 203 adopted N channel depletion type MOSFET, when GPIO is output as ' 1 ', and the MOSFET conducting, when GPIO was output as ' 0 ', MOSFET ended.In the application of reality, after system powered on, CPU201 normally started, and GPIO is output as ' 1 ', power switch 203 closures, and I2C is from device 202 operate as normal.When CPU201 detects bus by I2C during from device 202 locking, the output that is about to GPIO is adjusted into ' 0 ', control power switch 103 disconnects, this moment, I2C was from device 202 power supply of losing the job, all I2C will be de-energized from device, CPU is according to the demand of system, keep GPIO ' 0 ' output after 0.2 millisecond～5 seconds, again the output with GPIO is adjusted into ' 1 ', control power switch closure, I2C reconnects from the power supply and the system power supply of device, and this moment, all I2C can be in state behind the electrification reset from device, had promptly solved the situation of I2C from device locking bus.
Claims (8)
1, a kind of I2C bus is by the restoration methods after the device locking, it is characterized in that, control the working power of all I2C with the I2C main device from device, when the I2C main device detects bus when locked, promptly disconnect the working power of I2C from device, restore electricity again after waiting for setting-up time, make I2C return to original state from device.
2, I2C bus as claimed in claim 1 be is characterized in that by the restoration methods after the device locking described setting-up time span is 0.2 second～5 seconds.
3, a kind of I2C bus is by the recovery device after the device locking, comprise that I2C main device, I2C are from device and system power supply, it is characterized in that, also increased a power switch, described power switch one end links to each other with system power supply, one end links to each other from device power source with the I2C that links together, and controls its break-make by the I2C main device.
4, I2C bus as claimed in claim 3 be is characterized in that by the recovery device after the device locking described power switch is a relay.
5, I2C bus as claimed in claim 3 be is characterized in that by the recovery device after the device locking described power switch is a metal oxide semiconductor field effect tube.
6, I2C bus as claimed in claim 3 be is characterized in that by the recovery device after the device locking described power switch is controlled its break-make by the general input and output pin of I2C main device.
7, I2C bus as claimed in claim 3 be is characterized in that by the recovery device after the device locking described power switch is controlled its break-make by the I2C main device by outside programmable logic device (PLD).
8, I2C bus as claimed in claim 3 be is characterized in that by the recovery device after the device locking described power switch is controlled its break-make by the I2C main device by the outer lock storage.
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| Application Number | Priority Date | Filing Date | Title |
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| CNB2007100768336A CN100504831C (en) | 2007-08-31 | 2007-08-31 | Method and apparatus for recovering I2C bus locked by slave device |
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| CNB2007100768336A CN100504831C (en) | 2007-08-31 | 2007-08-31 | Method and apparatus for recovering I2C bus locked by slave device |
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| CN100504831C true CN100504831C (en) | 2009-06-24 |
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Families Citing this family (8)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN102073613B (en) * | 2010-12-15 | 2013-05-08 | 创新科存储技术有限公司 | Device and method for removing deadlock of I<2>C (Inter-Integrated Circuit) bus |
| CN103414625A (en) * | 2013-06-14 | 2013-11-27 | 无锡拓能自动化科技有限公司 | Ethernet IO module based on Modbus Tcp |
| CN103412531B (en) * | 2013-07-30 | 2016-09-07 | 华为数字技术（苏州）有限公司 | A kind of bus control method and device |
| CN106227682B (en) * | 2015-08-31 | 2020-08-18 | 旺宏电子股份有限公司 | Electronic device, memory device and data exchange method thereof |
| CN105279055B (en) * | 2015-10-20 | 2019-01-29 | 昆山龙腾光电有限公司 | A kind of hot plug detection adjusting circuit |
| CN106354685A (en) * | 2016-08-19 | 2017-01-25 | 浪潮电子信息产业股份有限公司 | Implementation method of PSU and ME communication I2C bus hang recovery |
| CN106649180B (en) * | 2016-09-09 | 2019-08-20 | 锐捷网络股份有限公司 | A kind of releasing I2The method and device of C bus deadlock |
| CN108563598A (en) * | 2018-03-02 | 2018-09-21 | 上海芯导电子科技有限公司 | A kind of I from wake-up2C communication architecture systems |
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| CN1831801A (en) * | 2005-03-10 | 2006-09-13 | 华为技术有限公司 | Method for recovering communication of I2C main device and I2C slave device |
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| CN1740998A (en) * | 2005-09-13 | 2006-03-01 | 中兴通讯股份有限公司 | Method for realizing to reset main device in 12C bus and resetting apparatus and equipment thereof |
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