CN1912858A - Method and device for preventing I2C bus locked - Google Patents
Method and device for preventing I2C bus locked Download PDFInfo
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- CN1912858A CN1912858A CN 200510089959 CN200510089959A CN1912858A CN 1912858 A CN1912858 A CN 1912858A CN 200510089959 CN200510089959 CN 200510089959 CN 200510089959 A CN200510089959 A CN 200510089959A CN 1912858 A CN1912858 A CN 1912858A
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Abstract
This invention discloses a method and a device for avoiding locking of I2C bus line, in which, the method includes: a monitor device is connected on the I2C bus line to monitor it timely, if the monitor device tests that the primary device of the being tested I2C bus is restored in the reading signal period on the I2C bus line, then the monitor device provides clock signal numbers for at least one read operation to the I2C bus to guarantee to complete one time of read operation. The device includes a controller, a storage, an input/output port and a monitor circuit for testing level signals on the bus, one end of which is connected to the controller via the bus structure, the other end is connected with the being tested I2C bus and the restoration line of the CPU is connected to the monitor circuit at the same time.
Description
Technical field
The present invention relates to the computing machine communication field, relate in particular to a kind of method and apparatus of avoiding the I2C lock bus in I2C bus (Inter-IC BUS, interconnect bus between the integrated circuit) equipment of having used.
Background technology
The I2C bus is an a kind of cover universal serial bus by the exploitation of Philip (PHILIPS) company, is used to connect microcontroller and peripherals thereof.The I2C bus has two signal wires: a clock line SCL, a bidirectional data line SDA.All clock line SCL that receive the device on the I2C bus all are connected to the SCL of bus, and data line SDA is connected to the bidirectional data line sda line of bus.Bus uses software addressing to discern each device (as microcontroller, storer, lcd driver, clock chip and other I2C bus devices), has saved the chip select line of each device fully, thereby has made the wiring of system very simple.I2C has become important global industrywide standard at present, is admitted and uses by all main IC manufacturers.In computer network communication equipment, the device application with I2C bus interface is also more and more.In the I2C bus, when certain device generated the clock signal SCK on bus and initiates data transmission, the transmitter of being known as (also being main device), certain device during receiving control information, were called as receiver (also crying from device) on bus.Main device is used to start bus, and clocking also transmits data, and this moment, any device that is addressed all was considered to from device.
During the work of I2C bus, SCL provides the clock sync signal pulse by the control of the main device on bus clock line, finishes data by bidirectional data line SDA and transmits.The data transfer rate of I2C bus is 100kbit/s under the standard operation mode, and under immediate mode, the highest transfer rate can reach 400kbit/s.In the I2C bussing technique standard, bus protocol has strict sequential requirement.
The data mode of I2C bus is: behind I2C bus commencing signal, first byte data of sending is what to be used for selecting from the address of device and indication read-write operation, wherein before 7bit be address code, 8bit is read-write zone bit (R/W).Zone bit for " 0 " expression be main device " writing " operation, promptly main device information be written to institute's addressing from device; Zone bit is " reading " operation of " 1 " expression main device.After commencing signal sends, each device in the system compares oneself address and the address delivered on the bus of main device, if it is consistent with the address that main device sends on the bus, then this device is by the device of main device addressing, and its reception information still sends information and then determined by 8bit sign (R/W).The data word joint number of each transmission is unrestricted on the I2C bus, but each byte is necessary for 8, and the byte back of each transmission (the 9th), must follow an authorization bit from device, also is response bits (ACK, Acknowledge bit).
In the I2C bussing technique standard, commencing signal, end signal (also claiming start signal and stop signal) and answer signal are defined as follows:
Start signal (S): keep between high period at clock line SCL, the last appearance of bidirectional data line SDA to low level variation, is used to start the I2C bus by high level, is the start signal of I2C bus;
Stop signal (P): keep between high period at clock line SCL, bidirectional data line SDA goes up and occurs being used to stop the I2C bus by the variation of low level to high level, is the stop signal of I2C bus;
Answer signal (A): the 9th of each byte the SCL pulse correspondence response bits in I2C bus transfer process, if bidirectional data line SDA go up to show low level and then " reply (A) " for bus,, bidirectional data line SDA shows that high level then is bus " non-replying (/A) " if going up.
Have only main device to realize management and to detect that beginning and end signal generally all are to be produced by main device to the I2C bus.During the transmission of I2C bus data, be between high period at clock line SCL, must maintain stable logic level state on the data line SDA, high level is represented data 1, and low level is represented data 0.Only when clock line SCL is low level, just allow the level state on the data line SDA to change.
The operating rate of I2C bus generally is to depend on main device and from the performance of device, with reference to the bus specification of I2C, the frequency of operation of clock line SCL can be operated in 0Hz between the 100kHz.
Itself can not lock the I2C bus, if but exist interference or SDA or SCL to be pulled into low level by some specific factor on the bus, the I2C bus just produces locking, and these are normally because external disturbance and cause from the inefficacy of device or fault.If sda line is pulled into low level by a device on the bus, main device just can not produce initial, stop signal, carry out next step transmission, this moment, main device generally can detect I2C bus appearance locking, therefore must solve the fault of I2C bus by certain means, realize next step data transmission.
In the computing machine communication apparatus, the main device on the I2C bus generally is CPU, is other device that is connected on the I2C bus from device, such as storer, sensor, real-time clock etc.If when Printed Circuit Board Design,, generally can avoid because of occurring disturbing the locking that causes bus on the bus through careful placement-and-routing.But, also have a kind of may the appearance but more hidden situation, also can cause the locking of I2C bus, and must solve by other means.For example, main device (CPU) to I2C during the read operation of device, if CPU is reset suddenly (RESET), and the read operation cycle on this moment I2C bus does not also finish, but I2C also can't know the situation that main device is reset from the device input pin that generally do not reset, the SCL that just sees bus stops to change, according to the I2C bus specification, allow clock line SCL to stop, therefore can not think that from device the main device of I2C bus breaks down yet.Behind cpu reset, this moment, SCL often was pulled to high level, standard according to I2C, data on the sda line are must be stable between high period at clock line SCL, if be low level just at the right time at the bit that SDA exports this moment from device, will drive sda line all the time from device is low level, makes main device can't produce any initial, stop signal, like this, cause the locking of I2C bus.This situation if there is not suitable reliable solution, generally can't only solve by reset (RESET) after occurring, and must re-power and could solve, and this obviously is not best solution.
At above-mentioned situation, some solutions have appearred.
MPC8541, MPC8560 series CPU in FreeScale company (a tame chip companies of the U.S.) the PowerPC series processors, its inner integrated I2C bus control register, after finding that the I2C bus is locked, can make the I2C bus withdraw from lock-out state by reading and writing a series of I2C bus control register.
The I2C of MAXIM company (a tame chip companies of the U.S.) MAX7500 series of products from device inside integrated timeout feature, the locking protection of I2C bus can be provided.If SCL does not change at 250ms internal clock line, the I2C that will finish this from device automatically operates, and gets back to original state, thereby has avoided from the locking of device to the I2C bus.
But, the device that connects on the I2C bus in the computing machine communication apparatus is often many, I2C main device (generally being CPU) not necessarily has the control register that solves I2C lock bus state, simultaneously, at present all on the I2C bus also can not all possess the function that withdraws from lock-out state automatically from device.Therefore, must design new departure, avoid the blocked problem of I2C bus possibility.
Summary of the invention
Avoid existing problem and shortage in the locking means at above-mentioned existing I2C bus, the purpose of this invention is to provide a kind of method and apparatus of avoiding the I2C lock bus simple, with low cost of realizing.
The present invention is achieved in that a kind of method of the I2C of avoiding lock bus, be connected with CPU and peripherals thereof on the described I2C bus, also be connected with watch-dog on the I2C bus between this CPU and peripherals thereof, this watch-dog is monitored in real time to the I2C bus between CPU and peripherals thereof; During being read signal on the I2C bus between CPU and peripherals thereof, if described watch-dog detects described cpu reset, then provide at least read operation required clock signal number to the I2C bus by this watch-dog, guarantee to finish once complete read operation.
A kind of device of avoiding interconnect bus locking between integrated circuit, be connected with CPU and peripherals thereof on the described I2C bus, this device includes the supervisory circuit of level signal on the described I2C bus of controller, storer, input/output port and detection, this supervisory circuit one end is connected in described controller by bus structure, other end monitoring circuit is connected in I2C bus to be detected, and the reset line of described CPU is connected in described supervisory circuit simultaneously; Described supervisory circuit is sent to described controller with the reset signal of level signal on the described I2C bus and CPU, described controller judges according to the signal that receives whether current monitoring circuit has the locking possibility, if the locking possibility is arranged, then transmit control signal to I2C bus to be detected, otherwise do not send any control signal by described supervisory circuit; After receiving the Restart Signal that resets of described CPU, described controller stops the transmission to I2C bus control signal to be detected.
By on I2C bus to be detected, connecting apparatus of the present invention, can avoid fully having improved stability, the reliability of system because of main device during I2C main device (generally being CPU) is to the read operation of I2C bus is reset by the lock bus that causes from device.It is convenient, flexible, with low cost that the present invention realizes.
Description of drawings
Fig. 1 is a realization electrical block diagram of the present invention;
Fig. 2 is a monitor state conversion synoptic diagram of the present invention.
Embodiment
The present invention is described in further detail below in conjunction with accompanying drawing.
Supervising device of the present invention includes the supervisory circuit of level signal on controller, storer, register, input/output port and the detection I2C bus, and each device connects by bus structure.Wherein, controller is finished the addressing of storer, register, input/output port and supervisory circuit and reading and writing data, realizes its control; Storer is used for the instruction of storer and the storage of related data.Device of the present invention has certain logic control function.As shown in Figure 1, label be 101 be main device on the I2C bus, generally be the CPU processor; Label be 102 be supervising device of the present invention; Label be 103 be on the I2C bus from device, a plurality of devices are generally arranged on the bus, the present invention only illustrates from device with one.Clock line SCL and bidirectional data line SDA that clock line and the data line of supervising device of the present invention by the I2C supervisory circuit is connected to the I2C bus, simultaneously, the reseting signal line of CPU is also introduced supervising device of the present invention, detects with the cpu reset situation of finishing I2C bus to be detected.Each circuit connects when realizing, can be in the unit system's (comprise I2C bus, CPU and from device) design phase of (veneer), just the reseting signal line of the clock line SCL on the I2C bus in the plate and bidirectional data line SDA and main device (generally being CPU) is introduced supervising device of the present invention simultaneously.The I2C supervisory circuit is sent to the reset signal of level signal on the I2C bus and CPU the controller of supervising device of the present invention, controller is judged the possibility that whether has on the current I 2C bus by from the device locking according to the signal that receives, if have, then pass through the I2C supervisory circuit to I2C bus tranmitting data register signal to be detected, otherwise do not send any control signal; After receiving the Restart Signal that resets of CPU, controller stops the transmission to the control signal of I2C bus to be detected.The present invention especially is fit to detect the equipment that has only a main device on the I2C bus.
In addition, for fear of the confusion of bus signals, the output terminal that requires each device to be connected to bus must be out to leak the structure of output or open collector output in the I2C bus.Therefore, at reseting period, main device (CPU) generally all be high resistant output about two pin SCL of I2C bus and SDA, the I2C bus pin of main device (CPU) can not influence entire I 2C bus, therefore, supervisory circuit of the present invention can be at the main device drive clock line SCL that is reset, the operating cycle of finishing the I2C bus, and need not the situation of knowing that main device is reset from device.After main device (CPU) resets and finishes, supervisory circuit will stop the control to the I2C bus, be operated in monitoring I2C bus state.
Supervising device of the present invention has general logic control ability and gets final product, can be by programmable logic device (PLD) (PLD, Programmable Logic Devices) realizes, can realize function of the present invention as CPLD (CPLD) or FPGA (field programmable gate array) etc.It will be appreciated by those skilled in the art that other more senior control device can be realized the present invention equally if do not consider cost.
Below describe concrete method for supervising of the present invention in detail.
As shown in Figure 2, each circle among the figure is represented a kind of duty of the present invention, and arrow is illustrated in conversion of operation state under the different condition.Supervisory circuit of the present invention in the inner realization of PLD, is the functional module of PLD generally.In the practical application, in order to form modularization, and adapt to the PLD device of how tame manufacturer, this functional module is generally by hardware description language Verilog or VHDL realization, to improve portability.
Under the situation of I2C bus free time, state of the present invention is " free time " state, the I2C bus is not made any control and treatment; At " free time " state, if start signal occurs on the I2C bus, the present invention is transformed into " detecting this I2C operation " state; Otherwise, still remain on " free time " state.
When " detecting this I2C operation " state, detect the 8bit of first byte data---the read-write zone bit, if this is operating as " write operation ", because " write operation " can be by the locking that causes the I2C bus from device even do not finish yet, therefore state exchange of the present invention is to " free time " state; If this is operating as " read operation ", should further follow the tracks of detection, state exchange of the present invention is to " monitoring the I2C bus " state.
At " monitoring the I2C bus " state, if stop signal appears in the I2C bus, show that the operating cycle of an I2C bus finishes, state exchange of the present invention is to " free time " state; If in this state, main device is reset, this moment may be by the locking that causes the I2C bus from device, and therefore, state exchange is to " avoiding the I2C locking " state.Promptly, send 9 time clock, guarantee to finish " read operation " on the I2C bus to the SCL clock line by the controller drives supervisory circuit of supervising device of the present invention.Then, state exchange is " free time " state.Simultaneously, after CPU (main device) withdraws from reset mode and restarts, should on the I2C bus, send a stop signal, make from device and finish the I2C bus operation cycle fully one time.Since general I2C bus be up to 100kHz from device supporting bus frequency, therefore, under the clock frequency, the time that sends 9 time clock is 90ms at this moment, should be not less than 100ms and get final product the reset time that CPU (main device) is set.
The clock pulses number of transmission of the present invention should be more than or equal to the clock pulses number of a read operation, and get final product the period of the cpu reset time of I2C bus to be detected greater than a read operation.
The present invention when being reset, finishes one time read operation cycle by supervisory circuit control I2C bus at the I2C main device during the device read operation, thereby can avoid the locking that may cause the I2C bus from device.
Certainly; the present invention also can have other various embodiments; under the situation that does not deviate from spirit of the present invention and essence thereof; those skilled in the art work as can make various corresponding changes and distortion according to the present invention, but these corresponding changes and distortion all should belong to the protection domain of the appended claim of the present invention.
Claims (10)
1, a kind of method of avoiding the I2C lock bus, be connected with CPU and peripherals thereof on the described I2C bus, it is characterized in that also be connected with watch-dog on the I2C bus between described CPU and peripherals thereof, this watch-dog is monitored in real time to the I2C bus between CPU and peripherals thereof; During being read signal on the I2C bus between CPU and peripherals thereof, if described watch-dog detects described cpu reset, then provide at least read operation required clock signal number to described I2C bus, guarantee to finish once complete read operation by this watch-dog.
2, the method for avoiding the I2C lock bus according to claim 1 is characterized in that, the period that described cpu reset is restarted is greater than the cycle of a read operation; After described CPU was restarted, interconnect bus sent stop signal between the integrated circuit between described CPU and peripherals thereof, finished a read operation cycle of described peripherals.
3, the method for avoiding the I2C lock bus according to claim 2 is characterized in that, after described watch-dog detects the stop signal of described CPU transmission, does not then finish it if finish the transmission of clock signal as yet, and returns original state; If finished then directly to return original state.
4, the method for avoiding the I2C lock bus according to claim 1, it is characterized in that this method also comprises, when described watch-dog detects on the I2C bus between described CPU and peripherals thereof to the signal beyond the read signal, be changed to idle condition, described I2C bus do not controlled.
5, according to the described method of avoiding the I2C lock bus of arbitrary claim in the claim 1 to 4, it is characterized in that, described I2C bus comprises serial time clock line and bidirectional serial data lines, described watch-dog is connected with described I2C bus and is specially, and described serial time clock line and bidirectional serial data lines are connected to the clock line and the data line of described watch-dog; Simultaneously, the reset line of described CPU is connected in described watch-dog simultaneously.
6, the method for avoiding the I2C lock bus according to claim 5 is characterized in that, described watch-dog can be the logic control device of low side, can be CPLD or field programmable gate array.
According to the described method of avoiding the I2C lock bus of arbitrary claim in the claim 1 to 4, it is characterized in that 7, the output terminal that described peripherals is connected to bus is out drain terminal or open-collector output.
8, a kind of device of avoiding the I2C lock bus includes controller, storer and input/output port; Be connected with CPU and peripherals thereof on the described I2C bus, it is characterized in that, this device also comprises the supervisory circuit that detects level signal on the described I2C bus, this supervisory circuit one end is connected in described controller by bus structure, other end monitoring circuit is connected in I2C bus to be detected, and the reset line of described CPU is connected in described supervisory circuit simultaneously; Described supervisory circuit is sent to described controller with the reset signal of level signal on the described I2C bus and CPU, described controller judges according to the signal that receives whether current monitoring circuit has the locking possibility, if the locking possibility is arranged, then transmit control signal to I2C bus to be detected, otherwise do not send any control signal by described supervisory circuit; After receiving the Restart Signal that resets of described CPU, described controller stops the transmission to the control signal of I2C bus to be detected.
9, the device of avoiding the I2C lock bus according to claim 8, it is characterized in that, described I2C bus comprises serial time clock line and bidirectional serial data lines, described supervisory circuit comprises clock line and data line, and the clock line of this supervisory circuit and data line are connected to described serial time clock line and bidirectional serial data lines; The control signal that described controller sends is specially clock signal.
10, the device of avoiding the I2C lock bus according to claim 9 is characterized in that, the possible situation of described I2C lock bus is meant and is described cpu reset during the read signal on the described I2C bus; Described controller sends at least required clock signal number of read operation cycle to described I2C bus, and the period that described cpu reset is restarted is greater than the cycle of a read operation.
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| CNB2005100899598A CN100426274C (en) | 2005-08-08 | 2005-08-08 | Method and device for preventing I2C bus locked |
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| CNB2005100899598A CN100426274C (en) | 2005-08-08 | 2005-08-08 | Method and device for preventing I2C bus locked |
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Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100504831C (en) * | 2007-08-31 | 2009-06-24 | 中兴通讯股份有限公司 | Method and apparatus for recovering I2C bus locked by slave device |
| CN102521187A (en) * | 2011-11-29 | 2012-06-27 | 广东东研网络科技有限公司 | Method for solving communication deadlock of I2C (Inter-Integrated Circuit) bus |
| CN102662452A (en) * | 2012-03-30 | 2012-09-12 | 中兴通讯股份有限公司 | Method, device and system for controlling inter-integrated circuit (I2C) master device to reset |
| CN102662902A (en) * | 2012-03-30 | 2012-09-12 | 中兴通讯股份有限公司 | Method, device and system for preventing I2C (inter-integrated circuit) bus locking |
| CN103856381A (en) * | 2012-11-28 | 2014-06-11 | 苏州工业园区新宏博通讯科技有限公司 | Method, device and system for automatically releasing dead lock of a hot-plug I2C bus |
| CN106126362A (en) * | 2016-06-17 | 2016-11-16 | 青岛海信宽带多媒体技术有限公司 | A kind of optical module I2C bus unrest sequential diagnosis method and device |
| CN106170781A (en) * | 2014-04-02 | 2016-11-30 | 高通股份有限公司 | The method sending extraneous information in (I2C) bus between integrated circuit in band |
| CN111352876A (en) * | 2020-02-29 | 2020-06-30 | 苏州浪潮智能科技有限公司 | Redriver chip code error rewriting monitoring system and method |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
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| US6799233B1 (en) * | 2001-06-29 | 2004-09-28 | Koninklijke Philips Electronics N.V. | Generalized I2C slave transmitter/receiver state machine |
| US7016993B2 (en) * | 2002-12-17 | 2006-03-21 | Inventec Corporation | I2C MUX with anti-lock device |
| CN100346330C (en) * | 2005-03-10 | 2007-10-31 | 华为技术有限公司 | Method for recovering communication of I2C main device and I2C slave device |
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- 2005-08-08 CN CNB2005100899598A patent/CN100426274C/en active Active
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN100504831C (en) * | 2007-08-31 | 2009-06-24 | 中兴通讯股份有限公司 | Method and apparatus for recovering I2C bus locked by slave device |
| CN102521187B (en) * | 2011-11-29 | 2014-05-28 | 广东东研网络科技股份有限公司 | Method for solving communication deadlock of I2C (Inter-Integrated Circuit) bus |
| CN102521187A (en) * | 2011-11-29 | 2012-06-27 | 广东东研网络科技有限公司 | Method for solving communication deadlock of I2C (Inter-Integrated Circuit) bus |
| CN102662902B (en) * | 2012-03-30 | 2015-05-13 | 中兴通讯股份有限公司 | Method, device and system for preventing I2C (inter-integrated circuit) bus locking |
| CN102662902A (en) * | 2012-03-30 | 2012-09-12 | 中兴通讯股份有限公司 | Method, device and system for preventing I2C (inter-integrated circuit) bus locking |
| CN102662452A (en) * | 2012-03-30 | 2012-09-12 | 中兴通讯股份有限公司 | Method, device and system for controlling inter-integrated circuit (I2C) master device to reset |
| CN103856381A (en) * | 2012-11-28 | 2014-06-11 | 苏州工业园区新宏博通讯科技有限公司 | Method, device and system for automatically releasing dead lock of a hot-plug I2C bus |
| CN106170781A (en) * | 2014-04-02 | 2016-11-30 | 高通股份有限公司 | The method sending extraneous information in (I2C) bus between integrated circuit in band |
| CN106126362A (en) * | 2016-06-17 | 2016-11-16 | 青岛海信宽带多媒体技术有限公司 | A kind of optical module I2C bus unrest sequential diagnosis method and device |
| CN106126362B (en) * | 2016-06-17 | 2019-01-04 | 青岛海信宽带多媒体技术有限公司 | A kind of optical module I2C bus unrest sequential diagnosis method and device |
| CN111352876A (en) * | 2020-02-29 | 2020-06-30 | 苏州浪潮智能科技有限公司 | Redriver chip code error rewriting monitoring system and method |
| CN111352876B (en) * | 2020-02-29 | 2021-07-27 | 苏州浪潮智能科技有限公司 | Redriver chip code error rewriting monitoring system and method |
| US11650872B2 (en) | 2020-02-29 | 2023-05-16 | Inspur Suzhou Intelligent Technology Co., Ltd. | System and method for monitoring code overwrite error of redriver chip |
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