CN102662902B - Method, device and system for preventing I2C (inter-integrated circuit) bus locking - Google Patents
Method, device and system for preventing I2C (inter-integrated circuit) bus locking Download PDFInfo
- Publication number
- CN102662902B CN102662902B CN201210090362.5A CN201210090362A CN102662902B CN 102662902 B CN102662902 B CN 102662902B CN 201210090362 A CN201210090362 A CN 201210090362A CN 102662902 B CN102662902 B CN 102662902B
- Authority
- CN
- China
- Prior art keywords
- bus
- pulse
- reset signal
- main device
- clock
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Abstract
The invention discloses a method, a device and a system for preventing I2C (inter-integrated circuit) bus locking. An externally transmitted reset signal to an I2C master device is acquired by a reset signal acquisition module which is connected with the I2C master device, and after the reset signal is acquired, the I2C master device needs resetting; and then a control module effectively connected an I2C bus transmits preset termination signal to the I2C bus to finish current unfinished operation on the I2C bus, so that the I2C master device is prevented from being locked due to a communication terminal in resetting, misoperation of an I2C slave device in recovering I2C bus communication is avoided, and operational reliability and stability of the system are improved.
Description
Technical field
The present invention relates to electronic communication control field, be specifically related to a kind of method, the Apparatus and system that prevent I2C lock bus.
Background technology
I2C (Inter-Integrated Circuit) bus is the twin wire universal serial bus developed by PHILIPS company, for connecting microcontroller and peripherals thereof.It is a kind of bus standard that microelectronics Control on Communication field extensively adopts.It is a kind of special shape of synchronous communication, has interface line few, and control mode is simple, and device package form is little, and traffic rate is advantages of higher comparatively.Be widely used in Technological Problems In Computer Manufacturing, telecommunication apparatus, the fields such as consumer electronics at present.
In I2C bus specification, bus protocol has strict timing requirements.During bus work, control the pulse of clock line SCL transmission clock by the main device in bus, transmit data by bidirectional data line SDA.In I2C bus, the data word joint number of each transmission is unrestricted, but each byte is necessary for 8, and must follow an authorization bit (the 9th) from device after the byte of each transmission, is also response bits (ACK, Acknowledge bit)
In I2C bus specification, beginning and end signal (also claiming initial sum stop signal) are defined as follows:
Start signal (S): keep between high period at clock line SCL, bidirectional data line SDA occurs by high level to low level change, for starting I2C bus, is the start signal of I2C bus;
Stop signal (P): keep between high period at clock line SCL, bidirectional data line SDA occurs by the change of low level to high level, for stopping I2C bus, is the termination signal of I2C bus;
Answer signal (A): the corresponding response bits of the 9th pulse of I2C bus, if bidirectional data line SDA shows low level, being bus " response " (A), if bidirectional data line SDA shows high level, is " non-response " (/A).
Beginning and end signal are all generally produced by main device, only have main device to realize management to I2C bus and to detect, as initial, stopping, tranmitting data register etc.During I2C bus data transfer, between clock line SCL high period, data line SDA must maintain stable logic level state, high level is data 1, and low level is data 0.Only when clock line is low level, the operating rate just allowing the level state change I2C bus on data line is generally the performance depending on primary controller, and with reference to the bus specification of I2C, the frequency of operation of clock line SCL can be low to moderate 0Hz.
When proper communication, I2C bus can not lock, but upon system reset, if I2C main device is also in communication process, and now SDA just by during from device drive, so due to the not tranmitting data register again of main device after resetting, SDA by from device to moving fixed level to, if SDA is now low level, after so main device resets, can think that I2C bus is done always, and then to from device operation, and cannot automatically cannot exit this state from device, cause I2C bus to be suspended, need human intervention to recover the normal sequential of bus.
Current Ge Jia chip producer is just to this situation provides some solutions, such as SCL can be detected from device, when terminating this operation without clock in certain hour, but it is all variant between I2C device each producer numerous, this just needs an additional control device, and unification addresses this problem.
For the recovery of I2C locking, the main method adopted at present has two kinds:
SDA state is detected when 1, resetting, if be low, output 9 clocks on SCL.
This method realizes relatively simple, also the state of lock bus can be removed, if but sequential is reset in specific position, can cause past from device write error data, owing to generally there is no reset function from device, this mistake, with may the normal work of influential system, be lifted conventional device EEPROM AT24C04 instance analysis below and is write situation once by mistake.
Fig. 1 is the SDA sequential of a byte write operation, Fig. 2 is the SDA sequential of a byte random write, there is the mark of 1 ACK marking line on the two maps, first can see to marking line place, the sequential of read and write is all identical, if after main device resets, just in time marking line is in from device sequential, send ACK and wait for that main device clock is responded, so can drag down data line from device always, wait for the clock that main device sends, at this moment anti-lock device detects that SDA drags down, 9 clocks are sent on SCL, response release SDA is terminated from device after 1st clock, 8 clock reference Fig. 1 next be actually toward current address be written with FF or 00 (depend on main device in the reset state SDA pin export acquiescence level, if 1 or tri-state, write FF, if 0, write 00), because EEPROM often can preserve some configuration informations, this maloperation probably causes the exception of system, after other 9 clocks, sequential does not terminate, main device first time operation after resetting, wrong sequential is spliced into operation residual during last reset, also first time operation failure can be caused, only have and send a STOP to main device, could recover normal.
SDA state is detected when 2, resetting, if be low, output 1 clock on SCL, and then detect SDA state, if send a clock again for low, move in circles, until SDA uprises.
This method is compared the first and is wanted complicated a lot, the operation to writing from device by mistake can be avoided, but detection SDA uprises and not necessarily releases SDA from device, be likely have sent one 1 when read data from device, if at this moment just stop sending clock, so SDA is still by from device drive, after resetting, main device START when initiating first time I2C operation cannot normally send, first time operation certainly failure, to only have etc. after main device sends a STOP, just can discharge SDA from device.This method also also exists in addition, main device first time operation after resetting, and during last reset, residual operation is spliced into wrong sequential, causes the problem of first time operation failure
Therefore, be badly in need of proposing a kind of a kind of control newly method preventing I2C lock bus, when to avoid occurring in I2C main device reseting procedure that I2C bus is locked and recover I2C bus, maloperation I2C is from situations such as devices.
Summary of the invention
The main technical problem to be solved in the present invention is, a kind of method, the Apparatus and system that prevent I2C lock bus are provided, the situation that in I2C main device reseting procedure, I2C bus is locked is avoided to occur, ensure proper operation when recovering I2C bus communication, improve the reliability and stability of system works.
For solving the problems of the technologies described above, the invention provides a kind of device preventing I2C lock bus, comprising:
Reset signal acquisition module, is connected with I2C main device, sends to the reset signal of described I2C main device for obtaining the external world;
Control module, is effectively connected with I2C bus, for after described reset signal acquisition module gets described reset signal, sends the termination signal preset and terminates current non-end operation in described I2C bus to described I2C bus.
In an embodiment of the present invention, described I2C bus comprises serial time clock line and bidirectional serial data lines, and the clock control line that described control module comprises and data line are connected with the Serial Bus Clock of described I2C bus and bidirectional serial data lines respectively.
In an embodiment of the present invention, described preset termination signal comprises the pulse of at least 10 specific time sequence.
In an embodiment of the present invention, described preset termination signal is the pulse of 10 specific time sequence, and described specific time sequence is the phase differential of the pulse on Serial Bus Clock and the pulse in bidirectional serial data lines be T/4, described T is the recurrence interval.
Present invention also offers a kind of system preventing I2C lock bus, comprising I2C that I2C main device is connected with described I2C main device by I2C bus with at least one from device, also comprising the device for preventing I2C lock bus;
Described I2C main device is for receiving the extraneous reset signal sent;
Described device comprises: reset signal acquisition module, is connected with described I2C main device, sends to the reset signal of described I2C main device for obtaining the external world;
Control module, is effectively connected with described I2C bus, for after described reset signal acquisition module gets described reset signal, sends the termination signal preset and terminates current non-end operation in described I2C bus to described I2C bus.
In an embodiment of the present invention, described I2C bus comprises serial time clock line and bidirectional serial data lines, and the clock control line that described control module comprises and data line are connected with the Serial Bus Clock of described I2C bus and bidirectional serial data lines respectively.
In an embodiment of the present invention, described preset termination signal comprises the pulse of at least 10 specific time sequence.
In an embodiment of the present invention, described preset termination signal is the pulse of 10 specific time sequence, and described specific time sequence is the phase differential of the pulse on Serial Bus Clock and the pulse in bidirectional serial data lines be T/4, described T is the recurrence interval.
Present invention also offers a kind of method preventing I2C lock bus, comprising:
Detect I2C main device and whether receive extraneous transmission reset signal;
If detect, I2C main device receives extraneous transmission reset signal, then send default termination signal and terminate current non-end operation in described I2C bus to I2C bus.
In an embodiment of the present invention, described preset termination signal comprises the pulse of at least 10 specific time sequence.
In an embodiment of the present invention, described preset termination signal is the pulse of 10 specific time sequence, and described specific time sequence is the phase differential of the pulse on Serial Bus Clock and the pulse in bidirectional serial data lines be T/4, described T is the recurrence interval.
The invention has the beneficial effects as follows: the present invention obtains the extraneous reset signal sending to I2C main device by the reset signal acquisition module be connected with I2C main device, after getting this reset signal, shows that I2C main device will carry out reset operation; Then current non-end operation in this I2C bus is terminated by sending with the control module that I2C bus is effectively connected the termination signal preset to I2C bus, the situation avoiding I2C main device to cause communication terminal to cause I2C bus locked in reseting procedure occurs, avoid when recovering I2C bus communication and from device, maloperation is carried out to I2C, improve the reliability and stability of system works.
Accompanying drawing explanation
Fig. 1 is the SDA sequential chart of a kind of byte write operation of the present invention;
Fig. 2 is the SDA sequential chart of a kind of byte random write of the present invention;
Fig. 3 is the structured flowchart preventing the system of I2C lock bus of an embodiment of the present invention;
Fig. 4 is the structured flowchart preventing the device of I2C lock bus of an embodiment of the present invention;
Fig. 5 is the pulse schematic diagram of the specific time sequence of an embodiment of the present invention;
Fig. 6 is the process flow diagram preventing the method for I2C lock bus of an embodiment of the present invention.
Embodiment
By reference to the accompanying drawings the present invention is described in further detail below by embodiment.
Please refer to Fig. 3, prevent the system of I2C lock bus from the comprising I2C that I2C main device is connected with described I2C main device by I2C bus with at least one provided in the present embodiment is from device, I2C also can comprise polytype from device, also comprises the device for preventing I2C lock bus; Wherein,
I2C main device can be used for receiving the extraneous reset signal sent;
Refer to Fig. 4, in the present embodiment for preventing the device of I2C lock bus from specifically comprising:
Reset signal acquisition module, is connected with I2C main device, sends to the reset signal of I2C main device for obtaining the external world;
Control module, is effectively connected with I2C bus, for after reset signal acquisition module gets reset signal, sends the termination signal preset and terminates current non-end operation in I2C bus to I2C bus.Namely embodiment mainly through increasing by one for preventing the device of I2C lock bus in I2C bus, the reset signal of monitoring I2C main device, when finding that main device is reset, sending the termination signal of setting, terminating the I2C bus operation that I2C bus may be interrupted.
The controller of reseting period main device be all generally high resistant export, and generally all there is no reseting pin from device, also cannot being reset by perception main device, therefore operating from device for preventing the device of I2C lock bus from can simulate main device completely in this state.The situation avoiding I2C main device to cause communication terminal to cause I2C bus locked in reseting procedure occurs, and can avoid carrying out maloperation to I2C from device when recovering I2C bus communication, improves the reliability and stability of system works.
Concrete, in the present embodiment for realizing by specific hardware circuit or programming device at reset signal acquisition module; I2C bus comprises serial time clock line SCL and bidirectional serial data lines SDA, the above-mentioned control module for preventing the device of I2C lock bus from comprising comprises clock control line and data line, and be connected with the Serial Bus Clock of I2C bus and bidirectional serial data lines respectively, with when I2C main device resets, send default termination signal in I2C bus.
Because I2C after transmission byte each in I2C bus must follow an authorization bit from device, the length of each byte therefore can thought in I2C bus is 9, and then known I2C needs maximum 9 termination signal STOP to discharge bidirectional serial data lines SDA from device, based on above-mentioned analysis, preset termination signal in the present embodiment comprises the pulse of at least 10 specific time sequence, specifically can be preferably the pulse that preset termination signal is 10 specific time sequence, refer to Fig. 5, this specific time sequence is the phase differential of pulse on the pulse of SCL on Serial Bus Clock and bidirectional serial data lines SDA is T/4, this T is the recurrence interval, the phase place being specially the pulse of SCL on Serial Bus Clock shifts to an earlier date T/4 than the phase place of the pulse on bidirectional serial data lines SDA.When I2C needs maximum 9 termination signal STOP could discharge bidirectional serial data lines SDA from device, when the pulse of the 10th specific time sequence from response device, this operates end.
As from the foregoing, if need N (0<N<10) individual clock release SDA from device, so within that N number of clock SDA for from device be all export, top n STOP is just equivalent to N number of clock, N+1 STOP is from response device, bus operation terminates, if after also have STOP, bus is not affected.The pulse number of the specific time sequence that the preset termination signal therefore in the present embodiment comprises specifically can be selected according to actual conditions, is not fixed as above-mentioned 10.
For a better understanding of the present invention, below in conjunction with preventing the concrete grammar of I2C lock bus, the present invention will be further described, refers to Fig. 6:
Step 61: detect that I2C main device receives extraneous transmission reset signal;
Step 62: send above-mentioned default termination signal (pulse signal namely shown in Fig. 5) and terminate current non-end operation in described I2C bus to I2C bus.
Method in the present embodiment does not need the state monitoring or consider I2C bus, and realization flow is simpler, cost is lower, does further brief description below for various situation:
I2C bus free when 1, resetting, does not have ongoing read-write operation:
In this case, 10 STOP on from device without any impact, bus keeps idle
When 2, resetting, I2C bus communicates, and SDA is driven by main device:
This situation, from response device first STOP, terminate last operation, follow-up STOP does not respond, and bus keeps idle.
3 I2C buses when resetting communicate, and SDA is by from device drive:
Here be no matter high or low from the SDA of device drive, for SDA from device be all export, suppose to need 9 maximum clocks to discharge data line from device, so front 9 STOP of sending of control module, say for from device, due to SDA from device be export, reality is just equivalent to 9 clocks, and from device release SDA after such 9 STOP, at this moment last 10th STOP is from response device, this operates end, and bus keeps idle.
Step 63: operation terminates.
Whether the present invention monitors I2C main device by the reset signal acquisition module be connected with I2C main device will carry out reset operation; In this way, current non-end operation in this I2C bus is terminated to I2C bus by sending with the control module that I2C bus is effectively connected the termination signal preset, the situation avoiding I2C main device to cause communication terminal to cause I2C bus locked in reseting procedure occurs, can avoid carrying out maloperation to I2C from device when recovering I2C bus communication, and then improve the reliability and stability of system works.
Above content is in conjunction with concrete embodiment further description made for the present invention, can not assert that specific embodiment of the invention is confined to these explanations.For general technical staff of the technical field of the invention, without departing from the inventive concept of the premise, some simple deduction or replace can also be made, all should be considered as belonging to protection scope of the present invention.
Claims (8)
1. prevent a device for I2C lock bus, it is characterized in that comprising:
Reset signal acquisition module, is connected with I2C main device, sends to the reset signal of described I2C main device for obtaining the external world;
Control module, effectively be connected with I2C bus, for after described reset signal acquisition module gets described reset signal, send the termination signal preset and terminate current non-end operation in described I2C bus to described I2C bus, described preset termination signal comprises the pulse of at least 10 specific time sequence.
2. prevent the device of I2C lock bus as claimed in claim 1, it is characterized in that, described I2C bus comprises serial time clock line and bidirectional serial data lines, and the clock control line that described control module comprises and data line are connected with the Serial Bus Clock of described I2C bus and bidirectional serial data lines respectively.
3. prevent the device of I2C lock bus as claimed in claim 1 or 2, it is characterized in that, described preset termination signal is the pulse of 10 specific time sequence, described specific time sequence is the phase differential of the pulse on Serial Bus Clock and the pulse in bidirectional serial data lines be T/4, described T is the recurrence interval.
4. prevent a system for I2C lock bus, it is characterized in that, comprising I2C that I2C main device is connected with described I2C main device by I2C bus with at least one from device, also comprising the device for preventing I2C lock bus;
Described I2C main device is for receiving the extraneous reset signal sent;
Described device comprises: reset signal acquisition module, is connected with described I2C main device, sends to the reset signal of described I2C main device for obtaining the external world;
Control module, effectively be connected with described I2C bus, for after described reset signal acquisition module gets described reset signal, send the termination signal preset and terminate current non-end operation in described I2C bus to described I2C bus, described preset termination signal comprises the pulse of at least 10 specific time sequence.
5. prevent the system of I2C lock bus as claimed in claim 4, it is characterized in that, described I2C bus comprises serial time clock line and bidirectional serial data lines, and the clock control line that described control module comprises and data line are connected with the Serial Bus Clock of described I2C bus and bidirectional serial data lines respectively.
6. the system preventing I2C lock bus as described in claim 4 or 5, it is characterized in that, described preset termination signal is the pulse of 10 specific time sequence, described specific time sequence is the phase differential of the pulse on Serial Bus Clock and the pulse in bidirectional serial data lines be T/4, described T is the recurrence interval.
7. prevent a method for I2C lock bus, it is characterized in that comprising:
Detect I2C main device and whether receive extraneous transmission reset signal;
If detect, I2C main device receives extraneous transmission reset signal, then send default termination signal and terminate current non-end operation in described I2C bus to I2C bus, described preset termination signal comprises the pulse of at least 10 specific time sequence.
8. prevent the method for I2C lock bus as claimed in claim 7, it is characterized in that, described preset termination signal is the pulse of 10 specific time sequence, and described specific time sequence is the phase differential of the pulse on Serial Bus Clock and the pulse in bidirectional serial data lines be T/4, described T is the recurrence interval.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210090362.5A CN102662902B (en) | 2012-03-30 | 2012-03-30 | Method, device and system for preventing I2C (inter-integrated circuit) bus locking |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210090362.5A CN102662902B (en) | 2012-03-30 | 2012-03-30 | Method, device and system for preventing I2C (inter-integrated circuit) bus locking |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN102662902A CN102662902A (en) | 2012-09-12 |
| CN102662902B true CN102662902B (en) | 2015-05-13 |
Family
ID=46772398
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201210090362.5A Active CN102662902B (en) | 2012-03-30 | 2012-03-30 | Method, device and system for preventing I2C (inter-integrated circuit) bus locking |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN102662902B (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103810132A (en) * | 2014-03-07 | 2014-05-21 | 福州瑞芯微电子有限公司 | Bus multi-bit separate control circuit and design and control method thereof |
| CN106326163A (en) * | 2016-08-16 | 2017-01-11 | 深圳天珑无线科技有限公司 | Data transfer system and transfer method |
| CN110908841B (en) * | 2019-12-03 | 2022-09-20 | 锐捷网络股份有限公司 | I2C communication abnormity recovery method and device |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1855083A (en) * | 2005-04-29 | 2006-11-01 | 三星电子株式会社 | Master device, control method thereof, and electronic device having master device |
| CN1912858A (en) * | 2005-08-08 | 2007-02-14 | 中兴通讯股份有限公司 | Method and device for preventing I2C bus locked |
| CN101561790A (en) * | 2009-05-27 | 2009-10-21 | 中兴通讯股份有限公司 | Method, system and device for communication between main control computer and slave computers |
-
2012
- 2012-03-30 CN CN201210090362.5A patent/CN102662902B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1855083A (en) * | 2005-04-29 | 2006-11-01 | 三星电子株式会社 | Master device, control method thereof, and electronic device having master device |
| CN1912858A (en) * | 2005-08-08 | 2007-02-14 | 中兴通讯股份有限公司 | Method and device for preventing I2C bus locked |
| CN101561790A (en) * | 2009-05-27 | 2009-10-21 | 中兴通讯股份有限公司 | Method, system and device for communication between main control computer and slave computers |
Non-Patent Citations (1)
| Title |
|---|
| 一种避免I2C接口因异常复位而死锁的方案;程琳;《无锡南洋学院学报》;20071231;第6卷(第4期);全文 * |
Also Published As
| Publication number | Publication date |
|---|---|
| CN102662902A (en) | 2012-09-12 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US10169282B2 (en) | Bus serialization for devices without multi-device support | |
| JP6517243B2 (en) | Link Layer / Physical Layer (PHY) Serial Interface | |
| CN110687993B (en) | Controlling power delivery by tunneling messages over USB | |
| US6842806B2 (en) | Method and apparatus for interconnecting wired-AND buses | |
| US20150074306A1 (en) | Single Wire Communications Interface and Protocol | |
| US20110208885A1 (en) | Data bus control method and apparatus | |
| CN104811273A (en) | Implement method for high speed single bus communication | |
| WO2016099627A1 (en) | DATA TRANSMISSION USING PCIe PROTOCOL VIA USB PORT | |
| US20070088874A1 (en) | Offload engine as processor peripheral | |
| TW201822011A (en) | A slave device connnected to host by I2C bus and its communication method | |
| CN111061587A (en) | Communication control method, device, equipment and storage medium of I2C bus | |
| WO2005119448A1 (en) | Error recovery scheme for i2c slave | |
| CN102662902B (en) | Method, device and system for preventing I2C (inter-integrated circuit) bus locking | |
| WO2007030978A1 (en) | Method, reset apparatus and equipment for realizing reset of master device in i2c bus | |
| CN108563595B (en) | System and method for long-distance transmission of USB data | |
| US20070168580A1 (en) | Apparatus to improve the firmware efficiency for a multiframe serial interface | |
| CN112214343B (en) | IIC (inter-Integrated Circuit) link recovery circuit and method based on PCA9511 chip | |
| CN111881076B (en) | I2C bus hang-up repairing method and device for communication between domestic CPU and BBU | |
| CN102455946A (en) | Detection and recovery circuit for exceptions of USB device, and method thereof | |
| CN103593316A (en) | Method for reducing I2C bus time occupied by MCU interruption | |
| CN106649187B (en) | A kind of method of chip automation peripheral hardware agreement selection | |
| CN105068962A (en) | I2C controller access method and I2C controller access system | |
| US6874047B1 (en) | System and method for implementing an SMBus/I2C interface on a network interface card | |
| CN112445744B (en) | I2C communication | |
| CN102662452A (en) | Method, device and system for controlling inter-integrated circuit (I2C) master device to reset |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant |