CN102662452A - Method, device and system for controlling inter-integrated circuit (I2C) master device to reset - Google Patents
Method, device and system for controlling inter-integrated circuit (I2C) master device to reset Download PDFInfo
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- CN102662452A CN102662452A CN2012100916343A CN201210091634A CN102662452A CN 102662452 A CN102662452 A CN 102662452A CN 2012100916343 A CN2012100916343 A CN 2012100916343A CN 201210091634 A CN201210091634 A CN 201210091634A CN 102662452 A CN102662452 A CN 102662452A
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Abstract
The invention discloses a method, a device and a system for controlling an inter-integrated circuit (I2C) master device to reset. A status flag of an inter-integrated circuit (I2C) bus is updated by setting the status flag of the I2C bus according to a preset rule in a working process; whether the I2C bus is free at present is judged according to the status flag of current I2C bus after a resetting signal transmitted from outside is received, and the resetting control signal is transmitted to the I2C master device to control the I2C master device to reset only when the judgment result is yes, otherwise, the resetting control signal is not transmitted to the I2C master device, namely the I2C master device is subjected to the resetting operation just under the condition that the I2C bus is free. Therefore, the situations that an I2C interface is abnormal, the I2C bus is suspended and the like caused by communicating of the I2C when the I2C master device is reset can be avoided; the stability and reliability of the system can be improved, and the method, device and system are low in cost and easy to achieve.
Description
Technical field
The present invention relates to electronic communication control field, be specifically related to method, Apparatus and system that a kind of I2C of control main device resets.
Background technology
I2C (Inter-Integrated Circuit) bus is by the twin wire universal serial bus of PHILIPS company exploitation, is used to connect microcontroller and peripherals thereof.It is a kind of bus standard that extensively adopt in microelectronics Control on Communication field.It is a kind of special shape of synchronous communication, and it is few to have an interface line, and control mode is simple, and the device package form is little, and traffic rate is than advantages such as height.Computing machine manufacturing, telecommunication apparatus, fields such as consumer electronics have been widely used at present.
In I2C bussing technique standard, bus protocol has strict sequential requirement.During bus work,, transmit data by bidirectional data line SDA by the pulse of the control of the main device on bus clock line SCL transmission clock.The data word joint number of each transmission is unrestricted on the I2C bus, but each byte is necessary for 8, and the byte of each transmission back must follow an authorization bit (the 9th) from device, also is response bits (ACK, Acknowledge bit)
In the I2C bussing technique standard, beginning and end signal (also claiming the initial sum stop signal) define as follows:
Start signal (S): keep between high period at clock line SCL, bidirectional data line SDA appearance to low level variation, is used to start the I2C bus by high level, is the start signal of I2C bus;
Stop signal (P): keep between high period at clock line SCL, bidirectional data line SDA occurs being used to stop the I2C bus by the variation of low level to high level, is the termination signal of I2C bus;
Answer signal (A): the corresponding response bits of the 9th pulse of I2C bus, show that low level then " replys " (A) for bus if bidirectional data line SDA goes up, if bidirectional data line SDA go up show high level then be " non-replying " (/A).
Beginning generally all is to be produced by main device with end signal, has only main device to realize management and detection to the I2C bus, as initial, stop, tranmitting data register etc.During the transmission of I2C bus data, between clock line SCL high period, must maintain stable logic level state on the data line SDA, high level is data 1, and low level is data 0.Only when clock line was low level, just allowing the operating rate of the level state variation I2C bus on the data line generally was the performance that depends on primary controller, and with reference to the bus specification of I2C, the frequency of operation of clock line SCL can be low to moderate 0Hz.
The I2C bus can not lock under the situation of proper communication, but when system reset, if the I2C main device also is in the communication process; And this moment SDA just by the time from device drive, the clock because the back main device that resets is not redispatched so, SDA is given from device to move fixed level to; If SDA is low level at this moment; After main device resets so, can think always that the I2C bus is busy, and then can't be to from device operation; And can't withdraw from this state automatically from device, cause the I2C bus to be hung up.
Therefore, be badly in need of proposing the method that a kind of new control I2C main device resets, hung up the generation of situation to avoid above-mentioned bus.
Summary of the invention
The technical problem underlying that the present invention will solve is; The method, the Apparatus and system that provide a kind of I2C of control main device to reset; When avoiding the I2C main device to reset because of I2C communicating by letter cause unusual from device I2C interface, cause the I2C bus by the generation of situation such as hanging up, improve the stability and reliability height of system.
For solving the problems of the technologies described above, the device that the present invention provides a kind of I2C of control main device to reset comprises:
Indicate storage unit, be used for the I2C bus state sign of storage representation I2C bus current state;
The reset signal receiving element is used to receive extraneous reset signal of sending;
The judgment processing unit; Be used for after said reset signal receiving element receives said reset signal; I2C bus state sign according to the current storage of sign storage unit is judged the current idle condition that whether is in of said I2C bus; In this way, sending reseting controling signal controls said I2C main device for the I2C main device to reset; Otherwise, do not send reseting controling signal and give said I2C main device.
In an embodiment of the present invention; Said judgment processing unit also is used for after said reset signal receiving element receives said reset signal; Judge whether said reset signal is effective; When judging that the effective and said I2C bus of said reset signal is current when idle, send said reseting controling signal and give said I2C main device.
The system that resets of a kind of I2C of control main device that the present invention also provides example comprises the I2C main device and is used to control the device that the I2C main device resets that the device that said I2C main device resets comprises:
Indicate storage unit, be used for the I2C bus state sign of storage representation I2C bus current state;
The reset signal receiving element is used to receive extraneous reset signal of sending;
The judgment processing unit; Be used for after said reset signal receiving element receives said reset signal; I2C bus state sign according to the current storage of sign storage unit is judged the current idle condition that whether is in of said I2C bus; In this way, sending reseting controling signal controls said I2C main device for the I2C main device to reset; Otherwise, do not send reseting controling signal and give said I2C main device;
Said I2C main device is used for upgrading by preset rules in the course of the work the I2C bus state sign of said sign cell stores; And after being used to receive the said reseting controling signal that sends said judgment processing unit, carry out reset operation.
In an embodiment of the present invention, said judgment processing unit is connected with the reset terminal of said I2C main device.
In an embodiment of the present invention, but saidly be used to control the device that the I2C main device resets and realize through programmable logic controller (PLC) spare or scene editorial logic array.
In an embodiment of the present invention, said I2C main device is connected with said sign storage unit through the read-write bus.
In an embodiment of the present invention; Said preset rules is: said I2C main device is updated to busy state with the I2C bus state sign of said sign cell stores when each I2C of initiation operates; When each I2C EO, the I2C bus state sign of said sign cell stores is updated to idle condition.
In an embodiment of the present invention, said I2C main device is CPU.
The method that the present invention also provides a kind of I2C of control main device to reset comprises:
I2C bus state sign is set;
Upgrade said I2C bus state sign by preset rules in the course of work;
After receiving reset signal, judge the current idle condition that whether is in of said I2C bus according to current I2C bus state sign, in this way, the transmission reseting controling signal is controlled said I2C main device to the I2C main device and is resetted; Otherwise, do not send reseting controling signal and give said I2C main device.
In an embodiment of the present invention; Said preset rules is: the I2C main device is updated to busy state with said I2C bus state sign when each I2C of initiation operates; When each I2C EO, said I2C bus state sign is updated to idle condition.
In an embodiment of the present invention, receive said reset signal after, also comprise and judge whether effectively step of said reset signal; Effective and said I2C bus is current when idle when said reset signal, sends said reseting controling signal and gives said I2C main device.
The invention has the beneficial effects as follows: the present invention is through being provided with I2C bus state sign, and upgrades I2C bus state sign by preset rules in the course of the work; After receiving extraneous reset signal of sending, judge according to current I2C bus state sign whether the I2C bus is current idle, and only just send reseting controling signal when being and control the I2C main device to the I2C main device and reset in judged result; Otherwise, do not send reseting controling signal and give the I2C main device.Be that the present invention is only under the idle situation of I2C bus; The I2C main device just can carry out reset operation; Therefore in the time of can avoiding the I2C main device to reset because of I2C communicating by letter cause unusual from device I2C interface, cause the I2C bus by the generation of situation such as hanging up; The stability and the reliability that can improve system are high, and cost is low, is prone to realize.
Description of drawings
Fig. 1 is the method flow diagram that the control I2C main device of an embodiment of the present invention resets;
The structured flowchart of the device that Fig. 2 resets for the control I2C main device of an embodiment of the present invention;
The structured flowchart of the system that Fig. 3 resets for the control I2C main device of an embodiment of the present invention;
Fig. 4 is the process flow diagram of the renewal I2C bus state sign of an embodiment of the present invention.
Embodiment
Combine accompanying drawing that the present invention is done further explain through embodiment below.
Please refer to Fig. 1, the method that control I2C main device resets in the present embodiment can may further comprise the steps:
I2C bus state sign is set, and set I2C bus state sign can be used for representing I2C bus current working state, is used to promptly represent that current I 2C bus is in idle condition or is in busy condition;
Upgrade I2C bus state sign by preset rules in the course of work;
After receiving reset signal, judge the current idle condition that whether is in of I2C bus according to current I2C bus state sign, in this way, then send reseting controling signal and reset for the I2C main device to control this I2C main device; Otherwise; Expression I2C bus is current to be in busy state; Promptly be in communications status, then do not sending reseting controling signal in the case and give the I2C main device, when avoiding the I2C bus to be in busy condition; The I2C main device carries out reset operation and causes, I2C bus unusual from device I2C interface by the generation of situation such as hanging up, therefore can improve the stability and reliability height of system.
Concrete, in the center of working, when I2C bus state sign was upgraded, this preset rules can be through real-time monitoring I2C bus current working state, according to testing result it is upgraded; But need so in real time the duty of I2C bus to be monitored.Therefore preferred following preset rules is upgraded I2C bus state sign in the present embodiment; Be that the I2C main device is updated to busy state with I2C bus state sign when each I2C of initiation operates; When each I2C EO, I2C bus state sign is updated to idle condition; This update mode need not the I2C bus is monitored, and by I2C bus state is provided initiatively, therefore can further simplify flow process, improves practicality, reduces exploitation, use cost.
Under some special applications scene; The reset signal that send the outside that receives might not be effective reset signal; Therefore in the present embodiment after receiving outside reset signal of sending; Also can further comprise and judge whether effectively step of the reset signal receive, have only when the reset signal that receives effectively and the I2C bus current when idle, just send reseting controling signal is controlled this device to the I2C main device reset operation.It should be noted that present embodiment China judge reset signal whether effectively step can be after receiving reset signal, judge that according to I2C bus state sign I2C bus current state carries out before; Carry out after also can after receiving reset signal, according to I2C bus state sign, judging I2C bus current state.
For a better understanding of the present invention, the device that also provides a kind of I2C of control main device to reset in the present embodiment sees also Fig. 2, comprising:
Indicate storage unit, be used for the I2C bus state sign of storage representation I2C bus current state;
The reset signal receiving element is used to receive extraneous reset signal of sending;
The judgment processing unit; Be used for after the reset signal receiving element receives said reset signal; Judge according to the I2C bus state sign of the current storage of sign storage unit whether the I2C bus is current idle, in this way, send reseting controling signal and reset for this I2C main device of I2C main device control; Otherwise; Do not send reseting controling signal and give this I2C main device; It is the current communications status that is in of I2C bus; Then do not send reseting controling signal in the case and give the I2C main device, when avoiding the I2C bus to be in busy condition, the I2C main device carries out reset operation and causes, I2C bus unusual from device I2C interface by the generation of situation such as hanging up.
As stated; Under some special applications scene; The reset signal that send the outside that receives might not be effective reset signal, so the judgment processing unit in the present embodiment also is used for after the reset signal receiving element receives reset signal, judges whether this reset signal is effective; When judge this reset signal effectively and current I 2C bus current when idle, just send said reseting controling signal to said I2C main device.Whether effective opportunity is the same for judgment processing unit judges reset signal.
It should be noted that above-mentionedly in the present embodiment to be used to control the device that the I2C main device resets and specifically can to realize, but also can realize through FPGA scene editorial logic array through programmable logic device (CPLD).For example; When realizing through programmable logic device (CPLD); Specifically can be the functional module that the CPLD internal logic circuit constitutes, in the practical application, in order to form modularization and to adapt to the CPLD device of a plurality of producers; This functional module can be through realizations such as hardware description language Verilog or VHDL, to improve module portability.
See also Fig. 3, control I2C also is provided in the present embodiment system that main device resets, at least one I2C that comprise the I2C main device, is connected with the I2C main device through the I2C bus is from device and above-mentionedly be used to control the device that the I2C main device resets; Wherein the I2C main device can be used in the course of the work the I2C bus state sign by above-mentioned preset rules updating mark cell stores; And after being used to receive the said reseting controling signal that sends above-mentioned judgment processing unit, carry out corresponding reset operation.
Concrete, see also Fig. 3, the judgment processing unit that is used to control the device that the I2C main device resets is connected with the reset terminal of I2C main device.The I2C main device then is connected with indicating storage unit through the read-write bus, so that it is carried out corresponding read-write operation, and then upgrades the I2C bus state sign of its storage.According to practical situations, the I2C main device is generally CPU in the present embodiment.Along with the development of technology, the I2C main device in the present embodiment also can be other concrete devices.I2C bus state sign specifically can be realized through the value of definition one bit register in the present embodiment, when for example the value of definition register is " 1 ", and the current idle condition that is in of expression I2C bus; During for " 0 ", then current operation on the representing bus is busy state.
For the clearer how actual response current I 2C bus state of the I2C bus state sign that is provided with among the present invention of explaining intuitively, the present invention is further specified below in conjunction with Fig. 4:
Step 401-402:I2C main device is CPU when initiating each time I2C operational example such as read-write operation, at first need remove I2C bus idle marker, makes it indicate current bus state busy (be about to I2C bus state sign and be updated to busy condition by idle condition);
Step 403-405: after carrying out corresponding read-write operation, after just operation was accomplished, the I2C main device was again with this flag set, and the indication bus is idle, is about to I2C bus state sign and is updated to idle condition; Finish this operation.Utilize the I2C main device to upgrade I2C bus state sign in this example and can react I2C bus current states really.
On the above-mentioned steps basis; Be used to control the reset signal that device that the I2C main device resets then sends the outside and the value of I2C bus state zone bit and carry out combinational logic calculating; When external reset signal was invalid, no matter whether the I2C bus was idle, and the reset signal of exporting to CPU is invalid.When external reset signal is effective, judge whether bus is idle at this moment, if I2C is idle, cpu reset is effective, if the I2C bus is busy, cpu reset is invalid.The advantage of using combinational logic is the input that this moment is only depended in the output of any time; When externally reset signal was effective, if the I2C sign is busy, cpu reset was invalid; Once I2C EO; Zone bit becomes the free time, and cpu reset signal can come into force at once, has good reliability and real-time.
In sum; The present invention offers the I2C main device through combining original extraneous reset signal of directly giving the I2C main device work state information of current I 2C to change to control the device that the I2C main device resets by being used to of being connected with the I2C main device; Avoid the I2C main device that I2C was reset during device read-write operation week, thereby prevent the locking that I2C may cause the I2C bus from device, and need not carry out special improvement and design from device I2C main device and I2C; Only need on the I2C operating process, simply to be provided with; Advantages such as it is high to have good stability, reliability, and it is convenient to realize, hardware cost is low.
Above content is to combine concrete embodiment to the further explain that the present invention did, and can not assert that practical implementation of the present invention is confined to these explanations.For the those of ordinary skill of technical field under the present invention, under the prerequisite that does not break away from the present invention's design, can also make some simple deduction or replace, all should be regarded as belonging to protection scope of the present invention.
Claims (11)
1. control the device that the I2C main device resets for one kind, it is characterized in that comprising:
Indicate storage unit, be used for the I2C bus state sign of storage representation I2C bus current state;
The reset signal receiving element is used to receive extraneous reset signal of sending;
The judgment processing unit; Be used for after said reset signal receiving element receives said reset signal; I2C bus state sign according to the current storage of sign storage unit is judged the current idle condition that whether is in of said I2C bus; In this way, sending reseting controling signal controls said I2C main device for the I2C main device to reset; Otherwise, do not send reseting controling signal and give said I2C main device.
2. the device that control I2C main device as claimed in claim 1 resets; It is characterized in that; Said judgment processing unit also is used for after said reset signal receiving element receives said reset signal; Judge whether said reset signal is effective,, send said reseting controling signal and give said I2C main device when judging that the effective and said I2C bus of said reset signal is current when idle.
3. control the system that the I2C main device resets for one kind, it is characterized in that comprising the I2C main device and be used to control the device that the I2C main device resets, the device that said I2C main device resets comprises:
Indicate storage unit, be used for the I2C bus state sign of storage representation I2C bus current state;
The reset signal receiving element is used to receive extraneous reset signal of sending;
The judgment processing unit; Be used for after said reset signal receiving element receives said reset signal; I2C bus state sign according to the current storage of sign storage unit is judged the current idle condition that whether is in of said I2C bus; In this way, sending reseting controling signal controls said I2C main device for the I2C main device to reset; Otherwise, do not send reseting controling signal and give said I2C main device;
Said I2C main device is used for upgrading by preset rules in the course of the work the I2C bus state sign of said sign cell stores; And after being used to receive the said reseting controling signal that sends said judgment processing unit, carry out reset operation.
4. the system that control I2C main device as claimed in claim 3 resets is characterized in that said judgment processing unit is connected with the reset terminal of said I2C main device.
5. the system that control as claimed in claim 3 I2C main device resets is characterized in that, but saidly is used to control the device that the I2C main device resets and realizes through programmable logic controller (PLC) spare or scene editorial logic array.
6. the system that control I2C main device as claimed in claim 3 resets is characterized in that said I2C main device is connected with said sign storage unit through the read-write bus.
7. the system that resets like each described control I2C main device of claim 3-6; It is characterized in that; Said preset rules is: said I2C main device is updated to busy state with the I2C bus state sign of said sign cell stores when each I2C of initiation operates; When each I2C EO, the I2C bus state sign of said sign cell stores is updated to idle condition.
8. the system that control I2C main device as claimed in claim 7 resets is characterized in that said I2C main device is CPU.
9. control the method that the I2C main device resets for one kind, it is characterized in that comprising:
I2C bus state sign is set;
Upgrade said I2C bus state sign by preset rules in the course of work;
After receiving reset signal, judge the current idle condition that whether is in of said I2C bus according to current I2C bus state sign, in this way, the transmission reseting controling signal is controlled said I2C main device to the I2C main device and is resetted; Otherwise, do not send reseting controling signal and give said I2C main device.
10. the method that I2C main device as claimed in claim 9 resets; It is characterized in that; Said preset rules is: the I2C main device is updated to busy state with said I2C bus state sign when each I2C of initiation operates; When each I2C EO, said I2C bus state sign is updated to idle condition.
11. the method as claim 9 or 10 described I2C main devices reset is characterized in that, receive said reset signal after, also comprise and judge whether effectively step of said reset signal; Effective and said I2C bus is current when idle when said reset signal, sends said reseting controling signal and gives said I2C main device.
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| CN2012100916343A CN102662452A (en) | 2012-03-30 | 2012-03-30 | Method, device and system for controlling inter-integrated circuit (I2C) master device to reset |
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| CN2012100916343A CN102662452A (en) | 2012-03-30 | 2012-03-30 | Method, device and system for controlling inter-integrated circuit (I2C) master device to reset |
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN109002159A (en) * | 2018-06-28 | 2018-12-14 | 珠海全志科技股份有限公司 | A kind of state control circuit and method of CPU |
| CN111400079A (en) * | 2020-03-16 | 2020-07-10 | 上海金卓网络科技有限公司 | Isolator, software resetting method and device applicable to isolator and storage medium |
| CN111813596A (en) * | 2020-06-08 | 2020-10-23 | 中国长城科技集团股份有限公司 | Chip restarting method and device and computing equipment |
| WO2022057372A1 (en) * | 2020-09-18 | 2022-03-24 | 苏州浪潮智能科技有限公司 | Iic hang link restoration circuit and method based on pca9511 chip |
| CN117950472A (en) * | 2022-10-21 | 2024-04-30 | 荣耀终端有限公司 | Reset method and electronic equipment |
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| CN1740998A (en) * | 2005-09-13 | 2006-03-01 | 中兴通讯股份有限公司 | Method for realizing to reset main device in 12C bus and resetting apparatus and equipment thereof |
| CN1912858A (en) * | 2005-08-08 | 2007-02-14 | 中兴通讯股份有限公司 | Method and device for preventing I2C bus locked |
| CN102023954A (en) * | 2009-09-17 | 2011-04-20 | 研祥智能科技股份有限公司 | Device with multiple I2C buses, processor, system main board and industrial controlled computer |
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| CN1912858A (en) * | 2005-08-08 | 2007-02-14 | 中兴通讯股份有限公司 | Method and device for preventing I2C bus locked |
| CN1740998A (en) * | 2005-09-13 | 2006-03-01 | 中兴通讯股份有限公司 | Method for realizing to reset main device in 12C bus and resetting apparatus and equipment thereof |
| CN102023954A (en) * | 2009-09-17 | 2011-04-20 | 研祥智能科技股份有限公司 | Device with multiple I2C buses, processor, system main board and industrial controlled computer |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN109002159A (en) * | 2018-06-28 | 2018-12-14 | 珠海全志科技股份有限公司 | A kind of state control circuit and method of CPU |
| CN111400079A (en) * | 2020-03-16 | 2020-07-10 | 上海金卓网络科技有限公司 | Isolator, software resetting method and device applicable to isolator and storage medium |
| CN111400079B (en) * | 2020-03-16 | 2024-03-01 | 上海金卓科技有限公司 | Isolator, and software resetting method, device and storage medium applicable to isolator |
| CN111813596A (en) * | 2020-06-08 | 2020-10-23 | 中国长城科技集团股份有限公司 | Chip restarting method and device and computing equipment |
| WO2022057372A1 (en) * | 2020-09-18 | 2022-03-24 | 苏州浪潮智能科技有限公司 | Iic hang link restoration circuit and method based on pca9511 chip |
| US11990895B2 (en) | 2020-09-18 | 2024-05-21 | Inspur Suzhou Intelligent Technology Co., Ltd. | IIC hang link restoration circuit and method based on PCA9511 chip |
| CN117950472A (en) * | 2022-10-21 | 2024-04-30 | 荣耀终端有限公司 | Reset method and electronic equipment |
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Application publication date: 20120912 |