CN103810132A - Bus multi-bit separate control circuit and design and control method thereof - Google Patents
Bus multi-bit separate control circuit and design and control method thereof Download PDFInfo
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- CN103810132A CN103810132A CN201410081664.5A CN201410081664A CN103810132A CN 103810132 A CN103810132 A CN 103810132A CN 201410081664 A CN201410081664 A CN 201410081664A CN 103810132 A CN103810132 A CN 103810132A
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Abstract
The invention provides a bus multi-bit separate control circuit and a design and control method of the bus multi-bit separate control circuit. The bus multi-bit separate control circuit comprises a logic operation circuit, a current control bit input interface, a yes-no effective control bit input interface, a port control bit input interface and a final control bit state output interface, wherein the current control bit input interface, the yes-no effective control bit input interface, the port control bit input interface and the final control bit state output interface are connected with the logic operation circuit; the logic operation circuit outputs a port control bit on the final control bit state output interface when a yes-no effective control bit is enabled, and outputs a current control bit state on the final control bit state output interface when the yes-no effective control bit is disabled. The circuit disclosed by the invention is simple, designed easily, and controlled conveniently. A bus port can be separately controlled, and problems of complex bus control and low efficiency can be solved.
Description
Technical field
The present invention relates to chip design art field, relate in particular to the independent control circuit of the many bits of a kind of bus and design thereof, control method.
Background technology
Some control ports in SOC chip are by total line traffic control, and each bit has independent meaning, and each bus operation can be controlled all bit.And if only wish to control part bit wherein, can only first read and in the situation that keeps again original state of a control after existing state of a control, revise part and wish the bit controlling.But complicated along with SOC chip, particularly, in multiple nucleus system, likely, after read operation, before write operation, target control state can be revised by other processor, and the control information of writing back like this may be just wrong value.So current method typically uses software mechanism and guarantees in the time that current processor operates control register, by this sheet address area locking, do not allow other processors to conduct interviews, but this mode control complexity, and had a strong impact on system software efficiency.
Summary of the invention
The technical problem to be solved in the present invention, is to provide the independent control circuit of the many bits of a kind of bus and design thereof, control method, solves the control port control complexity of existing SOC chip, the problem of inefficiency.
The present invention is achieved in that
The independent control circuit of a kind of many bits of bus, comprise logical operation circuit, current control bit state input interface, control bit input interface, port controlling position input interface and final control bit State-output interface whether effectively, described current control bit state input interface, effectively whether control bit input interface, port controlling position input interface and final control bit State-output interface are connected with logical operation circuit;
Described logical operation circuit is when whether, effectively control bit enables, output port control bit on final control bit State-output interface, when effectively control bit deenergizes whether, on final control bit State-output interface, export current control bit state.
Further, described whether effectively level when control bit enables be high level;
Further, described logical operation circuit comprises phase inverter, first with door, second with door and or door, described whether effectively control bit input interface with second and an input end, the input end of phase inverter connects, described port controlling position input interface is connected with another input end of door with second, the output terminal of described phase inverter is connected with an input end of door with first, described first is connected with current control bit state input interface with another input end of door, described first with the output terminal of door with or an input end be connected, described second with the output terminal of door with or another input end be connected, output terminal described or door is connected with final control bit State-output interface.
And the present invention also provides the method for designing of the independent control circuit of the many bits of a kind of bus, for chip design, comprise the steps:
First be whether effectively control bit of the port controlling position increase in control data controlling in data;
Then use hardware logic electric circuit, in the time receiving control data, whether effectively the corresponding port controlling of the control bit position of deenergizing in control data is replaced with to the current state of the port that will control port controlling position, then control data are sent to port.
Further, whether effectively the figure place of described control bit identical with the figure place of port controlling position.
Further, the width of described control data is 8,16,32 or 64.
And the present invention also provides the control method of the independent control circuit of the many bits of a kind of bus, comprise the above-mentioned independent control circuit of the many bits of a kind of bus for controlling, be specially to send and control data, whether effectively described control packet contains control bit, and whether effectively whether described control bit effective for controlling the port controlling position of described control data.
Further, whether effectively the figure place of described control bit identical with the figure place of port controlling position.
Further, the width of described control data is 8,16,32 or 64.
Tool of the present invention has the following advantages:
1, hardware is realized, and operating rate is fast;
2, do not need the software intervention such as address space lock operation, system effectiveness is high;
3, control method is simply clear, and has guaranteed the correctness of operation.
Accompanying drawing explanation
Fig. 1 is the circuit diagram of the preferred embodiment of control circuit of the present invention.
Embodiment
Refer to Fig. 1, by describing technology contents of the present invention, structural attitude in detail, being realized object and effect, below in conjunction with embodiment and coordinate accompanying drawing to be explained in detail.
As shown in Figure 1, the invention provides the independent control circuit of the many bits of a kind of bus, comprise logical operation circuit 1, current control bit state input interface, control bit input interface, port controlling position input interface and final control bit State-output interface whether effectively, current control bit state input interface, effectively whether control bit input interface, port controlling position input interface and final control bit State-output interface are connected with logical operation circuit 1.
Logical operation circuit 1 is when whether, effectively control bit enables, and output port control bit on final control bit State-output interface when effectively control bit deenergizes whether, is being exported current control bit state on final control bit State-output interface.
Foregoing circuit can be applicable in the control of a port of total line traffic control of SOC chip, the current control bit state input interface therewith state output end of port connects, effectively whether control bit input interface, port controlling position input interface are connected with bus control input end, and the final control bit State-output interface therewith control end of port connects.User is in the time of a write operation, if do not want to control this port, the whether effectively control bit of this port write 0(when enabling level as high level is as example), port controlling position can be arbitrary value, logical operation circuit 1 of the present invention can detect whether effectively control bit is to deenergize, can export at final control bit State-output interface the current state of this port, keep the current state of this port not change, avoided software to go to read the state of this port or the address area of removing to lock this port.
Logical operation circuit 1 can have multiple implementation, simultaneously above-mentioned level when effectively whether control bit enables can be high level or low level, in the time being high level, logical operation circuit 1 can be specially as shown in Figure 1: comprise phase inverter 10, first with door 11, second with door 12 and or door 13, whether effectively control bit input interface and second and an input end of 12, the input end of phase inverter 10 connects, port controlling position input interface is connected with another input end of door 12 with second, the output terminal of phase inverter 10 is connected with an input end of door 11 with first, first is connected with current control bit state input interface with another input end of door 11, first with door 11 output terminal with or an input end of 13 be connected, second with door 12 output terminal with or another input end of 13 be connected, or the output terminal of door 13 is connected with final control bit State-output interface.
In above-mentioned physical circuit, when whether when, effectively control bit is high level, or the output of the output terminal of door 13 is the level of port controlling position, and when whether when, effectively control bit is low level, or the output of the output terminal of door 13 is the level of current control bit state.
And the present invention also provides the method for designing of the independent control circuit of the many bits of a kind of bus, for chip design, comprise the steps:
First be whether effectively control bit of the port controlling position increase in control data controlling in data;
Then use hardware logic electric circuit, in the time receiving control data, whether effectively the corresponding port controlling of the control bit position of deenergizing in control data is replaced with to the current state of the port that will control port controlling position, then control data are sent to port.The hardware logic electric circuit here can be made up of by the independent control circuit of many bits above-mentioned bus.When concrete application, whether effectively the figure place of control bit can be identical with the figure place of port controlling position, also can be different.At chip field, the width of common control data is 8,16,32 or 64.To control the width of data as 32, effectively whether the figure place of control bit is high 16 below, and port controlling position is low 16, and the level position high level that enables of controlling data is that example describes the design's method.
Port controlling position is low 16, and 16 ports can be controlled in this port controlling position of 16, and whether the whether effectively control bit of high 16 is effective for controlling the port controlling position of low 16.The high speed that uses hardware logic electric circuit to carry out budget and can guarantee computing, avoids after port status changes or sends the port status before changing.Hardware logic electric circuit is received respectively on the state end of the control data input pin of 32, above-mentioned 16 bit ports and the control bus of above-mentioned 16 bit ports.Now, take the control data of 32 received as 0x00035555, the state of the port of 16 is that 0xC0C0 is example, and effectively whether control bit is 0x0003, and port controlling position is 0x5555.Only having the control bit of last two whether is effectively 1, and 14 whether effective control bits are all 0 above, and state deenergizes.By before port controlling position 14 replace to the current state of this 14 bit port, and two invariant positions after retaining are: 0xC0C1, and send to the control bus of above-mentioned 16 bit ports.The chip of designing by the design's method, user needn't consider the state of other ports of not controlling, do not spend lock address or remove read port state, only whether the port of not wanting to control effectively need to be set to 0 on control bit at it, greatly having simplified software flow yet.
And on the basis of above-mentioned method for designing, the present invention also provides the control method of the independent control circuit of the many bits of a kind of bus, comprise the above-mentioned independent control circuit of the many bits of a kind of bus for controlling, be specially to send and control data, control packet and whether effectively contain control bit, effectively whether whether control bit is effective for controlling the port controlling position of described control data.Whether effectively the figure place of control bit and the figure place of port controlling position can be identical also can be different, when identical, make user more easily remember.The width of common control data is 8,16,32 or 64.
The foregoing is only embodiments of the invention; not thereby limit the scope of the claims of the present invention; every equivalent structure or conversion of equivalent flow process that utilizes instructions of the present invention and accompanying drawing content to do; or be directly or indirectly used in other relevant technical fields, be all in like manner included in scope of patent protection of the present invention.
Claims (9)
1. the independent control circuit of the many bits of bus, it is characterized in that: comprise logical operation circuit, current control bit state input interface, control bit input interface, port controlling position input interface and final control bit State-output interface whether effectively, described current control bit state input interface, effectively whether control bit input interface, port controlling position input interface and final control bit State-output interface are connected with logical operation circuit;
Described logical operation circuit is when whether, effectively control bit enables, output port control bit on final control bit State-output interface, when effectively control bit deenergizes whether, on final control bit State-output interface, export current control bit state.
2. the independent control circuit of the many bits of a kind of bus according to claim 1, is characterized in that: described whether effectively level when control bit enables be high level.
3. the independent control circuit of the many bits of a kind of bus according to claim 1, it is characterized in that: described logical operation circuit comprises phase inverter, first with door, second with door and or door, described whether effectively control bit input interface with second and an input end, the input end of phase inverter connects, described port controlling position input interface is connected with another input end of door with second, the output terminal of described phase inverter is connected with an input end of door with first, described first is connected with current control bit state input interface with another input end of door, described first with the output terminal of door with or an input end be connected, described second with the output terminal of door with or another input end be connected, output terminal described or door is connected with final control bit State-output interface.
4. a method for designing for the independent control circuit of the many bits of bus, for chip design, is characterized in that: comprise the steps:
First be whether effectively control bit of the port controlling position increase in control data controlling in data;
Then use hardware logic electric circuit, in the time receiving control data, whether effectively the corresponding port controlling of the control bit position of deenergizing in control data is replaced with to the current state of the port that will control port controlling position, then control data are sent to port.
5. the method for designing of the independent control circuit of the many bits of a kind of bus according to claim 4, is characterized in that: whether effectively the figure place of described control bit identical with the figure place of port controlling position.
6. the method for designing of the independent control circuit of the many bits of a kind of bus according to claim 4, is characterized in that: the width of described control data is 8,16,32 or 64.
7. the control method of the independent control circuit of the many bits of bus, for controlling the circuit comprising as claim 1 or 2, it is characterized in that: comprise and send the step of controlling data, whether effectively described control packet contains control bit, and whether effectively whether described control bit effective for controlling the port controlling position of described control data.
8. the control method of the independent control circuit of the many bits of a kind of bus according to claim 7, is characterized in that: whether effectively the figure place of described control bit identical with the figure place of port controlling position.
9. the control method of the independent control circuit of the many bits of a kind of bus according to claim 7, is characterized in that: the width of described control data is 8,16,32 or 64.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201410081664.5A CN103810132A (en) | 2014-03-07 | 2014-03-07 | Bus multi-bit separate control circuit and design and control method thereof |
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| CN201410081664.5A CN103810132A (en) | 2014-03-07 | 2014-03-07 | Bus multi-bit separate control circuit and design and control method thereof |
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| US4200865A (en) * | 1977-02-02 | 1980-04-29 | Hitachi, Ltd. | Printed circuit board capable of being inserted and withdrawn on on-line status |
| CN101521041A (en) * | 2009-04-01 | 2009-09-02 | 北京泰科源科技有限责任公司 | Control circuit system based on nand gate structure memory |
| CN101727087A (en) * | 2009-12-04 | 2010-06-09 | 湖南大学 | 8-bit logic circuit for rapid replenishment |
| CN102036305A (en) * | 2009-09-30 | 2011-04-27 | 华为技术有限公司 | Transmitting method and receiving method of control information, devices and communication system |
| CN102662902A (en) * | 2012-03-30 | 2012-09-12 | 中兴通讯股份有限公司 | Method, device and system for preventing I2C (inter-integrated circuit) bus locking |
-
2014
- 2014-03-07 CN CN201410081664.5A patent/CN103810132A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4200865A (en) * | 1977-02-02 | 1980-04-29 | Hitachi, Ltd. | Printed circuit board capable of being inserted and withdrawn on on-line status |
| CN101521041A (en) * | 2009-04-01 | 2009-09-02 | 北京泰科源科技有限责任公司 | Control circuit system based on nand gate structure memory |
| CN102036305A (en) * | 2009-09-30 | 2011-04-27 | 华为技术有限公司 | Transmitting method and receiving method of control information, devices and communication system |
| CN101727087A (en) * | 2009-12-04 | 2010-06-09 | 湖南大学 | 8-bit logic circuit for rapid replenishment |
| CN102662902A (en) * | 2012-03-30 | 2012-09-12 | 中兴通讯股份有限公司 | Method, device and system for preventing I2C (inter-integrated circuit) bus locking |
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Address after: 350000 Fuzhou Gulou District, Fujian, software Avenue, building 89, No. 18 Applicant after: FUZHOU ROCKCHIP ELECTRONICS CO., LTD. Address before: 350000 Fuzhou Gulou District, Fujian, software Avenue, building 89, No. 18 Applicant before: Fuzhou Rockchip Semiconductor Co., Ltd. |
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Application publication date: 20140521 |