CN109884612A - A kind of burst length compression method of multi-channel single photon avalanche diode detector - Google Patents
A kind of burst length compression method of multi-channel single photon avalanche diode detector Download PDFInfo
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- CN109884612A CN109884612A CN201910174228.5A CN201910174228A CN109884612A CN 109884612 A CN109884612 A CN 109884612A CN 201910174228 A CN201910174228 A CN 201910174228A CN 109884612 A CN109884612 A CN 109884612A
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- 230000006835 compression Effects 0.000 title claims abstract description 25
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- 238000010791 quenching Methods 0.000 claims abstract description 37
- 230000000171 quenching effect Effects 0.000 claims abstract description 36
- 238000001514 detection method Methods 0.000 claims abstract description 7
- 230000003111 delayed effect Effects 0.000 claims description 4
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Abstract
The invention discloses a kind of burst length compression methods of multi-channel single photon avalanche diode detector, specifically: multichannel single-photon avalanche diode forms detection array, it is mutually indepedent between every road single-photon avalanche diode, and every road single-photon avalanche diode quenching circuit is connect with burst length compressor circuit all the way respectively；Every road single-photon avalanche diode generates wide pulse signal all the way by the effect of corresponding quenching circuit, and wide pulse signal carries out burst length compression by burst length compressor circuit again, generates narrow pulse signal all the way；Multichannel is merged into bus all the way through burst length compressed narrow pulse signal and externally exports as a pixel by bus circuit.Method of the invention can effectively avoid multi-channel single photon avalanche diode detector because that can not differentiate per signal caused by dead time is too long to bus holding time all the way, signal is failed to judge the problems such as judging by accident, while the transmission bandwidth of signal in bus can be improved.
Description
Technical field
The invention belongs to semiconductor light electro-technical fields, more particularly to a kind of arteries and veins of single photon avalanche diode detector
Rush time compression method.
Background technique
Single-photon avalanche diode has the characteristics that high-gain is highly sensitive as a kind of novel photodetector,
Application prospect is boundless, laser radar technique, conventional two-dimensional imaging technique, compressed sensing imaging including unmanned field
Technology etc..However, single single-photon avalanche diode is highly prone to secretly when being detected as pixel in laser radar field
The influence of the noise factors such as counting, environment light, ideal solution are formed using multiple single-photon avalanche diodes
Multi channel detector；Similarly, in compressed sensing imaging applications, multi channel detector is needed each two pole of road single-photon avalanche
The pulse signal that pipe detection photon generates, which is compressed in a bus, externally to be exported.
The pulse signal that single single-photon avalanche diode generates has certain width, and pulsewidth is primarily limited to be quenched
Circuit to avalanche breakdown be quenched and recovery time, single-photon avalanche diode is can not to carry out photon detection in this period
, referred to as dead time.When multichannel single-photon avalanche diode is compressed to output signal on the way, biggish dead time is led
The road Zhi Mei pulse signal occupies the overlong time of bus, is easy to obscure multiple signals together, can not clearly be differentiated.Mesh
Before, the dead time of common quenching circuit is generally in 10ns or more；Specially designed quenching circuit can further decrease dead zone
Time, but circuit structure can be more complicated, and chip area accounting is larger, and it is integrated to be unfavorable for array.
To sum up, it is the advantage for preferably playing multi-channel single photon avalanche diode detector, needs a kind of burst length
Compression method is input in a bus after the pulse signal of every road single-photon avalanche diode is carried out effective width compression,
Synthesis externally output all the way.
Summary of the invention
The present invention is directed to the application demand of above-mentioned multi-channel single photon avalanche diode detection, provides a kind of multichannel monochromatic light
The burst length compression method of sub- avalanche diode detector, this method can be by multichannel single-photon avalanche diodes, quenching circuit
And burst length compressor circuit effective integration, and by bus circuit will be compressed and multiplexed after pulse signal be incorporated on the way
Output.
The technical solution adopted by the present invention are as follows:
A kind of burst length compression method of multi-channel single photon avalanche diode detector, including two pole of single-photon avalanche
Pipe, quenching circuit, burst length compressor circuit and bus circuit, which is characterized in that single-photon avalanche diode described in multichannel
Detection array is formed, it is mutually indepedent between every road single-photon avalanche diode, and every road single-photon avalanche diode quenching circuit
It is connect respectively with burst length compressor circuit all the way；Every road single-photon avalanche diode is acted on by corresponding quenching circuit
Wide pulse signal all the way is generated, wide pulse signal carries out burst length compression by burst length compressor circuit again, generates narrow all the way
Pulse signal；Multichannel is merged into bus all the way through burst length compressed narrow pulse signal as one by the bus circuit
A pixel externally exports.
Further, the quenching circuit is using active quenching circuit, passive quenching circuit or gate quenching circuit.
Preferably, resistance is quenched as passive using single NMOS tube in the passive quenching circuit.
Further, the burst length compressor circuit is delayed after reverse phase using input signal and is made with input signal itself
The circuit structure of "AND" processing.
Preferably, the burst length compressor circuit includes delay phase inverter and AND logic circuit, the delay reverse phase
Device by input signal make delay and reverse phase handle, the AND logic circuit by be delayed reverse phase after signal and input signal itself
Make "AND" processing, obtains burst length compressed narrow pulse signal, the burst length of the narrow pulse signal is by the delay
The delay of phase inverter determines.
Further, the bus circuit is merged multichannel narrow pulse signal by "or" logic using multistage OR-gate
Onto a bus；Alternatively, every road narrow pulse signal is separately input to open-drain out gate electricity all the way by the bus circuit
The input terminal on road, the drain terminal of every road open-drain out-gate circuit, which is all connected, is used as total line output terminal, total line output terminal
Power supply is pulled upward to by pull-up resistor.
The invention has the benefit that
(1) present invention merges into multichannel single-photon avalanche diode exports all the way, can overcome single channel single-photon avalanche two
The problems such as photosurface is smaller in pole pipe detection, and the noises such as dark counting can not be differentiated.
(2) merge output after the present invention is compressed multiplex pulse signal, can effectively avoid multi-channel single photon snowslide
Mistake that diode detector per signal caused by dead time is too long to bus holding time all the way because that can not differentiate, signal is failed to judge
The problems such as sentencing improves the resolution capability for the signal that multichannel single-photon avalanche diode was generated adjacent to the time, signal in raising bus
Transmission bandwidth.
(3) passive quenching circuit can be using single metal-oxide-semiconductor as being passively quenched resistance, and circuit structure is simple and version
Figure area occupied is smaller, convenient for being closely integrated.
Detailed description of the invention
Fig. 1 is a kind of burst length compression method of multi-channel single photon avalanche diode detector in the embodiment of the present invention
Circuit frame schematic diagram.
Fig. 2 is single channel single-photon avalanche diode and quenching circuit structural schematic diagram in the embodiment of the present invention.
Fig. 3 is a kind of burst length compressor circuit (a) circuit structure and (b) time diagram in the embodiment of the present invention.
Fig. 4 is that another burst length compressor circuit (a) circuit structure and (b) timing are illustrated in the embodiment of the present invention
Figure.
Fig. 5 is a kind of bus circuit structural schematic diagram in the embodiment of the present invention.
Fig. 6 is another bus circuit structural schematic diagram in the embodiment of the present invention.
Specific embodiment
Technical solution of the present invention is described in further detail below in conjunction with the drawings and specific embodiments, described tool
Body embodiment is only explained the present invention, is not used in the limitation present invention.
The present invention provides a kind of burst length compression method of multi-channel single photon avalanche diode detector, Fig. 1 is
Whole circuit frame schematic diagram.Include following core in legend:
101 form of array is formed by multichannel single-photon avalanche diode 102, between multichannel single-photon avalanche diode 102
Independently of each other, each array 101 corresponds to a sensing point.The specific number of single-photon avalanche diode 102 is unrestricted, battle array
The composition form of column 101 is also unrestricted, and such as 2 × 2,2 × 3 etc., 3 × 3 array format is used in the present embodiment；
Multichannel quenching circuit 103, every road quenching circuit match single-photon avalanche diode 102 all the way respectively, are responsible for respective
Single-photon avalanche diode 102 is quenched and restores；Every road single-photon avalanche diode is made by corresponding quenching circuit
With generating wide pulse signal all the way.The circuit form of quenching circuit 103 can have a multiplicity, for example active quenching circuit, passively quench
Go out circuit and gate quenching circuit etc., and for the ease of being closely integrated, structure is simple and domain area occupied is lesser is passively quenched
Circuit has great advantages, but is also not limited to passive quenching circuit；
Multiplex pulse time compression circuit 104, the pulse signal exported for compressing respective quenching circuit 103,
Generate narrow pulse signal all the way.Burst length compressor circuit major function is by longer pulse signal (such as 10ns of pulse width
The pulse signal of the above pulsewidth) it is compressed into the shorter pulse signal of pulse width (pulse signal of such as 1ns or so pulsewidth), electricity
Road way of realization can there are many, including but not limited to: with input signal itself making "AND" processing after input signal delay reverse phase
Circuit structure, circuit structure mainly includes delay phase inverter and AND logic circuit, and delay phase inverter makees input signal
Delay and reverse phase processing, AND logic circuit by be delayed reverse phase after signal and input signal itself make "AND" processing, obtain arteries and veins
Time compressed narrow pulse signal is rushed, the narrow pulse signal burst length is determined by the delay of delay phase inverter；
Bus circuit 105, will be compressed and multiplexed after pulse signal be integrated into a bus, final realize has with single
Higher bandwidth bus 106 is as output.Bus circuit 105 can realize that including but not limited to: use is more by a variety of circuit structures
Grade OR-gate, all narrow pulse signals are merged into a bus by "or" logic；Alternatively, using OD work " lines of multichannel
With " every road narrow pulse signal is specifically input to corresponding OD input terminal by logical process, OD drain terminals described in every road are whole
It is connected and is used as total line output terminal, total line output terminal is pulled upward to power supply by pull-up resistor.
Fig. 2 is single channel single-photon avalanche diode and quenching circuit structural schematic diagram in one embodiment of the invention.This reality
It applies, chip area the smallest single NMOS tube 203 most simple using structure in example and is used as passive quenching circuit, NMOS tube 203
The conduct of source and drain resistance is quenched resistance and connects with single-photon avalanche diode 202, and the grid of NMOS tube 203 is used as input terminal 201
In reception input voltage Vq, and pass through different VqValue adjusts the resistance value of source and drain resistance, i.e., the resistance value of resistance is passively quenched.Single photon
The anode of avalanche diode 202, which connects, is quenched resistance simultaneously while as the external output signal of output end 204, and cathode meets a VhvHeight
Pressure, the voltage value are greater than the avalanche breakdown point of single-photon avalanche diode.Although passive quenching circuit needs longer recovery
Between, cause dead time longer, but due to the introducing of succeeding impulse time compression circuit, longer dead time is can to tolerate
's；On the contrary, its simple circuit structure can reduce chip area instead at a big advantage, be conducive to integrate in an array.
Fig. 3 is a kind of circuit structure and time diagram of burst length compressor circuit in the embodiment of the present invention.The arteries and veins
The structure for rushing time compression circuit includes input terminal 301, delay phase inverter 302, AND gate circuit 303 and output end 304.Its
In, input terminal 301 is used to receive the wide pulse signal of quenching circuit output, which is directly connected to AND gate electricity all the way
The end input terminal A on road 303, another way are input to the end input terminal B of AND gate circuit 303, the end A, B by delay phase inverter 302
Signal exports burst length compressed pulse letter after AND gate circuit 303 makees "AND" logical process, in output end 304
Number.The waveform situation on tri- tunnel A, B, O is described in detail in timing diagram 305, and the end A is a broad pulse letter identical with input terminal 301
Number, the end B is the delay of A end signal and negates signal, and the end O is that A, B end signal make the signal after "AND" logic.Pass through above-mentioned pulse
Time compression circuit, the broad pulse of input terminal 301 are finally compressed into the burst pulse of output end 304, and the arteries and veins of final burst pulse
Rushing width can be designed as desired, and when design need to only adjust the delay time of delay phase inverter 302.
Fig. 4 is the circuit structure and time diagram of another burst length compressor circuit in the embodiment of the present invention.It is described
The structure of burst length compressor circuit includes input terminal 401, preceding phase inverter 402, NMOS-PMOS pipe to 403, or gate circuit
404, rear phase inverter 405 and output end 406.Input terminal 401 is used to receive the wide pulse signal of quenching circuit output；The width arteries and veins
It rushes after premenstrual 402 reverse phase of phase inverter of signal and inputs the end input terminal B of or gate circuit 404 all the way, another way acts on NMOS-
PMOS tube is on 403 NMOS tube grid, and NMOS tube source ground connection, drain terminal are connected with PMOS tube drain terminal as output, and output connects
It is connected to the end input terminal A of or gate circuit 404；404 output end C-terminal of or gate circuit is connected to NMOS-PMOS pipe to 403
On PMOS tube grid, PMOS source end connects electric source and drain and connects with draining end of NMOS tube, and 404 output end C-terminal of or gate circuit is simultaneously
It is connected to the input terminal of rear phase inverter 405；The output of phase inverter 405 is output end 406 afterwards.Timing diagram 407 is described in detail respectively
The waveform situation on road, including the end I, the end B, the end A, C-terminal and the end O.The end I is the wide pulse signal that input terminal 401 inputs；The end B is I
Hold the anti-of wide pulse signal；A end signal is relatively complicated, by NMOS-PMOS pipe to 403 common modulation: when the end B be height
When, NMOS tube is in the open state, the end A pull down to be low, A, B end signal C-terminal after "or" logic are height at this time；Work as B
When end is lower, the end A keeps low level, and A, B end signal C-terminal after "or" logic are low at this time, and PMOS tube is opened, on the end A
Power supply is drawn to get higher, the C-terminal after "or" logic is also got higher；C-terminal signal generates in the variation by above-mentioned A end signal, negative for one
To burst pulse；The end O is the reverse phase of C-terminal signal, is final narrow pulse signal.It is defeated by above-mentioned burst length compressor circuit
The broad pulse for entering end 401 is finally compressed into the burst pulse of output end 406, and the pulse width of final burst pulse be can be according to
What demand was designed, when design, need to only adjust NMOS-PMOS pipe to the grid length ratio of PMOS tube in 403.
Fig. 5 is a kind of bus circuit structural schematic diagram in the embodiment of the present invention.The bus circuit is mainly opened using drain electrode
Multiple signals are connected to a bus by " line with " logic by road out-gate circuit (Open-Drain Output, OD) structure
On.The bus circuit includes input terminal 501, NMOS tube 502, PMOS tube 503 and output end 504.Multiple input terminals 501 are used for
Receive the narrow pulse signal of multiplex pulse time compression circuit output；NMOS tube 502 uses the connection of open-drain, i.e. source connects
Ground, grid is as input terminal, and drain terminal is as output end；PMOS tube 503 is used as pull-up resistor, and source and grid connect power supply, drain terminal
It is connected with the drain terminal of all NMOS tubes 502, realizes " line with " logic；Output end 504 is bus output.Specific implementation process
In, the input terminal number of bus circuit is matched according to the number that front end exports, and is not specifically limited, but it is noted that PMOS tube
With the design of the respective breadth length ratio of NMOS tube.
Fig. 6 is another bus circuit structural schematic diagram in the embodiment of the present invention.The bus circuit mainly uses "or"
Multiple signals are connected in a bus by logical construction.The bus circuit includes input terminal 601, level-one OR-gate 602, two
Grade OR-gate 603 and output end 604.Multiple input terminals 601 are used to receive the burst pulse of multiplex pulse time compression circuit output
Signal；Multiple input signals after grouping are made "or" logical process by multiple level-one OR-gates 602；Second level OR-gate 603 will be more
The output signal of a level-one OR-gate 602 makees "or" logical process；Output end 604 is all signals after "or" logical process
Final output.In specific implementation process, the input terminal number of bus circuit is matched according to the number that front end exports；OR-gate
Whether it is classified using level-one with second level, or even with no restriction using the number of three-level OR-gate and OR-gate at different levels,
It is determined according to specific requirements.
Claims (6)
1. a kind of burst length compression method of multi-channel single photon avalanche diode detector, including two pole of single-photon avalanche
Pipe, quenching circuit, burst length compressor circuit and bus circuit, which is characterized in that single-photon avalanche diode described in multichannel
Detection array is formed, it is mutually indepedent between every road single-photon avalanche diode, and every road single-photon avalanche diode quenching circuit
It is connect respectively with burst length compressor circuit all the way；Every road single-photon avalanche diode is acted on by corresponding quenching circuit
Wide pulse signal all the way is generated, wide pulse signal carries out burst length compression by burst length compressor circuit again, generates narrow all the way
Pulse signal；Multichannel is merged into bus all the way through burst length compressed narrow pulse signal as one by the bus circuit
A pixel externally exports.
2. a kind of burst length compression method of multi-channel single photon avalanche diode detector according to claim 1,
It is characterized in that, the quenching circuit is using active quenching circuit, passive quenching circuit or gate quenching circuit.
3. a kind of burst length compression method of multi-channel single photon avalanche diode detector according to claim 2,
It is characterized in that, resistance is quenched as passive using single NMOS tube in the passive quenching circuit.
4. a kind of burst length compression method of multi-channel single photon avalanche diode detector according to claim 1,
It is characterized in that, the burst length compressor circuit makees "AND" processing with input signal itself using after input signal delay reverse phase
Circuit structure.
5. a kind of burst length compression method of multi-channel single photon avalanche diode detector according to claim 4,
It is characterized in that, the burst length compressor circuit includes delay phase inverter and AND logic circuit, the delay phase inverter will
Input signal makees delay and reverse phase processing, and the AND logic circuit makees the signal after the reverse phase that is delayed with input signal itself
"AND" processing obtains burst length compressed narrow pulse signal, and the burst length of the narrow pulse signal is anti-by the delay
The delay of phase device determines.
6. a kind of burst length compression method of multi-channel single photon avalanche diode detector according to claim 1,
It is characterized in that, multichannel narrow pulse signal is merged into one by "or" logic using multistage OR-gate by the bus circuit
In bus；Alternatively, every road narrow pulse signal is separately input to the defeated of open-drain out-gate circuit all the way by the bus circuit
Enter end, the drain terminal of every road open-drain out-gate circuit, which is all connected, is used as total line output terminal, and total line output terminal is by pulling up
Resistance is pulled upward to power supply.
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| CN112782714A (en) * | 2021-01-05 | 2021-05-11 | 广东博智林机器人有限公司 | Pulse signal processing circuit and laser radar |
| CN113534107A (en) * | 2020-04-22 | 2021-10-22 | 上海禾赛科技有限公司 | Detection circuit with adjustable output pulse width, receiving unit and laser radar |
| CN113671466A (en) * | 2021-08-10 | 2021-11-19 | 南京大学 | SPAD array suitable for compressed sensing |
| CN113687332A (en) * | 2021-07-08 | 2021-11-23 | 西安电子科技大学 | Analog front-end circuit based on capacitor array voltage synthesis technology in laser radar |
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