CN109884612B - Pulse time compression method of multichannel single photon avalanche diode detector - Google Patents
Pulse time compression method of multichannel single photon avalanche diode detector Download PDFInfo
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Abstract
The invention discloses a pulse time compression method of a multichannel single photon avalanche diode detector, which comprises the following steps: the detection array is formed by a plurality of paths of single photon avalanche diodes, each path of single photon avalanche diodes are mutually independent, and each path of single photon avalanche diode quenching circuit is respectively connected with one path of pulse time compression circuit; each path of single photon avalanche diode generates a path of wide pulse signal under the action of a corresponding quenching circuit, and the wide pulse signal is subjected to pulse time compression by a pulse time compression circuit to generate a path of narrow pulse signal; the bus circuit combines the multi-path narrow pulse signals compressed by pulse time to one bus as one pixel point to be output. The method can effectively avoid the problems of indistinguishable signals, misjudgment of signal missing judgment and the like caused by overlong bus occupation time of each path of dead time of the multichannel single photon avalanche diode detector, and can improve the transmission bandwidth of signals on the bus.
Description
Technical Field
The invention belongs to the technical field of semiconductor photoelectricity, and particularly relates to a pulse time compression method of a single photon avalanche diode detector.
Background
The single photon avalanche diode as one new type of photoelectric detector has high gain, high sensitivity and other features, and has very wide application foreground including laser radar technology, traditional two-dimensional imaging technology, compressed sensing imaging technology, etc. However, in the laser radar field, when a single photon avalanche diode is used as a pixel point to detect, the single photon avalanche diode is extremely susceptible to noise factors such as dark count, ambient light and the like, and a more ideal solution is to adopt a plurality of single photon avalanche diodes to form a multichannel detector; similarly, in compressed sensing imaging applications, the multi-channel detector needs to compress pulse signals generated by the detected photons of each path of single photon avalanche diode onto a bus for external output.
The pulse signal generated by the single photon avalanche diode has a certain width, and the pulse width is mainly limited by the quenching and recovery time of the quenching circuit to the avalanche breakdown, and the single photon avalanche diode cannot detect photons during the time, which is called dead time. When the multipath single photon avalanche diode is compressed to output signal on the way, the longer dead time leads to that each path of pulse signal occupies too long bus, so that the multipath signals are easily mixed together and cannot be clearly distinguished. At present, dead time of a common quenching circuit is generally more than 10 ns; the dead time can be further reduced by the quenching circuit with special design, but the circuit structure is complex, the layout area is large, and the array integration is not facilitated.
To sum up, in order to better play the advantages of the multichannel single photon avalanche diode detector, a pulse time compression method is needed, and pulse signals of each channel of single photon avalanche diode are compressed in effective width and then input to a bus to be combined into one channel for external output.
Disclosure of Invention
Aiming at the application requirement of the multichannel single photon avalanche diode detection, the invention provides a pulse time compression method of the multichannel single photon avalanche diode detector, which can effectively integrate a plurality of channels of single photon avalanche diodes, a quenching circuit and a pulse time compression circuit and integrate and output the pulse signals after the multiplexing on the way through a bus circuit.
The invention adopts the technical scheme that:
the pulse time compression method of the multichannel single photon avalanche diode detector comprises single photon avalanche diodes, a quenching circuit, a pulse time compression circuit and a bus circuit, and is characterized in that a detection array is formed by a plurality of single photon avalanche diodes, each single photon avalanche diode is mutually independent, and each single photon avalanche diode quenching circuit is respectively connected with one pulse time compression circuit; each path of single photon avalanche diode generates a path of wide pulse signal under the action of a corresponding quenching circuit, and the wide pulse signal is subjected to pulse time compression by a pulse time compression circuit to generate a path of narrow pulse signal; and the bus circuit combines the multi-path narrow pulse signals subjected to pulse time compression onto one bus to serve as one pixel point to be output outwards.
Further, the quenching circuit adopts an active quenching circuit, a passive quenching circuit or a gate-controlled quenching circuit.
Preferably, a single NMOS tube is adopted as the passive quenching resistor in the passive quenching circuit.
Further, the pulse time compression circuit adopts a circuit structure that the input signal is delayed and inverted and then is subjected to AND processing with the input signal.
Preferably, the pulse time compression circuit comprises a delay inverter and an and logic circuit, the delay inverter delays and inverts an input signal, the and logic circuit performs an and process on the delayed and inverted signal and the input signal to obtain a narrow pulse signal after pulse time compression, and the pulse time of the narrow pulse signal is determined by the delay of the delay inverter.
Further, the bus circuit adopts a multi-stage OR gate to combine multiple paths of narrow pulse signals onto one bus through OR logic; or the bus circuit inputs each path of narrow pulse signal to the input end of one path of drain electrode open-circuit output gate circuit respectively, all the drain ends of each path of drain electrode open-circuit output gate circuit are connected to be used as bus output ends, and the bus output ends are pulled up to a power supply by a pull-up resistor.
The beneficial effects of the invention are as follows:
(1) The invention combines the multiple single photon avalanche diodes into one output, and can solve the problems of small photosurface, indistinguishable noise such as dark count and the like in the detection of the single photon avalanche diode.
(2) The multi-channel single photon avalanche diode detector can effectively avoid the problems of indistinguishable signals, misjudgment of signal missing judgment and the like caused by overlong bus occupation time caused by dead time of each channel, improves the resolving power of signals generated by adjacent time of the multi-channel single photon avalanche diode, and improves the transmission bandwidth of signals on the bus.
(3) The passive quenching circuit can adopt a single MOS tube as a passive quenching resistor, and has simple circuit structure, small layout occupation area and convenient tight integration.
Drawings
Fig. 1 is a schematic circuit diagram of a pulse time compression method of a multichannel single photon avalanche diode detector in an embodiment of the invention.
FIG. 2 is a schematic diagram of a single-pass single photon avalanche diode and quenching circuit in accordance with an embodiment of the present invention.
Fig. 3 is a schematic diagram of (a) a circuit structure and (b) a timing sequence of a pulse time compression circuit according to an embodiment of the present invention.
FIG. 4 is a schematic diagram of the circuit structure (a) and the timing sequence (b) of another pulse time compression circuit according to the embodiment of the present invention.
FIG. 5 is a schematic diagram of a bus circuit according to an embodiment of the invention.
FIG. 6 is a schematic diagram of another bus circuit configuration in an embodiment of the invention.
Detailed Description
The technical solution of the present invention will be described in further detail below with reference to the accompanying drawings and specific embodiments, which are only illustrative of the present invention and are not intended to limit the present invention.
The invention provides a pulse time compression method of a multichannel single photon avalanche diode detector, and fig. 1 is a schematic diagram of an overall circuit frame. The legend comprises the following core parts:
the array 101 is formed by multiple single photon avalanche diodes 102, and the multiple single photon avalanche diodes 102 are independent, and each array 101 corresponds to a detection point. The specific number of the single photon avalanche diodes 102 is not limited, and the composition form of the array 101 is not limited, such as 2×2,2×3, etc., and in this embodiment, a 3×3 array form is adopted;
the multi-path quenching circuit 103 is respectively matched with one path of single photon avalanche diode 102 and is responsible for quenching and recovering the single photon avalanche diode 102; each path of single photon avalanche diode generates a path of wide pulse signal through the action of the corresponding quenching circuit. The circuit form of the quenching circuit 103 can be various, such as an active quenching circuit, a passive quenching circuit, a gate-controlled quenching circuit and the like, and in order to facilitate compact integration, the passive quenching circuit with a simple structure and a small layout occupation area has a great advantage, but is not limited to the passive quenching circuit;
the multipath pulse time compression circuit 104 is used for compressing the pulse signals output by the respective quenching circuits 103 to generate a path of narrow pulse signals. The pulse time compression circuit mainly has the function of compressing a pulse signal with a longer pulse width (for example, a pulse signal with a pulse width of more than 10 ns) into a pulse signal with a shorter pulse width (for example, a pulse signal with a pulse width of about 1 ns), and various circuit implementation forms can be realized, including but not limited to: the circuit structure mainly comprises a delay inverter and an AND logic circuit, wherein the delay inverter delays and inverts the input signal, the AND logic circuit performs AND processing on the delayed and inverted signal and the input signal to obtain a narrow pulse signal with compressed pulse time, and the pulse time of the narrow pulse signal is determined by the delay of the delay inverter;
the bus circuit 105 integrates the multiplexed compressed pulse signals onto a bus, and finally achieves output with a single bus 106 having a higher bandwidth. The bus circuit 105 may be implemented by a variety of circuit structures including, but not limited to: combining all narrow pulse signals onto a bus through OR logic by adopting a multi-stage OR gate; or adopting a plurality of paths of OD gates as the AND logic processing, specifically, inputting each path of narrow pulse signals to the input end of the corresponding OD gate, wherein all the drain ends of each path of OD gates are connected to serve as bus output ends, and the bus output ends are pulled up to a power supply by a pull-up resistor.
Fig. 2 is a schematic diagram of a single-pass single photon avalanche diode and quenching circuit in accordance with one embodiment of the present invention. In this embodiment, a single NMOS 203 with the simplest structure and the smallest layout area is used as a passive quenching circuit, the source-drain resistance of the NMOS 203 is used as a quenching resistor and connected in series with a single photon avalanche diode 202, and the gate of the NMOS 203 is used as an input terminal 201 for receiving an input voltage V q And is combined withBy different V q The value of the source-drain resistor is regulated, namely the resistance of the passive quenching resistor. The anode of the single photon avalanche diode 202 is connected with the quenching resistor and simultaneously serves as an output end 204 to output signals externally, and the cathode is connected with a V hv The voltage value is greater than the avalanche breakdown point of a single photon avalanche diode. Although the passive quenching circuit requires a longer recovery time, resulting in a longer dead time, the longer dead time is tolerable due to the introduction of the subsequent pulse time compression circuit; in contrast, the simple circuit structure of the array has the advantages of reducing the layout area and being beneficial to integration in the array.
Fig. 3 is a circuit structure and a timing diagram of a pulse time compression circuit according to an embodiment of the invention. The pulse time compression circuit comprises an input terminal 301, a delay inverter 302, an AND gate 303 and an output terminal 304. The input terminal 301 is configured to receive a wide pulse signal output by the quenching circuit, where one path of the wide pulse signal is directly connected to the input terminal a of the and gate 303, and the other path of the wide pulse signal is input to the input terminal B of the and gate 303 through the delay inverter 302, and the A, B end signal is subjected to and logic processing by the and gate 303, and then the pulse signal after pulse time compression is output at the output terminal 304. The timing diagram 305 details the waveforms of the three paths A, B, O, wherein the a-terminal is a wide pulse signal identical to the input terminal 301, the B-terminal is a delayed and inverted signal of the a-terminal signal, and the O-terminal is a signal obtained by and-logic of the A, B-terminal signal. By the pulse time compression circuit, the wide pulse of the input terminal 301 is finally compressed into the narrow pulse of the output terminal 304, and the pulse width of the final narrow pulse can be designed according to the requirement, and the design can be performed by only adjusting the delay time of the delay inverter 302.
FIG. 4 is a schematic circuit diagram of another pulse time compression circuit according to an embodiment of the present invention. The pulse time compression circuit comprises an input end 401, a front inverter 402, an NMOS-PMOS tube pair 403, an OR gate 404, a rear inverter 405 and an output end 406. The input end 401 is used for receiving the wide pulse signal output by the quenching circuit; the wide pulse signal is inverted by the front inverter 402 and then is input into the input end B of the OR gate circuit 404, the other path of the wide pulse signal acts on the gate electrode of the NMOS tube of the NMOS-PMOS tube pair 403, the source end of the NMOS tube is grounded, the drain end of the NMOS tube is connected with the drain end of the PMOS tube in series to serve as output, and the output is connected to the input end A of the OR gate circuit 404; the output end C of the OR gate circuit 404 is connected to the PMOS tube gate of the NMOS-PMOS tube pair 403, the source end of the PMOS tube is connected with the power supply, the drain end of the PMOS tube is connected with the drain end of the NMOS tube in series, and the output end C of the OR gate circuit 404 is simultaneously connected to the input end of the rear inverter 405; the output of the post inverter 405 is the output 406. The timing diagram 407 details the waveforms of each path, including the I-terminal, the B-terminal, the a-terminal, the C-terminal, and the O-terminal. The I end is the wide pulse signal input by the input end 401; the B end is the inverse of the I end wide pulse signal; the signal at the a end is relatively complex and is commonly modulated by the NMOS-PMOS transistor pair 403: when the end B is high, the NMOS tube is in an open state, the end A is pulled down to be low, and at the moment, the end C is high after the signal of the end A, B passes through OR logic; when the end B is low, the end A keeps low level, at the moment, the end C of the A, B signal is low after OR logic, the PMOS tube is opened, the end A is pulled up to the power supply to be high, and the end C after OR logic is also high; the C-terminal signal is generated by the change of the A-terminal signal and is a negative narrow pulse; the O end is the inverse of the C end signal and is the final narrow pulse signal. Through the pulse time compression circuit, the wide pulse of the input end 401 is finally compressed into the narrow pulse of the output end 406, and the pulse width of the final narrow pulse can be designed according to the requirement, and the gate length ratio of the PMOS transistor in the NMOS-PMOS transistor pair 403 is only required to be adjusted during the design.
FIG. 5 is a schematic diagram of a bus circuit according to an embodiment of the invention. The bus circuit mainly adopts an Open-Drain Output (OD) gate structure, and connects multiple signals to one bus through a wired AND logic. The bus circuit includes an input 501, an NMOS 502, a PMOS 503, and an output 504. The multiple input terminals 501 are used for receiving the narrow pulse signals output by the multi-path pulse time compression circuit; the NMOS tube 502 adopts a drain electrode open circuit connection method, namely, a source electrode is grounded, a grid electrode is used as an input end, and a drain end is used as an output end; the PMOS tube 503 is used as a pull-up resistor, the source end and the grid electrode are connected with a power supply, the drain end is connected with the drain ends of all NMOS tubes 502, and the AND logic is realized; the output 504 is a bus output. In the implementation process, the number of input ends of the bus circuit is matched according to the number of output ends of the front end, and the design of the width-to-length ratio of the PMOS tube and the NMOS tube is to be noted without specific limitation.
FIG. 6 is a schematic diagram of another bus circuit configuration in an embodiment of the invention. The bus circuit mainly adopts an OR logic structure to connect multiple paths of signals to one bus. The bus circuit includes an input 601, a primary or gate 602, a secondary or gate 603, and an output 604. The multiple input terminals 601 are used for receiving the narrow pulse signals output by the multi-path pulse time compression circuit; a plurality of stage OR gates 602 OR logically process the plurality of packetized input signals; the second-stage OR gate 603 OR-logically processes the output signals of the plurality of first-stage OR gates 602; the output 604 is the final output of all signals after the OR logic processing. In the specific implementation process, the number of input ends of the bus circuit is matched according to the number of output ends of the front end; whether the OR gate adopts the first stage and the second stage for classification, even adopts the third stage OR gate, and the number of the OR gates of each stage is not limited, and the OR gates are determined according to specific requirements.
Claims (4)
1. The pulse time compression method of the multichannel single photon avalanche diode detector comprises single photon avalanche diodes, a quenching circuit, a pulse time compression circuit and a bus circuit, and is characterized in that a detection array is formed by a plurality of single photon avalanche diodes, each single photon avalanche diode is mutually independent, and each single photon avalanche diode quenching circuit is respectively connected with one pulse time compression circuit; each path of single photon avalanche diode generates a path of wide pulse signal under the action of a corresponding quenching circuit, and the wide pulse signal is subjected to pulse time compression by a pulse time compression circuit to generate a path of narrow pulse signal; the bus circuit combines the multi-path narrow pulse signals compressed by pulse time to one bus as a pixel point to be output outwards;
the pulse time compression circuit comprises a delay inverter and an AND logic circuit, wherein the delay inverter delays and inverts an input signal, the AND logic circuit performs AND processing on the delayed and inverted signal and the input signal to obtain a narrow pulse signal after pulse time compression, and the pulse time of the narrow pulse signal is determined by the delay of the delay inverter.
2. The pulse time compression method of a multi-channel single photon avalanche diode detector according to claim 1, wherein said quenching circuit employs an active quenching circuit, a passive quenching circuit or a gated quenching circuit.
3. The pulse time compression method of a multi-channel single photon avalanche diode according to claim 2, wherein a single NMOS transistor is used as a passive quenching resistor in the passive quenching circuit.
4. The pulse time compression method of a multi-channel single photon avalanche diode according to claim 1, wherein said bus circuit employs multi-stage or gates to combine multiple narrow pulse signals onto a bus through or logic; or the bus circuit inputs each path of narrow pulse signal to the input end of one path of drain electrode open-circuit output gate circuit respectively, all the drain ends of each path of drain electrode open-circuit output gate circuit are connected to be used as bus output ends, and the bus output ends are pulled up to a power supply by a pull-up resistor.
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| CN113534107A (en) * | 2020-04-22 | 2021-10-22 | 上海禾赛科技有限公司 | Detection circuit with adjustable output pulse width, receiving unit and laser radar |
| CN112782714A (en) * | 2021-01-05 | 2021-05-11 | 广东博智林机器人有限公司 | Pulse signal processing circuit and laser radar |
| CN113687332A (en) * | 2021-07-08 | 2021-11-23 | 西安电子科技大学 | Analog front-end circuit based on capacitor array voltage synthesis technology in laser radar |
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| US7705284B2 (en) * | 2006-03-06 | 2010-04-27 | Nihon University | High-speed single-photon detector in telecommunication wavelength band |
| CN101964647B (en) * | 2010-09-14 | 2012-10-24 | 日银Imp微电子有限公司 | Pulse width signal duty ratio detection circuit |
| CN103036145A (en) * | 2011-09-30 | 2013-04-10 | 上海华魏光纤传感技术有限公司 | Multi-narrow-pulse laser light source and achieving method thereof |
| CN106603051A (en) * | 2016-12-08 | 2017-04-26 | 中国科学院上海高等研究院 | Quenching resetting circuit of single photon avalanche diode |
| CN108008402B (en) * | 2017-11-30 | 2021-05-28 | 南京大学 | Single photon avalanche diode detector array for laser ranging |
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