CN107741919B - Data communication device applied to control system - Google Patents

Data communication device applied to control system Download PDF

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Publication number
CN107741919B
CN107741919B CN201710878364.3A CN201710878364A CN107741919B CN 107741919 B CN107741919 B CN 107741919B CN 201710878364 A CN201710878364 A CN 201710878364A CN 107741919 B CN107741919 B CN 107741919B
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Prior art keywords
data
data read
write module
signal
clock
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CN107741919A (en
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李华平
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SHENZHEN UNIMAT AUTOMATION TECHNOLOGY Co Ltd
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SHENZHEN UNIMAT AUTOMATION TECHNOLOGY Co Ltd
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4247—Bus transfer protocol, e.g. handshake; Synchronisation on a daisy chain bus
    • G06F13/426—Bus transfer protocol, e.g. handshake; Synchronisation on a daisy chain bus using an embedded synchronisation, e.g. Firewire bus, Fibre Channel bus, SSA bus
    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
    • G05B19/00—Programme-control systems
    • G05B19/02—Programme-control systems electric
    • G05B19/04—Programme control other than numerical control, i.e. in sequence controllers or logic controllers
    • G05B19/05—Programmable logic controllers, e.g. simulating logic interconnections of signals according to ladder diagrams or function charts
    • G05B19/054—Input/output
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4247—Bus transfer protocol, e.g. handshake; Synchronisation on a daisy chain bus
    • G06F13/4256—Bus transfer protocol, e.g. handshake; Synchronisation on a daisy chain bus using a clocked protocol

Abstract

The invention relates to the technical field of communication, and discloses a data communication device applied to a control system, which comprises a plurality of stages of data read-write modules connected in series; outputting a control signal for controlling the data transmission direction to a next-stage data read-write module through the data read-write module; when the control signal is at a first level, the data read-write module synchronously sends a clock output signal and a data output signal to the next-stage data read-write module; when the control signal is at the second level, the data read-write module sends a clock output signal to the next-stage data read-write module, the next-stage data read-write module synchronously returns a clock input signal and a data input signal to the data read-write module according to the clock output signal, and the frequency of the clock input signal is the same as that of the clock output signal. Therefore, the phase difference between the clock signal and the data signal in the data transmission process between the modules is eliminated, the distance and the speed of data transmission are improved, and the effect of high-speed synchronous data transmission is achieved.

Description

Data communication device applied to control system
Technical Field
The present invention relates to the field of communications technologies, and in particular, to a data communication apparatus applied to a control system.
Background
A PLC (Programmable Logic Controller) control system generally adopts a modular system structure, i.e., a daisy chain structure of "PLC + modules", where a PLC host supports connection of an expansion module through a backplane bus, and the backplane bus is a high-speed data path between the PLC host and the expansion module and supports data communication between the host and the expansion module.
The traditional backboard bus interface adopts a synchronous communication interface, but when the speed is increased to a certain value, the dislocation phenomenon can be generated by adopting the interface, and the problem is mainly caused by two aspects, namely, the wiring length between the PLC and the module and between the modules is longer, and the transmission delay exists in a wire material; secondly, the transmission delay of the electronic components exists. Therefore, the phase difference between the data and the clock is large during communication, and indexes such as communication distance and communication speed are difficult to improve.
Disclosure of Invention
The embodiment of the invention provides a data communication device applied to a control system, and aims to solve the problems that in the prior art, the phase difference between data and a clock is large during communication, and indexes such as communication distance, communication speed and the like are difficult to improve.
The embodiment of the invention provides a data communication device applied to a control system, which comprises a plurality of stages of data reading and writing modules connected in series.
The data read-write module is connected with the next-stage data read-write module, and the control signal output end, the clock output end, the data output end, the clock input end and the data input end of the data read-write module are respectively connected with the control signal input end, the clock input end, the data input end, the clock output end and the data output end of the next-stage data read-write module in a one-to-one correspondence manner;
The data read-write module outputs a control signal for controlling the data transmission direction to the next-stage data read-write module; when the control signal is at a first level, the data read-write module synchronously sends a clock output signal and a data output signal to the next-stage data read-write module; when the control signal is at the second level, the data read-write module sends a clock output signal to the next-stage data read-write module, the next-stage data read-write module synchronously returns a clock input signal and a data input signal to the data read-write module according to the clock output signal, and the frequency of the clock input signal is the same as that of the clock output signal.
In one embodiment, the reset signal output end of the data read-write module is connected with the reset signal input end of the next-stage data read-write module; the data read-write module outputs a reset signal to the next-stage data read-write module, and the next-stage data read-write module executes reset operation and outputs the reset signal.
In one embodiment, the reset signal is a pulse signal.
In one embodiment, the data read-write modules connected in series in multiple stages include a first-stage data read-write module and a preset number of later-stage data read-write modules connected in sequence.
In one embodiment, the first stage data read/write module includes a programmable logic controller.
In one embodiment, the post-stage data read/write module comprises a field programmable gate array.
In one embodiment, the second level is a low level when the first level is a high level, or the second level is a high level when the first level is a low level.
In one embodiment, the data read-write modules connected in series in multiple stages are connected through a bus.
In one embodiment, the clock output signal, the data output signal, the clock input signal, and the data input signal are serial data.
Compared with the prior art, the embodiment of the invention has the following beneficial effects: outputting a control signal for controlling the data transmission direction to a next-stage data read-write module through the data read-write module; when the control signal is at a first level, the data read-write module synchronously sends a clock output signal and a data output signal to the next-stage data read-write module; when the control signal is at the second level, the data read-write module sends a clock output signal to the next-stage data read-write module, the next-stage data read-write module synchronously returns a clock input signal and a data input signal to the data read-write module according to the clock output signal, and the frequency of the clock input signal is the same as that of the clock output signal. The embodiment of the invention realizes the synchronous output of the clock signal and the data signal, and the two signals are synchronously delayed even if delayed, thereby eliminating the phase difference in the data transmission process between the modules, improving the distance and the speed of data transmission and achieving the effect of synchronously transmitting data at high speed.
Drawings
in order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings needed to be used in the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art that other drawings can be obtained according to these drawings without inventive labor.
Fig. 1 is a schematic structural diagram of a data communication device applied in a control system according to an embodiment of the present invention;
FIG. 2 is a bus timing diagram of a reset signal output of a data communication device applied in a control system according to an embodiment of the present invention;
FIG. 3 is a bus timing diagram illustrating a first level of control signals applied to a data communication device in a control system according to an embodiment of the present invention;
fig. 4 is a bus timing diagram of a data communication device applied in a control system according to a second embodiment of the present invention.
Detailed Description
In order to make the technical solution better understood by those skilled in the art, the technical solution in the embodiment of the present invention will be clearly described below with reference to the drawings in the embodiment of the present invention, and it is obvious that the described embodiment is a part of the embodiment of the present invention, but not all embodiments. All other embodiments obtained by a person of ordinary skill in the art based on the embodiments in the present disclosure without any creative effort shall fall within the protection scope of the present disclosure.
The terms "comprises" and "comprising," as well as any variations thereof, in the description and claims of this document and the above-described drawings, are intended to cover non-exclusive inclusions. Furthermore, the terms "first" and "second," etc. are used to distinguish between different objects and are not used to describe a particular order.
the following detailed description of implementations of the invention refers to the accompanying drawings in which:
Fig. 1 is a schematic structural diagram of a data communication device applied in a control system according to an embodiment of the present invention, and for convenience of description, only the parts related to the embodiment of the present invention are shown, which is detailed as follows:
as shown in fig. 1, a data communication apparatus applied in a control system according to an embodiment of the present invention includes a data read/write module connected in series in multiple stages;
The DATA read-write module is connected with the next-stage DATA read-write module, and a control signal output end CTL1_ OUT, a clock output end CLK _ OUT, a DATA output end DATA _ OUT, a clock input end CLK _ IN and a DATA input end DATA _ IN of the DATA read-write module are respectively connected with a control signal input end CTL1_ IN, a clock input end CLK _ IN, a DATA input end DATA _ IN, a clock output end CLK _ OUT and a DATA output end DATA _ OUT of the next-stage DATA read-write module IN a one-to-one correspondence manner;
the data read-write module outputs a control signal C1 for controlling the data transmission direction to the next-stage data read-write module; when the control signal C1 is at the first level, the data read-write module synchronously sends a clock output signal C _ O and a data output signal D _ O to the next-stage data read-write module; when the control signal C1 is at the second level, the data read-write module sends a clock output signal C _ O to the next-stage data read-write module, and the next-stage data read-write module synchronously returns a clock input signal C _ I and a data input signal D _ I to the data read-write module according to the clock output signal C _ O, where the clock input signal C _ I and the clock output signal C _ O have the same frequency.
It should be noted that the apparatus includes a plurality of data read/write modules, and in this embodiment, any one of the data read/write modules is taken as an example for description, and the data read/write module connected to the rear end of the data read/write module is the next-stage data read/write module.
IN one embodiment, the control signal output terminal CTL1_ OUT of the DATA read/write module outputs the control signal C1, the clock output terminal CLK _ OUT outputs the clock output signal C _ O, the DATA output terminal DATA _ OUT outputs the DATA output signal D _ O, the clock input terminal CLK _ IN receives the clock input signal C _ I, and the DATA input terminal DATA _ IN receives the DATA input signal D _ I.
IN one embodiment, the control signal input terminal CTL1_ IN of the next stage DATA read/write module receives the control signal C1, the clock input terminal CLK _ IN receives the clock output signal C _ O, the DATA input terminal DATA _ IN receives the DATA output signal D _ O, the clock output terminal CLK _ OUT outputs the clock input signal C _ I, and the DATA output terminal DATA _ OUT outputs the DATA input signal D _ I.
In one embodiment, when the control signal C1 is at the first level, the DATA reading and writing module starts writing DATA, the clock output terminal CLK _ OUT of the DATA reading and writing module outputs the clock output signal C _ O, and the DATA output terminal DATA _ OUT outputs the DATA output signal D _ O. When the control signal is at the second level, the data read-write module starts to read data, and the clock output end CLK _ OUT of the data read-write module outputs a clock output signal C _ O. After the clock input end CLK _ IN of the next-stage DATA read-write module receives the clock output signal C _ O, the clock output end CLK _ OUT returns the clock input signal C _ I to the DATA read-write module, and the DATA output end DATA _ OUT synchronously returns the DATA input signal D _ I to the DATA read-write module.
In one embodiment of the present invention, the second level is a low level when the first level is a high level, or the second level is a high level when the first level is a low level.
In one embodiment of the present invention, the clock output signal C _ O, the data output signal D _ O, the clock input signal C _ I, and the data input signal D _ I are serial data.
As shown IN fig. 1, IN an embodiment of the present invention, the reset signal output terminal CTL2_ OUT of the data read/write module is connected to the reset signal input terminal CTL2_ IN of the data read/write module of the next stage; the data read-write module outputs a reset signal C2 to the next-stage data read-write module, and the next-stage data read-write module executes the reset operation and outputs a reset signal C2. The reset signal is a pulse signal.
As shown in fig. 1, in an embodiment of the present invention, the data reading and writing modules connected in series in multiple stages include a first-stage data reading and writing module and a preset number of later-stage data reading and writing modules connected in sequence.
In one embodiment, the first-level data read/write module 100 includes a processor 110 and an upper-level interface 120, the upper-level interface 120 includes a plurality of ports, and the post-level data read/write module 200 includes a programmable gate array 210, a lower-level interface 220, and an upper-level interface 230. The lower level interface 220 and the upper level interface 230 each include a plurality of ports.
in one embodiment of the invention, the first-level data read-write module comprises a programmable logic controller.
in one embodiment, the first-stage data read/write module 100 includes a programmable logic controller PLC, which employs a type of programmable memory for storing programs therein, executing user-oriented instructions such as logic operations, sequence control, timing, counting, and arithmetic operations, and controlling various types of machinery or manufacturing processes through digital or analog input/output. The basic structure of the PLC includes a power supply, a processor 110, a memory, and an input/output module, wherein the processor 110 is configured to receive and store user programs and data according to functions assigned by the PLC system program. The processor of the PLC controls the upper level interface 120 to read and write data in this embodiment.
In one embodiment of the present invention, the back-stage data read/write module 200 comprises a field programmable gate array.
In an embodiment, the post-stage data read/write module 200 includes a Programmable logic device for receiving data sent by the first-stage data read/write module 100 and performing corresponding operations according to a pre-stored program, preferably, the Programmable logic device of the embodiment of the present invention selects an FPGA (Field-Programmable Gate Array) 210, where the FPGA has parallel processing capability, and when receiving a clock output signal C _ O sent by the first-stage data read/write module 100, returning a clock input signal C _ I and a data input signal D _ I at the same time, wherein the frequency of the clock output signal C _ O is the same as that of the data input signal D _ I, IN this way, the first stage DATA read/write module 100 can receive the clock input signal C _ I through the clock input terminal CLK _ IN at the same time as receiving the DATA input signal D _ I through the DATA input terminal DATA _ IN. Therefore, the phase difference between the clock output signal C _ O and the data input signal D _ I is eliminated, and the communication speed and the communication distance are greatly improved. It can be understood that the Programmable Logic Device in the back-stage data read/write module 200 in the embodiment of the present invention may also be a CPLD (Complex Programmable Logic Device).
In one embodiment of the invention, the data read-write modules connected in series in multiple stages are connected through a bus.
In the embodiment of the present invention, when data is read, the first-stage data read/write module 100 sends out the clock output signal C _ O, the second-stage data read/write module 200 synchronously returns the clock input signal C _ I and the data input signal D _ I, and the frequency of the clock output signal C _ O is the same as that of the clock input signal C _ I, so that the clock input signal C _ I and the data input signal D _ I can synchronously reach the first-stage data read/write module 100, thereby eliminating the phase difference between the clock output signal C _ O and the data input signal D _ I caused by the data read/write module sending out the clock output signal C _ O and then returning the data input signal D _ I in the data reading process in the prior art, and ensuring the synchronous transmission of the clock and the data in the communication process.
fig. 2 shows a bus timing diagram of a reset signal output according to an embodiment of the present invention, and for convenience of description, only the portions related to the embodiment of the present invention are shown, and the details are as follows:
As shown in fig. 2, when the reset signal output terminal CTL2_ OUT of the first stage data r/w block 100 outputs a low-level pulse reset signal C2, the clock input signal C _ I, the clock output signal C _ O, the data input signal D _ I, the data output signal D _ O and the control signal C1 of the first stage data r/w block 100 all recover the original state. After the reset signal input end CTL2_ IN of the rear stage data read/write module 200 receives the reset signal C2, the clock input signal C _ I, the clock output signal C _ O, the data input signal D _ I, the data output signal D _ O, and the control signal C1 of the rear stage data read/write module 200 also recover to the original state. The later stage data read/write module 200 receives the reset signal C2 to execute the reset operation and outputs the reset signal C2 to the next stage data read/write module.
Fig. 3 shows a bus timing diagram when the control signal provided by the embodiment of the present invention is at the first level, and for convenience of description, only the portions related to the embodiment of the present invention are shown, which is detailed as follows:
in this embodiment, the first level is a low level, and the second level is a high level.
As shown in FIG. 3, when the control signal C1 is at the first level, the control signal C1 controls the first DATA R/W module 100 to write DATA, and the DATA output terminal DATA _ OUT synchronously outputs the DATA output signal D _ O when the clock output terminal CLK _ OUT outputs the clock output signal C _ O. As can be seen from fig. 3, the data output signal D _ O is output in the form of bytes, and each bit of the data output signal D _ O corresponds to one clock cycle of the clock output signal C _ O.
Fig. 4 shows a bus timing diagram when the control signal provided by the embodiment of the present invention is at the second level, and for convenience of description, only the portions related to the embodiment of the present invention are shown, which is detailed as follows:
as shown in fig. 4, in an embodiment of the present invention, when the control signal C1 is at the second level, the control signal C1 controls the data reading and writing module to read data, and when the clock output terminal CLK _ OUT of the first stage data reading and writing module 100 outputs the clock output signal C _ O to the next stage data reading and writing module 200, the next stage data reading and writing module 200 synchronously returns the clock input signal C _ I and the data input signal D _ I.
As can be seen from fig. 4, the clock output signal C _ O has the same frequency as the returned clock input signal C _ I, i.e. the clock output signal is sent out and is "reflected" back by the next-stage data read-write module.
In this embodiment, the clock input signal C _ I and the data input signal D _ I can be simultaneously returned to the first-stage data read/write module 100, so as to solve the problem of data misalignment caused by the data input signal D _ I lagging behind the clock input signal C _ I in the prior art, and improve the communication rate to a greater extent.
Similarly, when reading data, the data input signal D _ I is output in the form of bytes, and each bit of the data input signal D _ I corresponds to one clock cycle of the clock input signal C _ I.
In the present embodiment, when reading data, the returned clock input signal C _ I is controlled by the transmitted clock output signal C _ O, that is, the returned clock rate and the number of data bits are still controlled by the first-stage data read/write module 100.
In the timing chart provided in fig. 3 and fig. 4 of this embodiment, the second level is high when the first level of the control signal C1 is low, and similarly, the control signal C1 may select the second level to be low when the first level is high, that is, the data read/write module is controlled to read data when the control signal C1 is the first level, and the data read/write module is controlled to write data when the control signal C1 is the second level.
in the embodiment of the invention, the control signal for controlling the data transmission direction is output to the next-stage data read-write module through the data read-write module; when the control signal is at a first level, the data read-write module synchronously sends a clock output signal and a data output signal to the next-stage data read-write module; when the control signal is at the second level, the data read-write module sends a clock output signal to the next-stage data read-write module, the next-stage data read-write module synchronously returns a clock input signal and a data input signal to the data read-write module according to the clock output signal, and the frequency of the clock input signal is the same as that of the clock output signal. According to the data communication device provided by the embodiment of the invention, the phase difference between the clock output signal and the data input signal caused by the fact that the data read-write module sends the clock output signal and then returns the data input signal in the data reading process in the prior art is eliminated, the synchronous transmission of the clock and the data in the communication process is ensured, the distance and the speed of data transmission are improved, and the effect of synchronously transmitting the data at a high speed is achieved.
The above-mentioned embodiments are only used for illustrating the technical solutions of the present invention, and not for limiting the same; although the present invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; and such modifications or substitutions do not depart from the spirit and scope of the corresponding technical solutions of the embodiments of the present invention.

Claims (9)

1. A data communication device applied in a control system is characterized by comprising a plurality of stages of data reading and writing modules which are connected in series;
the data read-write module is connected with the next-stage data read-write module, and a control signal output end, a clock output end, a data output end, a clock input end and a data input end of the data read-write module are respectively connected with a control signal input end, a clock input end, a data input end, a clock output end and a data output end of the next-stage data read-write module in a one-to-one correspondence manner;
The data read-write module outputs a control signal for controlling the data transmission direction to the next-stage data read-write module; when the control signal is at a first level, the data read-write module synchronously sends a clock output signal and a data output signal to the next-stage data read-write module; when the control signal is at a second level, the data read-write module sends a clock output signal to the next-stage data read-write module, the next-stage data read-write module synchronously returns a clock input signal and a data input signal to the data read-write module according to the clock output signal, and the frequency of the clock input signal is the same as that of the clock output signal;
One bit of the data input signal corresponds to one clock cycle of the clock input signal, and the clock output signal controls a clock rate of the clock input signal and a data bit number of the data input signal.
2. The data communication apparatus applied in the control system according to claim 1, wherein the reset signal output terminal of the data read/write module is connected to the reset signal input terminal of the next-stage data read/write module;
The data read-write module outputs a reset signal to the next-stage data read-write module, and the next-stage data read-write module executes reset operation and outputs the reset signal.
3. The data communication device for use in a control system of claim 2, wherein said reset signal is a pulse signal.
4. The data communication device as claimed in claim 1, wherein the plurality of stages of serially connected data read/write modules include a first stage of data read/write modules and a preset number of subsequent stage data read/write modules connected in sequence.
5. the data communication device as claimed in claim 4, wherein the first stage data read/write module comprises a programmable logic controller.
6. The data communication device applied to the control system according to claim 4, wherein the post-stage data read/write module comprises a field programmable gate array.
7. the data communication apparatus for use in a control system according to claim 1, wherein the second level is a low level when the first level is a high level, or the second level is a high level when the first level is a low level.
8. The data communication device applied to the control system according to claim 1, wherein the data read-write modules connected in series in the plurality of stages are connected through a bus.
9. The data communication device as claimed in claim 1, wherein the clock output signal, the data output signal, the clock input signal and the data input signal are serial data.
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CN101022039A (en) * 2007-03-14 2007-08-22 北京中星微电子有限公司 Apparatus and method for identifying synchronous memory controller based on field programmable gate array
CN202904557U (en) * 2012-11-08 2013-04-24 广西工学院 Output data refreshing, read-write and time sequence controller of programmable logical controller (PLC)
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