CN103312339B - A kind of parallel-to-serial converter supporting preequalization - Google Patents
A kind of parallel-to-serial converter supporting preequalization Download PDFInfo
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- CN103312339B CN103312339B CN201310176253.XA CN201310176253A CN103312339B CN 103312339 B CN103312339 B CN 103312339B CN 201310176253 A CN201310176253 A CN 201310176253A CN 103312339 B CN103312339 B CN 103312339B
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Abstract
The present invention discloses a kind of parallel-to-serial converter supporting preequalization, comprise the first clock generator, second clock generator, first d type flip flop, second d type flip flop and the first gate, the output of the first clock generator and the clock signal input terminal of the first d type flip flop are electrically connected, the output of second clock generator is electrically connected with the clock signal input terminal of the second d type flip flop and the first gate respectively, the output of the first d type flip flop and the output of the second d type flip flop are electrically connected with two data signal input of the first gate respectively, the data signal input of the first d type flip flop is connected with the first parallel data output, the data signal input of the second d type flip flop is connected with the second parallel data output.The present invention adopts two clocks, the phase of the first clock and second clock 180 °, realizes parallel-serial conversion, and support preequalization under the prerequisite that the clock frequency of d type flip flop is different from the frequency exporting data.
Description
Technical field
The present invention relates to CMOS integrated circuit (IC) design field, particularly relate to a kind of parallel-to-serial converter supporting preequalization.
Background technology
In high speed serial communication field, before bus driving circuits, need a parallel-to-serial converter that parallel digital signal is changed into serial signal.Because preequalization supported by needs, general needs postpones a beat serial data, usually adopts one-level d type flip flop to reach delay object.This related method thereof requires that the clock frequency of this d type flip flop is consistent with the frequency exporting data.If the frequency exporting data is 5GHz, then the clock frequency of trigger also needs to be 5GHz, as depicted in figs. 1 and 2.Cause the execution of this d type flip flop at full stretch for opportunity like this, be difficult to realize this related method thereof.
Summary of the invention
The technical problem that the present invention mainly solves is to provide a kind of parallel-to-serial converter supporting preequalization, adopt two clocks, the phase of the first clock and second clock 180 °, under the prerequisite that the clock frequency of d type flip flop is different from the frequency exporting data, realize parallel-serial conversion, and support preequalization.
For solving the problems of the technologies described above, the technical solution used in the present invention is: provide a kind of parallel-to-serial converter supporting preequalization, comprise the first clock generator, second clock generator, first d type flip flop, second d type flip flop and the first gate, the output of described first clock generator and the clock signal input terminal of the first d type flip flop are electrically connected, the output of second clock generator is electrically connected with the clock signal input terminal of the second d type flip flop and the clock signal input terminal of the first gate respectively, the output of described first d type flip flop and the output of the second d type flip flop are electrically connected with two data signal input of the first gate respectively, the data signal input of described first d type flip flop is connected with the first parallel data output, the data signal input of described second d type flip flop is connected with the second parallel data output.
In a preferred embodiment of the present invention, described parallel-to-serial converter comprises 3d flip-flop, four d flip-flop, the 5th d type flip flop and the second gate further, the output of described four d flip-flop and the data signal input of the 5th d type flip flop are electrically connected, and the output of the 5th d type flip flop and 3d flip-flop output are electrically connected with two data signal input of the second gate respectively.
In a preferred embodiment of the present invention, the output of described first clock generator is electrically connected with the clock signal input terminal of four d flip-flop, the 5th d type flip flop and the second gate respectively.
In a preferred embodiment of the present invention, the described output of second clock generator and the clock signal input terminal of 3d flip-flop are electrically connected.
In a preferred embodiment of the present invention, described first parallel data output is electrically connected with the data signal input of 3d flip-flop further, and the second parallel data output is electrically connected with the data signal input of four d flip-flop further.
In a preferred embodiment of the present invention, described first clock generator is identical with the clock signal frequency that second clock generator exports, and described first gate is identical with the frequency data signal that the second gate exports.
In a preferred embodiment of the present invention, the frequency data signal that described first gate exports is the twice of the clock signal frequency that the first clock generator exports.
In a preferred embodiment of the present invention, the clock signal frequency that described first clock generator exports is 2.5GHz, and the frequency data signal that the first gate exports is 5GHz.
In a preferred embodiment of the present invention, the clock signal phase that described first clock generator and second clock generator export differs 180 °.
In a preferred embodiment of the present invention, described first gate and the second gate are alternative gate.
The invention has the beneficial effects as follows: the phase of described first clock and second clock 180 °, under the prerequisite that the clock frequency of d type flip flop is different from the frequency exporting data, realize parallel-serial conversion, and support preequalization.
Accompanying drawing explanation
Fig. 1 is the circuit diagram of existing 2 to 1 parallel-to-serial converter;
Fig. 2 is the sequential chart of existing 2 to 1 parallel-to-serial converter;
Fig. 3 is the circuit diagram that the present invention supports the parallel-to-serial converter of preequalization;
Fig. 4 is the sequential chart that the present invention supports the parallel-to-serial converter of preequalization.
In accompanying drawing, the mark of each parts is as follows: J0, the first d type flip flop; J1, the second d type flip flop; J2,3d flip-flop; J3, four d flip-flop; J4, the 5th d type flip flop; D0, the first output signal; D1, the second output signal; D2, the 3rd output signal; D3, the 4th output signal; D4, the 5th output signal; U1, the first gate; U2, the second gate; Din0, the first parallel data; Din1, the second parallel data; Clkp, the first clock; Clkn, second clock; Dout, serial signal; Dout_dly1, serial delay signal.
Embodiment
Below in conjunction with accompanying drawing, preferred embodiment of the present invention is described in detail, can be easier to make advantages and features of the invention be readily appreciated by one skilled in the art, thus more explicit defining is made to protection scope of the present invention.
Refer to Fig. 3 and Fig. 4, the embodiment of the present invention comprises:
A kind of parallel-to-serial converter supporting preequalization, comprise the first clock generator, second clock generator, the first d type flip flop J0, the second d type flip flop J1,3d flip-flop J2, four d flip-flop J3, the 5th d type flip flop J4, the first gate U1 and the second gate U2, described first gate U1 and the second gate U2 is alternative gate.
First parallel data output exports the first parallel data Din0, and the first parallel data Din0 inputs to the data signal input of the first d type flip flop J0 and 3d flip-flop J2 respectively.Second parallel data output exports the second parallel data Din1, and the second parallel data Din1 inputs to the data signal input of the second d type flip flop J1 and four d flip-flop J3 respectively.
The output of described first d type flip flop J0 and first data signal input of the first gate U1 are electrically connected, the output of the second d type flip flop J1 and second data signal input of the first gate U1 are electrically connected, and the first gate U1 exports serial signal dout.
The output of described four d flip-flop J3 and the data signal input of the 5th d type flip flop J4 are electrically connected, the output of the 5th d type flip flop J4 and first data signal input of the second gate U2 are electrically connected, the output of 3d flip-flop J2 and second data signal input of the second gate U2 are electrically connected, and the second gate U2 exports serial delay signal dout_dly1.
Described first clock generator exports the first clock clkp, and the first clock clkp inputs to the clock signal input terminal of the first d type flip flop J0, four d flip-flop J3, the 5th d type flip flop J4 and the second gate U2 respectively.Second clock generator exports second clock clkn, and second clock clkn inputs to the clock signal input terminal of the second d type flip flop J1,3d flip-flop J2 and the first gate U1 respectively.
Wherein, described first clock generator is identical with the clock signal frequency that second clock generator exports, and described first gate U1 is identical with the frequency data signal that the second gate U2 exports.The frequency data signal that described first gate U1 exports is the twice of the clock signal frequency that the first clock generator exports.In the present embodiment, the clock signal frequency that described first clock generator exports is 2.5GHz, and the frequency data signal that the first gate U1 exports is 5GHz.The clock signal that described first clock generator exports and the clock signal phase that second clock generator exports differ 180 °.
Assuming that the first parallel data Din0 series is 1,3,5,7 ..., the second parallel data Din1 series is 2,4,6,8 ..., the first clock clkp exceeds half clock cycle than second clock clkn.The first parallel data Din0 of 2.5GHz inputs to the first d type flip flop J0, and the first d type flip flop J0 exports the first output signal D0 of 2.5GHz.The second parallel data Din1 of 2.5GHz inputs to the second d type flip flop J1, and the second d type flip flop J1 exports the second output signal D1 of 2.5GHz.First output signal D0 and second output signal D1 inputs to the first gate U1, and second clock clkn signal controlling first gate U1 selects output first to output signal D0 or second output signal D1, exports the first output signal D0 when second clock clkn signal is low level, export the second output signal D1 when second clock clkn signal is high level, finally, the first gate U1 exports the serial signal dout1 of 5GHz, 2,3,4,5,6,7,8 ...
In like manner, the first parallel data Din0 inputs to 3d flip-flop J2, and the second parallel data Din1 inputs to four d flip-flop J3,3d flip-flop J2 exports the 4th output signal D3 of the 3rd output signal D2, the four d flip-flop J3 output 2.5GHz of 2.5GHz, and the 5th d type flip flop J4 exports the 5th output signal D4 of 2.5GHz, second gate U2 exports the serial delay signal dout_dly11 of 5GHz, and 2,3,4,5,6,7,8 ...Due to the difference that clock selecting is connected with circuit, 5th output signal D4 is delayed half first clock cycle relative to the second output signal D1,3rd output signal D2 is delayed half first clock cycle relative to the first output signal D0, therefore, the serial delay signal dout_dly1 that second gate U2 exports also relative serial signal dout postpones half first clock cycle, thus realizes preequalization function.
The present invention adopts two clocks, the phase of the first clock clkp and second clock clkn 180 °, realizes parallel-serial conversion, and support preequalization under the prerequisite that the clock frequency of d type flip flop is different from the frequency exporting data.
The foregoing is only embodiments of the invention; not thereby the scope of the claims of the present invention is limited; every utilize specification of the present invention and accompanying drawing content to do equivalent structure or equivalent flow process conversion; or be directly or indirectly used in other relevant technical fields, be all in like manner included in scope of patent protection of the present invention.
Claims (6)
1. support a parallel-to-serial converter for preequalization, it is characterized in that, comprise the first clock generator, second clock occurs
Device, first d type flip flop, second d type flip flop and the first gate, the output of described first clock generator and the clock signal input terminal of the first d type flip flop are electrically connected, the output of second clock generator is electrically connected with the clock signal input terminal of the second d type flip flop and the clock signal input terminal of the first gate respectively, the output of described first d type flip flop and the output of the second d type flip flop are electrically connected with two data signal input of the first gate respectively, the data signal input of described first d type flip flop is connected with the first parallel data output, the data signal input of described second d type flip flop is connected with the second parallel data output, described parallel-to-serial converter comprises 3d flip-flop further, four d flip-flop, 5th d type flip flop and the second gate, the output of described 4th D tentaculum and the data signal input of the 5th d type flip flop are electrically connected, the output of the 5th d type flip flop and 3d flip-flop output are electrically connected with two data signal input of the second gate respectively, the output of described first clock generator respectively with four d flip-flop, the clock signal input terminal of the 5th d type flip flop and the second gate is electrically connected, the described output of second clock generator and the clock signal input terminal of 3d flip-flop are electrically connected, described first parallel data output is electrically connected with the data signal input of 3d flip-flop further, second parallel data output is electrically connected with the data signal input of four d flip-flop further.
2. the parallel-to-serial converter supporting preequalization as claimed in claim 1, it is characterized in that, described first clock generator is identical with the clock signal frequency that second clock generator exports, and described first gate is identical with the frequency data signal that the second gate exports.
3. the parallel-to-serial converter supporting preequalization as claimed in claim 1, is characterized in that, the frequency data signal that described first gate exports is the twice of the clock signal frequency that the first clock generator exports.
4. the parallel-to-serial converter supporting preequalization as claimed in claim 3, is characterized in that, the clock signal frequency that described first clock generator exports is 2.5GHz, and the frequency data signal that the first gate exports is 5GHz.
5. the parallel-to-serial converter supporting preequalization as claimed in claim 1, is characterized in that, the clock signal phase that described first clock generator and second clock generator export differs 180 °.
6. the parallel-to-serial converter supporting preequalization as claimed in claim 1, it is characterized in that, described first gate and the second gate are alternative gate.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201310176253.XA CN103312339B (en) | 2013-05-14 | 2013-05-14 | A kind of parallel-to-serial converter supporting preequalization |
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| CN201310176253.XA CN103312339B (en) | 2013-05-14 | 2013-05-14 | A kind of parallel-to-serial converter supporting preequalization |
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| CN103312339B true CN103312339B (en) | 2016-03-30 |
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| KR102006022B1 (en) * | 2013-11-06 | 2019-08-01 | 에스케이하이닉스 주식회사 | Serializer |
| CN116743184A (en) * | 2023-08-16 | 2023-09-12 | 合肥奎芯集成电路设计有限公司 | Four-to-two parallel-serial conversion circuit |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1551507A (en) * | 2003-05-09 | 2004-12-01 | �ձ�������ʽ���� | Serial-to-parallel- and parallel-to-serial converter |
| CN102332924A (en) * | 2010-07-06 | 2012-01-25 | 川崎微电子股份有限公司 | Parallel to serial conversion apparatus and method of converting parallel data having different widths |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| JP3501732B2 (en) * | 2000-06-23 | 2004-03-02 | 日本電気通信システム株式会社 | Parallel-serial conversion circuit |
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Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1551507A (en) * | 2003-05-09 | 2004-12-01 | �ձ�������ʽ���� | Serial-to-parallel- and parallel-to-serial converter |
| CN102332924A (en) * | 2010-07-06 | 2012-01-25 | 川崎微电子股份有限公司 | Parallel to serial conversion apparatus and method of converting parallel data having different widths |
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