CN100552660C - A kind of data handling system and data processing method - Google Patents

A kind of data handling system and data processing method Download PDF

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CN100552660C
CN100552660C CNB200810105630XA CN200810105630A CN100552660C CN 100552660 C CN100552660 C CN 100552660C CN B200810105630X A CNB200810105630X A CN B200810105630XA CN 200810105630 A CN200810105630 A CN 200810105630A CN 100552660 C CN100552660 C CN 100552660C
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data
address
control
bus pin
pin
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CN101271441A (en
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杨宁
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Guangdong Beidou South Technology Co ltd
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Beijing Star Net Ruijie Networks Co Ltd
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Abstract

The invention discloses a kind of data handling system and data processing method, comprise: the address of CPU processor links to each other with the data bus pins of data storage device with the data multiplex bus pin, the CPU processor is when carrying out data manipulation, by control bus pin, address and data multiplex bus pin transmitting control commands and address information; Converter converts the control signal and the address signal of data storage device form to, and is sent to data storage device after receiving control command and address information; Data storage device is according to control signal and address signal, the data manipulation that response CPU processor is undertaken by address and data multiplex bus pin and data storage device data bus pins.Use the present invention, the CPU processor is not influenced by converter to the data manipulation speed of peripheral components, and when carrying out data manipulation, data need not the processing through converter, have saved the internal resource of converter.

Description

A kind of data handling system and data processing method
Technical field
The present invention relates to data processing equipment, particularly a kind of data handling system, and the data processing method of this system.
Background technology
The processor of inner integrated LOCAL BUS (local bus) controller can describe this process below to carrying out read-write operation as peripheral components such as FLASH.
RM9224 belongs to the RM9K of PMC company series Communication processor, and inner integrated LOCAL BUS (local bus) controller is used to read start-up code and peripheral components is operated.The LOCALBUS controller is supported address information, 8/16/32 bit data width, 4 sheet selected control system signals of 24.Because the peripheral components that uses all is 8 bit data width, below be the example explanation with 8 bit data.
Fig. 1 is the LOCALBUS mount structure synoptic diagram of RM9224, and as shown in the figure, the LOCAL BUS of RM9224 is made up of LBCLK (bus clock), LBAD (address and data multiplex bus, 8 bit data width), LBCMD (control bus, 4 bit width data).LBCLK guarantees that the sequential on the bus is synchronous; LBAD is used for transport address and data; LBCMD is used for transmitting control command.LBCLK and LBCMD are the unidirectional peripherals of exporting to of RM9224; LBAD is the unidirectional peripherals of exporting to of RM9224 when the transport address, and 24 bit address are divided 3 output; During the transmission data are bidirectional lines, if write operation, RM9224 exports to peripherals, if read operation, peripherals is exported to RM9224, owing to be 8 bit manipulations, the output transmission primaries is finished.
The different code that LBCMD uses has been represented different implications, as:
0x0 represents the read operation of CS0 (sheet selects 0), 8 the highest bit address A (23..16) of LBAD output simultaneously;
0X4 represents the write operation of CS0 (sheet selects 0), 8 the highest bit address A (23..16) of LBAD output simultaneously;
0x8 represents data transmission;
0xC represents LBAD output least-significant byte address A (7..0);
0xD represents the address A (15..8) of middle 8 of LBAD output;
0xE represents end of transmission (EOT);
0xF represents the bus free time.
Introduce the write operation of RM9224 below and implement, Fig. 2 is the write operation sequential synoptic diagram of RM9224, and as shown in the figure, each clock period was as follows when RM9224 implemented the write operation of peripherals:
Clock period 1, RM9224 export 0X4 on LBCMD, expression is selected 0 write operation to sheet, and the output high address, simultaneously output most-significant byte address A (23..16) on LBAD.
Clock period 2, RM9224 export 0XD on LBCMD, expression output intermediate address, output intermediate address A (15..8) on LBAD simultaneously.
Clock period 3, RM9224 export 0XC on LBCMD, expression output lowest address, output lowest address A (7..0) on LBAD simultaneously.
Clock period 4-6, RM9224 export 0XF on LBCMD, the expression idling cycle, and LBAD goes up output data D (7..0) simultaneously.
Clock period 7, RM9224 export 0X8 on LBCMD, the expression data transmission continues output data D (7..0) simultaneously on LBAD.
Clock period 8, RM9224 export 0XE on LBCMD, expression end of transmission (EOT), no longer output on LBAD simultaneously.
Clock period 9 and after, RM9224 exports 0XF on LBCMD, expression is idle, no longer output on LBAD simultaneously.
Introduce the read operation of RM9224 below and implement, Fig. 3 is the read operation sequential synoptic diagram of RM9224, and as shown in the figure, each clock period was as follows when RM9224 implemented the read operation of peripherals:
Clock period 1, RM9224 export 0X0 on LBCMD, expression is selected 0 read operation to sheet, and the output high address, simultaneously output most-significant byte address A (23..16) on LBAD.
Clock period 2, RM9224 export 0XD on LBCMD, expression output intermediate address, output intermediate address A (15..8) on LBAD simultaneously.
Clock period 3, RM9224 export 0XC on LBCMD, expression output lowest address, output lowest address A (7..0) on LBAD simultaneously.
Clock period 4-6, RM9224 export 0X8 on LBCMD, the expression data transmission, and LBAD goes up and waits for peripherals output data D (7..0) simultaneously.
Clock period 7, RM9224 export 0X8 on LBCMD, expression data transmission, peripherals output data D (7..0) on LBAD simultaneously.
Clock period 8, RM9224 read in the data on the LBAD, export 0XF simultaneously on LBCMD, the expression end of transmission (EOT), and LBAD enters the free time, and peripherals is no longer exported.
Clock period 9 and after, RM9224 exports 0XF on LBCMD, expression is idle.
Parallel FLASH generally is used to deposit start-up code etc. as typical peripheral components.Fig. 4 is the LOCAL BUS pin synoptic diagram of FLASH, as shown in the figure, the pin of parallel FLASH is by the pin, link address bus ADDR (24 bit data width that connect control bus (CS, WR, RD), the pin of the pin 16MByte capacity), connection data bus (8 bit data width) is formed, wherein CS, WR, RD are respectively in the control bus: CS:Chip Select, sheet selected control system signal; RD:Read, read control signal; WR:Write, write control signal.
Fig. 5 is the write operation synoptic diagram of FLASH, and is as shown in the figure, as follows to the write operation flow process of parallel FLASH:
1, CPU is at ADDR OPADD A (23..0).
2, CPU is low at CS and WR output signal, expression write operation, output data D (7..0) on data line DATA simultaneously.
3, CPU draws high the signal of CS and WR output, and the expression write operation finishes, and finishes output on data line DATA.
4, CPU finishes OPADD.
Fig. 6 is the read operation synoptic diagram of FLASH, and is as shown in the figure, as follows to the read operation flow process of parallel FLASH:
1, CPU is low at CS and RD output signal at ADDR OPADD A (23..0) simultaneously, the expression read operation.
2, FLASH output data on data line DATA.
3, CPU reads in data by DATA, and the signal of CS and RD output is drawn high.
4, CPU finishes OPADD.
Because parallel FLASH has independently data bus, address bus and control bus, and the data line of the LOCAL BUS of RM9224 and address wire are multiplexing, the control bus of LBCMD and FLASH definition simultaneously is different, one is 4 lines, one is 3 lines, therefore must could realize connecting by decoding.This just makes RM9224 can not directly be connected with parallel FLASH.The method of operating and the FLASH of other peripheral components are similar, can not directly connect.
Fig. 7 is common LOCAL BUS and the transformational structure synoptic diagram of FLASH, as shown in the figure, it is present normally used local bus conversion plan, generally all use CPLD (ComplexProgrammable Logic Device, CPLD) between CPU and FLASH, to change in the prior art.
Changing under the conversion regime, each clock period was as follows when RM9224 implemented the write operation of peripherals:
Clock period 1, RM9224 export 0X4 on LBCMD, expression is selected 0 write operation to sheet, and the output high address, and CPLD is judged as write operation according to the value 0X4 of LBCMD, latchs high address A (23..16) simultaneously.
Clock period 2, RM9224 export 0XD on LBCMD, expression output intermediate address is exported intermediate address A (15..8) simultaneously on LBAD, and CPLD latchs intermediate address A (15..8).
Clock period 3, RM9224 export 0XC on LBCMD, expression output lowest address is exported lowest address A (7..0) simultaneously on LBAD, and CPLD latchs low order address A (7..0).
Clock period 4-6, RM9224 export 0XF on LBCMD, the expression idling cycle, and LBAD goes up output data D (7..0) simultaneously.
Clock period 7, RM9224 export 0X8 on LBCMD, expression data transmission, while output data D (7..0) on LBAD, CPLD latch data.
Clock period 8, RM9224 export 0XE on LBCMD, expression end of transmission (EOT), no longer output on LBAD simultaneously.
Clock period 9 and after, RM9224 exports 0XF on LBCMD, expression is idle, no longer output on LBAD simultaneously.
After clock period 9, CPLD OPADD A (23..0).CPLD output CS and WR signal are low, expression write operation, output data D (7..0) on data line simultaneously.CPLD output CS and WR signal are drawn high, and the expression write operation finishes.CPLD finishes output on data line.CPLD finishes OPADD.
Changing under the conversion regime, each clock period was as follows when RM9224 implemented the read operation of peripherals:
Clock period 1, RM9224 export 0X0 on LBCMD, expression is selected 0 read operation to sheet, and the output high address, simultaneously output most-significant byte address A (23..16) on LBAD, CPLD is judged as read operation according to the value 0X0 of LBCMD, latchs high address A (23..16) simultaneously.
Clock period 2, RM9224 export 0XD on LBCMD, expression output intermediate address is exported intermediate address A (15..8) simultaneously on LBAD, and CPLD latchs intermediate address A (15..8).
Clock period 3, RM9224 export 0XC on LBCMD, expression output lowest address, on LBAD, export lowest address A (7..0) simultaneously, CPLD latchs low order address A (7..0), and all address A (23..0) are exported to FLASH, simultaneously, CPLD is output as CS and RD signal low, the expression read operation, and remain to the clock period 7 always.
Clock period 4-6, RM9224 export 0X8 on LBCMD, the expression data transmission, and in the clock period 6, CPLD reads the data of FLASH output.
Clock period 7, RM9224 export 0X8 on LBCMD, the expression data transmission, and while peripherals output data D (7..0) on LBAD, CPLD draws high CS and RD signal, and the expression read operation finishes, and CPLD sends to LBAD (7..0) with data.
Clock period 8, RM9224 read in the data on the LBAD, export 0XF simultaneously on LBCMD, the expression end of transmission (EOT), and LBAD enters the free time, and peripherals is no longer exported, the output on the output of CPLD end address line A (23..0) and the LBAD (7..0).
Clock period 9 and after, RM9224 exports 0XF on LBCMD, expression is idle, the CPLD no-output.
From implementation process as can be seen, the deficiencies in the prior art are:
CPU is in to peripherals write operations such as FLASH, and the time that needs is longer, simultaneously, when CPLD operates peripherals, needs the resource of consumption more.
Summary of the invention
The invention provides a kind of data handling system, and utilize this system to carry out the method for data processing, in order to improve the data manipulation speed between CPU processor and the data storage device.
The invention provides a kind of data handling system, comprising:
The CPU processor is used for transmitting control commands, address information, and the line data of going forward side by side operation comprises the first control bus pin, first address and data multiplex bus pin;
Data storage device is used to store data, and carries out data manipulation according to control signal, address signal, comprises the 3rd control bus pin, the first address bus pin, data bus pins;
Converter, be used for control signal and address signal that control command that the CPU processor is sent and address information convert the data storage device form to, comprise the second control bus pin, second address and data multiplex bus pin, the 4th control bus pin, the second address bus pin;
Wherein:
The first control bus pin links to each other with the second control bus pin;
First address links to each other with the data multiplex bus pin with second address with the data multiplex bus pin;
First address links to each other with data bus pins with the data multiplex bus pin;
The 3rd control bus pin links to each other with the 4th control bus pin;
The first address bus pin links to each other with the second address bus pin.
Preferably, described the 4th control bus pin comprises a CS pin, a RD pin, a WR pin;
The 3rd control bus pin comprises the 2nd CS pin, the 2nd RD pin, the 2nd WR pin;
Wherein, comprise that a CS pin links to each other with the 2nd CS pin, a RD pin links to each other with the 2nd RD pin, a WR pin links to each other with the 2nd WR pin.
Preferably, described converter is CPLD.
Preferably, described data storage device is FLASH.
The present invention also provides a kind of data processing method of data handling system, comprises the steps:
The CPU processor is when carrying out data manipulation, by the first control bus pin, first address and data multiplex bus pin transmitting control commands and address information;
Converter converts the control signal and the address signal of data storage device form to, and is sent to data storage device after receiving control command and address information;
Data storage device is according to control signal and address signal, the data manipulation that response CPU processor is undertaken by first address and data multiplex bus pin and data storage device data bus pins.
Preferably, converter will convert the write operation control signal to and be sent to data storage device by the 4th control bus pin by the write operation control command that the second control bus pin receives;
When the CPU processor carries out write operation, send the write operation control command to converter, send data to data storage device by first address and data multiplex bus pin by the first control bus pin;
Converter will convert the write operation control signal to and be sent to data storage device by the 4th control bus pin by the write operation control command that the second control bus pin receives, and after receiving the end of transmission (EOT) control command, send end of transmission (EOT) control signaling to data storage device by the second control bus pin.
Preferably, further comprise:
When converter receives the write operation control command by the second control bus pin, latch the address information that the CPU processor receives by second address and data multiplex bus pin, and be sent to data storage device by the second address bus pin after converting address information to address signal.
Preferably, converter will convert the read operation control signal to and be sent to data storage device by the 4th control bus pin by the read operation control command that the second control bus pin receives;
When the CPU processor carries out read operation, send the read operation control command to converter, receive the data that data storage device sends by first address and data multiplex bus pin by the first control bus pin;
Converter will convert the read operation control signal to and be sent to data storage device by the 4th control bus pin by the read operation control command that the second control bus pin receives, and after receiving the end of transmission (EOT) control command, send end of transmission (EOT) control signaling to data storage device by the second control bus pin.
Preferably, further comprise:
When converter receives the read operation control command by the second control bus pin, latch the address information that the CPU processor receives by second address and data multiplex bus pin, and be sent to data storage device by the second address bus pin after converting address information to address signal.
Beneficial effect of the present invention is as follows:
In the invention process, the address of CPU processor links to each other with the data bus pins of data storage device with the data multiplex bus pin, the CPU processor is when carrying out data manipulation, by control bus pin, address and data multiplex bus pin transmitting control commands and address information; Data storage device is according to control signal and address signal, the data manipulation that response CPU processor is undertaken by address and data multiplex bus pin and data storage device data bus pins.Because the CPU processor carries out the data manipulation of peripheral components simultaneously to the data manipulation and the converter of peripheral components, for the CPU processor, the speed of whole data manipulation is unaffected.Simultaneously, because the address date multiplex bus of CPU processor and the data bus of data storage device directly link to each other, when carrying out data manipulation, data need not the processing through converter, have therefore saved the internal resource of converter.
Description of drawings
Fig. 1 is the LOCAL BUS mount structure synoptic diagram of RM9224 described in the background technology;
Fig. 2 is the write operation sequential synoptic diagram of RM9224 described in the background technology;
Fig. 3 is the read operation sequential synoptic diagram of RM9224 described in the background technology;
Fig. 4 is the LOCAL BUS pin synoptic diagram of FLASH described in the background technology;
Fig. 5 is the write operation synoptic diagram of FLASH described in the background technology;
Fig. 6 is the read operation synoptic diagram of FLASH described in the background technology;
Fig. 7 is LOCAL BUS common described in the background technology and the transformational structure synoptic diagram of FLASH;
Fig. 8 is the structural representation of data handling system described in the embodiment of the invention;
Fig. 9 is the data processing method implementing procedure synoptic diagram of data handling system described in the embodiment of the invention;
Figure 10 is that write operation described in the embodiment of the invention is implemented the sequential synoptic diagram;
Figure 11 is that the sequential synoptic diagram is implemented in read operation described in the embodiment of the invention.
Embodiment
Below in conjunction with accompanying drawing the specific embodiment of the present invention is described.
By prior art is analyzed, can find, CPU in to peripherals write operations such as FLASH, the time that needs length be because of: CPU adds the time of CPLD to the FLASH write operation to the time of CPLD write operation, causes operating speed slack-off.If under the CPU situation equal to the FLASH write operation time with CPLD to the CPLD write operation time, actual write operation speed has only half of CPU write operation speed.Simultaneously, when CPLD operates peripherals, owing to need use internal resource to carry out latching of data line D (7..0), and realize corresponding control logic, therefore need the resource of consumption more.
Based on this, the invention provides a kind of data handling system, it is: the LBCMD of converter and CPU processor is linked to each other with LBAD, and produce control signal (CS, WR, RD) and address signal to data storage device.The LBAD of CPU processor is also connected on the data line DATA of data storage device, for it provides data line interface simultaneously.Embodiment to this system describes below.
Fig. 8 is the structural representation of data handling system, as shown in the figure, can comprise in the data handling system:
CPU processor 801 is used for transmitting control commands, address information, and the line data of going forward side by side operation comprises the first control bus pin 8011, first address and data multiplex bus pin 8012;
Data storage device 802 is used to store data, and carries out data manipulation according to control signal, address signal, comprises the 3rd control bus pin 8021, the first address bus pin 8022, data bus pins 8023;
Converter 803, be used for control signal and address signal that control command that the CPU processor is sent and address information convert the data storage device form to, comprise the second control bus pin 8031, second address and data multiplex bus pin 8032, the 4th control bus pin 8033, the second address bus pin 8034;
Wherein:
The first control bus pin 8011 links to each other with the second control bus pin 8031;
First address links to each other with data multiplex bus pin 8032 with second address with data multiplex bus pin 8012;
First address links to each other with data bus pins 8023 with data multiplex bus pin 8012;
The 3rd control bus pin 8021 links to each other with the 4th control bus pin 8033;
The first address bus pin 8022 links to each other with the second address bus pin 8034.
Concrete, can comprise a CS pin, a RD pin, a WR pin in the 3rd control bus pin 8021;
Can comprise the 2nd CS pin, the 2nd RD pin, the 2nd WR pin in the 4th control bus pin 8033;
Wherein, comprise that a CS pin links to each other with the 2nd CS pin, a RD pin links to each other with the 2nd RD pin, a WR pin links to each other with the 2nd WR pin.
In the enforcement, converter can adopt CPLD to realize, as long as the soft hardware equipment that sends after also promptly can changing the signal that receives can be implemented.
Data storage device can adopt FLASH to realize, knows easily, so long as can store data, and can be used for implementing according to the equipment that control signal, address signal carry out data manipulation.
Also will adopt CPLD to realize converter in the following enforcement, adopt FLASH to realize that data storage device describes.
Utilize this data handling system, the present invention also provides a kind of corresponding data processing methods, below this disposal route is described.
Fig. 9 is the data processing method implementing procedure synoptic diagram of data handling system, as shown in the figure, when data handling system is carried out data processing, can comprise the steps:
Step 901, CPU processor are when carrying out data manipulation, by the first control bus pin, first address and data multiplex bus pin transmitting control commands and address information;
Step 902, converter convert the control signal and the address signal of data storage device form to, and are sent to data storage device after receiving control command and address information;
Step 903, data storage device be according to control signal and address signal, the data manipulation that response CPU processor is undertaken by first address and data multiplex bus pin and data storage device data bus pins.
Be respectively write operation with data manipulation below and read operation is that example describes.
One, the enforcement of write operation.
Converter will convert the write operation control signal to and be sent to data storage device by the 4th control bus pin by the write operation control command that the second control bus pin receives;
When the CPU processor carries out write operation, send the write operation control command to converter, send data to data storage device by first address and data multiplex bus pin by the first control bus pin;
Converter will convert the write operation control signal to and be sent to data storage device by the 4th control bus pin by the write operation control command that the second control bus pin receives, and after receiving the end of transmission (EOT) control command, send end of transmission (EOT) control signaling to data storage device by the second control bus pin.
Further, can also comprise:
When converter receives the write operation control command by the second control bus pin, latch the address information that the CPU processor receives by second address and data multiplex bus pin, and be sent to data storage device by the second address bus pin after converting address information to address signal.
In implementing below, adopting CPLD, peripheral data memory storage to adopt FLASH with CPU processor adopting RM9224, converter is the enforcement that example describes write operation.Figure 10 implements the sequential synoptic diagram for write operation, and as shown in the figure, each clock period was as follows when RM9224 carried out write operation to peripherals FLASH:
Clock period 1, M9224 export 0X4 on LBCMD, expression is selected 0 write operation to sheet, and the output high address.CPLD is judged as write operation according to the value 0X4 of LBCMD, latchs high address A (23..16) simultaneously, exports to FLASH.
Clock period 2, RM9224 export 0XD on LBCMD, expression output intermediate address.On LBAD, export intermediate address A (15..8) simultaneously.
CPLD latchs intermediate address A (15..8), exports to FLASH.
Clock period 3, RM9224 export 0XC on LBCMD, expression output lowest address.On LBAD, export lowest address A (7..0) simultaneously.CPLD latchs low order address A (7..0), exports to FLASH.Though the clock period 1～3, CPLD is always to FLASH OPADD information, and up to the clock period 3, just to FLASH output sufficient address signal, the output of the ADDR shown in the figure refers to address signal to CPLD.
Clock period 4-6, RM9224 export 0XF on LBCMD, the expression idling cycle.
Simultaneously, the last output data D of LBAD (7..0) is to FLASH.And in the clock period 4, CPLD is output as CS and WR signal low, the expression write operation, and remain to the clock period 6 always.
In this clock period, data need keep a period of time before the write operation.Really write data and be at CS and WR in low uprising, promptly write in the clock period 7.7 all is the same data from the cycle 4 to the cycle.
Unlike the prior art be, not only carry out RM9224 and on LBCMD, export 0XF, the expression idling cycle.Simultaneously, the last output data D of LBAD (7..0) to as if FLASH, and in the clock period 4, CPLD is output as CS and WR signal low, expression write operation, and always remaining to the clock period 6.
Clock period 7, RM9224 export 0X8 on LBCMD, the expression data transmission.While output data D (7..0) on LBAD.CPLD judges that according to the value 0X8 of LBCMD write operation finishes, and draws high CS and WR.
Unlike the prior art be CPLD latch data not in this clock period, and CPLD will judge that write operation finishes, and draws high CS and WR according to the value 0X8 of LBCMD.
Clock period 8, RM9224 export 0XE on LBCMD, the expression end of transmission (EOT).Output data no longer on LBAD simultaneously.No longer export the address of CPLD.
In this clock period, output data no longer on LBAD not only, also no longer output of the address signal of CPLD simultaneously.
Clock period 9 and after, RM9224 exports 0XF on LBCMD, expression is idle.No longer output on LBAD simultaneously.CPLD is action not.
Unlike the prior art, after this clock period, CPLD will no longer carry out action.And in the prior art, after the clock period 9, CPLD also need carry out:
OPADD A (23..0);
Output CS and WR signal are low, the expression write operation.While output data D (7..0) on data line; Output CS and WR signal are drawn high, and the expression write operation finishes;
On data line, finish output;
Finish OPADD.
As seen, in write operation is implemented,, can reduce the execution time, reduce resource consumption by saving the execution of CPLD.
Two, the enforcement of read operation.
Converter will convert the read operation control signal to and be sent to data storage device by the 4th control bus pin by the read operation control command that the second control bus pin receives;
When the CPU processor carries out read operation, send the read operation control command to converter, receive the data that data storage device sends by first address and data multiplex bus pin by the first control bus pin;
Converter will convert the read operation control signal to and be sent to data storage device by the 4th control bus pin by the read operation control command that the second control bus pin receives, and after receiving the end of transmission (EOT) control command, send end of transmission (EOT) control signaling to data storage device by the second control bus pin.
Further, can also comprise:
When converter receives the read operation control command by the second control bus pin, latch the address information that the CPU processor receives by second address and data multiplex bus pin, and be sent to data storage device by the second address bus pin after converting address information to address signal.
Same, in implementing below, adopting CPLD, peripheral data memory storage to adopt FLASH with CPU processor adopting RM9224, converter is the enforcement that example describes read operation.Figure 11 implements the sequential synoptic diagram for read operation, and as shown in the figure, each clock period was as follows when RM9224 carried out read operation to peripherals FLASH:
Clock period 1, RM9224 export 0X0 on LBCMD, expression is selected 0 read operation to sheet, and the output high address.On LBAD, export most-significant byte address A (23..16) simultaneously.CPLD is judged as read operation according to the value 0X0 of LBCMD, latchs high address A (23..16) simultaneously, exports to FLASH.
Clock period 2, RM9224 export 0XD on LBCMD, expression output intermediate address.On LBAD, export intermediate address A (15..8) simultaneously.CPLD latchs intermediate address A (15..8), exports to FLASH.
Clock period 3, RM9224 export 0XC on LBCMD, expression output lowest address.On LBAD, export lowest address A (7..0) simultaneously.CPLD latchs low order address A (7..0), exports to FLASH.Simultaneously, CPLD is output as CS and RD signal low, the expression read operation, and remain to the clock period 7 always.
In this clock period, compared with prior art, after CPLD latchs low order address A (7..0), all address A (23..0) need not be exported to FLASH.
Clock period 4-6, RM9224 export 0X8 on LBCMD, the expression data transmission.LBAD goes up and waits for FLASH output data D (7..0) simultaneously.
In this clock period, prior art is: RM9224 exports 0X8 on LBCMD, the expression data transmission.In the clock period 6, CPLD reads the data of FLASH output.
And, among the embodiment, behind output 0X8 on the LBCMD, can wait for just on the LBAD that peripherals FLASH output data D (7..0).
Clock period 7, the RM9224 0X8 that on LBCMD, publishes books, the expression data transmission.While FLASH output data D (7..0) on LBAD.CPLD draws high CS and R signal, and the expression read operation finishes.
In this clock period, prior art is: RM9224 exports 0X8 on LBCMD, the expression data transmission.While FLASH output data D (7..0) on LBAD.CPLD draws high CS and R signal, and the expression read operation finishes.Then, CPLD also needs data are sent to LBAD (7..0).And in the present embodiment owing to data and without CPLD, so CPLD need not carry out this step.
Clock period 8, RM9224 read in the data on the LBAD.On LBCMD, export simultaneously 0XF, the expression end of transmission (EOT), LBAD enters the free time.FLASH no longer exports.The output of CPLD end address line A (23..0).
In this clock period, prior art is: RM9224 reads in the data on the LBAD.On LBCMD, export simultaneously 0XF, the expression end of transmission (EOT), LBAD enters the free time.FLASH no longer exports.The output of CPLD end address line A (23..0), CPLD also need carry out the output on the LBAD (7..0).And in the present embodiment owing to data and without CPLD, so CPLD need not carry out this step.
Clock period 9 and after, RM9224 exports 0XF on LBCMD, expression is idle.The CPLD no-output.
Execution by each clock period in implementing is compared, and in read operation, by saving the execution of CPLD, can reduce the execution time as can be known, reduces resource consumption.
By above-mentioned enforcement, as can be seen, in the invention process, the LBCMD and the LBAD of CPU processor is connected to data storage device, output control bus of converter (CS, WR, RD) and address bus offer the peripheral components data storage device.The LBAD of CPU processor is connected on the data bus of peripheral data memory storage simultaneously, in order to data channel to be provided.
Then, converter is according to LBCMD judgment data action type, and output control signal corresponding (CS, RD, WR) is given the peripheral components data storage device.
Further, converter is according to the LBCMD latch address, and exports to the peripheral components data storage device.
Through above scheme, just can guarantee the data manipulation of CPU processor and peripheral components data storage device.And owing to data manipulation and the converter of CPU processor to peripheral components carries out simultaneously to the data manipulation of peripheral components, for the CPU processor, the speed of whole data manipulation is unaffected.Simultaneously, because the address date multiplex bus of CPU processor and the data bus of data storage device directly link to each other, when carrying out data manipulation, data need not the processing through converter, have therefore saved the internal resource of converter.
Obviously, those skilled in the art can carry out various changes and modification to the present invention and not break away from the spirit and scope of the present invention.Like this, if of the present invention these are revised and modification belongs within the scope of claim of the present invention and equivalent technologies thereof, then the present invention also is intended to comprise these changes and modification interior.

Claims (9)

1, a kind of data handling system is characterized in that, comprising:
The CPU processor is used for transmitting control commands, address information, and the line data of going forward side by side operation comprises the first control bus pin, first address and data multiplex bus pin;
Data storage device is used to store data, and carries out data manipulation according to control signal, address signal, comprises the 3rd control bus pin, the first address bus pin, data bus pins;
Converter, be used for control signal and address signal that control command that the CPU processor is sent and address information convert the data storage device form to, comprise the second control bus pin, second address and data multiplex bus pin, the 4th control bus pin, the second address bus pin;
Wherein:
The first control bus pin links to each other with the second control bus pin;
First address links to each other with the data multiplex bus pin with second address with the data multiplex bus pin;
First address links to each other with data bus pins with the data multiplex bus pin;
The 3rd control bus pin links to each other with the 4th control bus pin;
The first address bus pin links to each other with the second address bus pin.
2, the system as claimed in claim 1 is characterized in that, described the 4th control bus pin comprises first selected control system signal pins, the first read control signal pin, the first write control signal pin;
The 3rd control bus pin comprises second selected control system signal pins, second reading control signal pin, the second write control signal pin;
Wherein, comprise that first selected control system signal pins links to each other with second selected control system signal pins, the first read control signal pin links to each other with second reading control signal pin, the first write control signal pin links to each other with the second write control signal pin.
3, the system as claimed in claim 1 is characterized in that, described converter is CPLD.
4, the system as claimed in claim 1 is characterized in that, described data storage device is FLASH.
5, the data processing method of data handling system described in a kind of claim 1 is characterized in that, comprises the steps:
The CPU processor is when carrying out data manipulation, by the first control bus pin, first address and data multiplex bus pin transmitting control commands and address information;
Converter converts the control signal and the address signal of data storage device form to, and is sent to data storage device after receiving control command and address information;
Data storage device is according to control signal and address signal, the data manipulation that response CPU processor is undertaken by first address and data multiplex bus pin and data storage device data bus pins.
6, method as claimed in claim 5 is characterized in that,
Converter will convert the write operation control signal to and be sent to data storage device by the 4th control bus pin by the write operation control command that the second control bus pin receives;
When the CPU processor carries out write operation, send the write operation control command to converter, send data to data storage device by first address and data multiplex bus pin by the first control bus pin;
Converter will convert the write operation control signal to and be sent to data storage device by the 4th control bus pin by the write operation control command that the second control bus pin receives, and after receiving the end of transmission (EOT) control command, send end of transmission (EOT) control signaling to data storage device by the second control bus pin.
7, method as claimed in claim 6 is characterized in that, further comprises:
When converter receives the write operation control command by the second control bus pin, latch the address information that the CPU processor receives by second address and data multiplex bus pin, and be sent to data storage device by the second address bus pin after converting address information to address signal.
8, method as claimed in claim 5 is characterized in that,
Converter will convert the read operation control signal to and be sent to data storage device by the 4th control bus pin by the read operation control command that the second control bus pin receives;
When the CPU processor carries out read operation, send the read operation control command to converter, receive the data that data storage device sends by first address and data multiplex bus pin by the first control bus pin;
Converter will convert the read operation control signal to and be sent to data storage device by the 4th control bus pin by the read operation control command that the second control bus pin receives, and after receiving the end of transmission (EOT) control command, send end of transmission (EOT) control signaling to data storage device by the second control bus pin.
9, method as claimed in claim 8 is characterized in that, further comprises:
When converter receives the read operation control command by the second control bus pin, latch the address information that the CPU processor receives by second address and data multiplex bus pin, and be sent to data storage device by the second address bus pin after converting address information to address signal.
CNB200810105630XA 2008-04-30 2008-04-30 A kind of data handling system and data processing method Expired - Fee Related CN100552660C (en)

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