CN214586880U

CN214586880U - Information processing apparatus

Info

Publication number: CN214586880U
Application number: CN202121014456.5U
Authority: CN
Inventors: 邓勇; 刘宗瑶
Original assignee: Hunan Zetian Zhihang Electronic Technology Co ltd
Current assignee: Hunan Zetian Zhihang Electronic Technology Co ltd
Priority date: 2021-05-12
Filing date: 2021-05-12
Publication date: 2021-11-02
Anticipated expiration: 2031-05-12

Abstract

The utility model discloses an information processing equipment, including the CPU module, first FPGA module, the second FPGA module, SRIO switch module and network switch module, wherein, the CPU module respectively with first FPGA module, the second FPGA module, SRIO switch module and network switch module electricity are connected, SRIO switch module is connected with first FPGA module and second FPGA module electricity respectively, network switch module is connected with first FPGA module and second FPGA module electricity respectively, the CPU module is as the control unit, be used for carrying out the information interaction respectively between SRIO switch module and/or the network switch module and first FPGA module and/or the second FPGA module. The utility model discloses an information processing device, the information processing real-time is high, the processing speed is fast; and is easy to maintain or expand.

Description

Information processing apparatus

Technical Field

The utility model relates to a data processing equipment technical field especially discloses an information processing equipment.

Background

With the continuous development of modern information technology, the rapid interaction and processing of information play more and more important roles in the fields of internet, industrial control, national defense and the like.

Application publication is CN 110737219A's patent document discloses a digital signal processing equipment based on DSP, including the DSP treater, FPGA treater, storage module, SRIO exchange module, PCIE exchange module, GE exchange module and panel, the DSP treater is equipped with four, every DSP treater is all to carry storage module, and every DSP treater equally divide respectively with the FPGA treater, SRIO exchange module, PCIE exchange module and GE exchange module are connected, be equipped with the VPX connector on the panel, the FPGA treater respectively with SRIO exchange module, PCIE exchange module and GE exchange module are connected, SRIO exchange module, PCIE exchange module and GE exchange module still dock with the VPX connector respectively, wherein: the SRIO switching module, the PCIE switching module and the GE switching module are respectively used for supporting SRIO, PCIe and SGMII bus protocols, receiving digital signals accessed by different bus protocols from a VPX connector and transmitting the digital signals to the FPGA processor, the FPGA processor is used for preprocessing the digital signals accessed by the VPX connector and polling the working states of the four DSP processors, selecting an idle DSP processor to input a preprocessing result, then controlling the selected DSP processor to access the digital signals from the SRIO switching module or the PCIE switching module or the GE switching module to perform main task processing, the selected DSP processor combines the preprocessing result and the main task processing result and then performs signal playback from an original channel accessed with the digital signals, and the storage module is used for storing processing data of the DSP processor and a time sequence configuration mode. However, the existing digital signal processing equipment adopts a single FPGA, and has low processing speed and poor real-time performance.

Therefore, the existing digital signal processing equipment has low processing speed and poor real-time performance, and is a technical problem to be solved urgently.

SUMMERY OF THE UTILITY MODEL

The utility model provides an information processing equipment aims at solving the technical problem that current digital signal processing equipment processing speed is slow and the real-time is poor.

The utility model provides an information processing equipment, including the CPU module, first FPGA module, second FPGA module, SRIO switch module and network switch module, wherein, the CPU module respectively with first FPGA module, second FPGA module, SRIO switch module and network switch module electricity are connected, SRIO switch module is connected with first FPGA module and second FPGA module electricity respectively, network switch module is connected with first FPGA module and second FPGA module electricity respectively, the CPU module is as the control unit, be used for carrying out the information interaction respectively between SRIO switch module and/or the network switch module and first FPGA module and/or the second FPGA module through SRIO switch module and/or network switch module.

Furthermore, the information processing device also comprises a first network bridge chip module arranged between the SRIO switching module and the CPU module.

Furthermore, the information processing device also comprises a second network bridge chip module arranged between the network exchange module and the CPU module.

Further, the first FPGA module is electrically connected with the second FPGA module.

Further, the CPU module comprises a FT2000/4 chip.

Further, the CPU module is in communication connection with the first FPGA module and the second FPGA module through a PCIE X8 interface, respectively.

Further, the first FPGA module and the second FPGA module each include XC7VX690T80 chips from Xilinx corporation.

Further, the SRIO switch module includes an NRS1800 chip.

Further, the first network bridge module and the second network bridge module each include a TSI721 chip.

Further, the network switching module is an ethernet switching module, and the ethernet switching module includes a BCM5396 chip.

The utility model discloses the beneficial effect who gains does:

the utility model discloses an information processing equipment adopts CPU module, first FPGA module, second FPGA module, SRIO switching module and network switching module to integrated two FPGA modules can parallel process throughput is big, the high information data of bandwidth, can realize the communication mode of multiprotocol, multichannel, multiple speed, for ordinary information processing equipment, has that the information processing real-time is high, easy to maintain or extension. The utility model discloses an information processing device, which has high real-time performance and high processing speed of information processing; and is easy to maintain or expand.

Drawings

Fig. 1 is a functional block diagram of a first embodiment of an information processing apparatus provided by the present invention;

fig. 2 is a functional block diagram of a second embodiment of the information processing apparatus provided by the present invention.

The reference numbers illustrate:

10. a CPU module; 20. a first FPGA module; 30. a second FPGA module; 40. an SRIO switching module; 50. a network switching module; 60. a first network bridge piece module; 70. and a second network bridge piece module.

Detailed Description

In order to better understand the technical solution, the technical solution will be described in detail with reference to the drawings and the specific embodiments.

As shown in fig. 1 and fig. 2, a first embodiment of the present invention provides an information processing device, including a CPU module 10, a first FPGA module 20, a second FPGA module 30, a SRIO switching module 40 and a network switching module 50, wherein the CPU module 10 is respectively electrically connected to the first FPGA module 20, the second FPGA module 30, the SRIO switching module 40 and the network switching module 50, the SRIO switching module 40 is respectively electrically connected to the first FPGA module 20 and the second FPGA module 30, the network switching module 50 is respectively electrically connected to the first FPGA module 20 and the second FPGA module 30, the CPU module 10 serves as a control unit, and is configured to perform information interaction with the first FPGA module 20 and/or the second FPGA module 30 through the SRIO switching module 40 and/or the network switching module 50. In the present embodiment, the routing table of SRIO switching is configured by the CPU module 10.

As shown in fig. 2, fig. 2 is a functional block diagram of a second embodiment of the information processing apparatus according to the present invention, and on the basis of the first embodiment, the information processing apparatus further includes a first network bridge piece module 60 disposed between the SRIO switching module 40 and the CPU module 10, and a second network bridge piece module 70 disposed between the network switching module 50 and the CPU module 10. The first network bridge chip module 60 is responsible for protocol conversion between the CPU module 10 and the SRIO switching module 40; the second network bridge module 70 is responsible for protocol conversion between the CPU module 10 and the network switching module 50. The CPU module 10 configures internal logic modules of the first FPGA module 20 and the second FPGA module 30 through a PCIE interface; the first FPGA module 20 and the second FPGA module receive external data, process the external data, and upload the external data to the CPU module 10 in a DMA (Direct Memory Access) manner. In the present embodiment, the first FPGA module 20 is electrically connected to the second FPGA module 30. The first FPGA module 20 and the second FPGA module 30 perform information interaction through SRIO and an ethernet protocol. Different SRIO rates can be selected according to configuration, the Ethernet is gigabit Ethernet, and the Ethernet adopts UDP protocol for communication. The CPU module 10 includes a FT2000/4 chip. The CPU module 10 is in communication connection with the first FPGA module 20 and the second FPGA module 30 through a PCIE X8 interface. The first FPGA module 20 and the second FPGA module 30 each include XC7VX690T80 chips from Xilinx corporation. The SRIO switch module 40 includes an NRS1800 chip. The first network bridge module 60 and the second network bridge module 70 each include a TSI721 chip. The network switching module 50 adopts an ethernet switching module, and the ethernet switching module includes a BCM5396 chip. The first FPGA module 20 and the second FPGA module 30 are 4GB DDR3 SDRAM onboard. The SRIO switching module 40 is responsible for SRIO data switching of each module, and the CPU module 10, the first FPGA module 20, and the second FPGA module 30 exchange information with an external module through the SRIO switching module 40.

Referring to fig. 2, the working principle of the information processing apparatus provided in this embodiment is as follows:

after power-on, the external information passes through the SRIO switching module 40, and the SRIO switching module 40 distributes the external information to the first FPGA module 20, the second FPGA module 30, and the CPU module 10 according to the routing information. After receiving the information, the CPU module 10 may respectively send the processed information to the first FPGA module 20 and the second FPGA module 30 through a PCIE (peripheral component interconnect express, high speed serial computer expansion bus standard), and send the information out through the SRIO switching module 40 after the information is processed by the first FPGA module 20 and the second FPGA module 30; the CPU module 10 may also send the information through the SR1O switching module 40 after receiving the information; meanwhile, external information is sent to the first FPGA module 20 and the second FPGA module 30 through the SRIO switching module 40, and after the first FPGA module 20 and the second FPGA module 30 analyze data, the data is processed and then sent to the CPU module 10 through the PCIE interface.

After power-on, the external information passes through the network switching module 50, and the network switching module 50 distributes the external information to the first FPGA module 20, the second FPGA module 30 and the CPU module 10 according to the routing information. After receiving the information, the CPU module 10 may send the information to the first FPGA module 20 and the second FPGA module 30 through PCIE after processing, and send the information out through the network switch chip after the information is processed and completed by the first FPGA module 20 and the second FPGA module 30; the CPU can also send out the information through the network switching module 50 after receiving the information; meanwhile, the external information is sent to the first FPGA module 20 and the second FPGA module 30 through the network switching module 50, and after the first FPGA module 20 and the second FPGA module 30 analyze the data, the data is processed and then sent to the CPU module 10 through the PCIE interface.

Compared with the prior art, the information processing equipment disclosed by the embodiment adopts the CPU module, the first FPGA module, the second FPGA module, the SRIO switching module and the network switching module, so that double FPGA modules are integrated, information data with high throughput and high bandwidth can be processed in parallel, a multi-protocol, multi-channel and multi-speed communication mode can be realized, and compared with common information processing equipment, the information processing equipment has the advantages of high information processing real-time performance and easiness in maintenance or expansion. The information processing equipment disclosed by the embodiment has high information processing real-time performance and high processing speed; and is easy to maintain or expand.

While the preferred embodiments of the present invention have been described, additional variations and modifications in those embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. It is therefore intended that the appended claims be interpreted as including the preferred embodiment and all such alterations and modifications as fall within the scope of the invention. It will be apparent to those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the invention. Thus, if such modifications and variations of the present invention fall within the scope of the claims and their equivalents, the present invention is also intended to include such modifications and variations.

Claims

1. An information processing device is characterized by comprising a CPU module (10), a first FPGA module (20), a second FPGA module (30), an SRIO switching module (40) and a network switching module (50), wherein the CPU module (10) is respectively electrically connected with the first FPGA module (20), the second FPGA module (30), the SRIO switching module (40) and the network switching module (50), the SRIO switching module (40) is respectively electrically connected with the first FPGA module (20) and the second FPGA module (30), the network switching module (50) is respectively electrically connected with the first FPGA module (20) and the second FPGA module (30), the CPU module (10) is used as a control unit, the FPGA module is used for information interaction with the first FPGA module (20) and/or the second FPGA module (30) through the SRIO switching module (40) and/or the network switching module (50).

2. The information processing apparatus according to claim 1, further comprising a first network bridge module (60) provided between the SRIO switch module (40) and the CPU module (10).

3. The information processing apparatus according to claim 2, further comprising a second network bridge module (70) provided between the network switching module (50) and the CPU module (10).

4. The information processing apparatus according to claim 1, wherein the first FPGA module (20) is electrically connected to the second FPGA module (30).

5. The information processing apparatus according to claim 1, wherein the CPU module (10) includes a FT2000/4 chip.

6. The information processing apparatus according to claim 1, wherein the CPU module (10) is communicatively connected to the first FPGA module (20) and the second FPGA module (30) via a PCIE X8 interface, respectively.

7. The information processing apparatus according to claim 1, wherein the first FPGA module (20) and the second FPGA module (30) each comprise XC7VX690T80 chips of Xilinx corporation.

8. The information processing apparatus according to claim 1, wherein the SRIO switching module (40) includes an NRS1800 chip.

9. The information processing apparatus of claim 3, wherein the first network bridge module (60) and the second network bridge module (70) each comprise a TSI721 chip.

10. The information processing apparatus according to claim 1, wherein the network switching module (50) is an ethernet switching module including a BCM5396 chip.