CN110417780B - Multi-channel high-speed data interface conversion module of customized data transmission protocol - Google Patents
Multi-channel high-speed data interface conversion module of customized data transmission protocol Download PDFInfo
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- CN110417780B CN110417780B CN201910694982.1A CN201910694982A CN110417780B CN 110417780 B CN110417780 B CN 110417780B CN 201910694982 A CN201910694982 A CN 201910694982A CN 110417780 B CN110417780 B CN 110417780B
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
- H04L1/0078—Avoidance of errors by organising the transmitted data in a format specifically designed to deal with errors, e.g. location
- H04L1/0083—Formatting with frames or packets; Protocol or part of protocol for error control
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L12/00—Data switching networks
- H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
- H04L12/40—Bus networks
- H04L12/40006—Architecture of a communication node
- H04L12/40032—Details regarding a bus interface enhancer
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L69/00—Network arrangements, protocols or services independent of the application payload and not provided for in the other groups of this subclass
- H04L69/06—Notations for structuring of protocol data, e.g. abstract syntax notation one [ASN.1]
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L69/00—Network arrangements, protocols or services independent of the application payload and not provided for in the other groups of this subclass
- H04L69/08—Protocols for interworking; Protocol conversion
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L69/00—Network arrangements, protocols or services independent of the application payload and not provided for in the other groups of this subclass
- H04L69/16—Implementation or adaptation of Internet protocol [IP], of transmission control protocol [TCP] or of user datagram protocol [UDP]
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L12/00—Data switching networks
- H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
- H04L12/40—Bus networks
- H04L2012/40208—Bus networks characterized by the use of a particular bus standard
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Abstract
A multi-channel high-speed data interface conversion module of a customized data transmission protocol relates to the technical field of satellite ground test, and aims to solve the problem that the data information of a customized high-speed parallel interface is difficult to obtain in the satellite test process in the prior art; carrying interface data; step three, data storage and format encapsulation; step four, transplanting and modifying the lightweight Ethernet protocol stack; and step five, data transmission based on the lightweight Ethernet protocol stack. The invention has the advantages of customizable interface protocol, 30% improvement of data transmission speed, multiple accessible channels and the like, can acquire high-speed LVDS interface signals in a specified protocol format, converts the high-speed LVDS interface signals into standard Ethernet protocol data and outputs the standard Ethernet protocol data to a client.
Description
Technical Field
The invention relates to the technical field of satellite ground test, in particular to a multi-channel high-speed data interface conversion module.
Background
The satellite ground test is a key link for ensuring the normal work of the satellite, and the processing module for converting the special satellite interface data format into the universal Ethernet interface data format of the ground equipment is the key for realizing controllable process, visible result and information comparison. With the diversification and customization of satellite tasks, more and more data need to be transmitted among different single machines, interfaces among the single machines are mostly high-speed LVDS parallel signals with personalized data protocols, although the LVDS signals have the advantages of high transmission speed, low power consumption, strong anti-interference capability and the like, in the functional test and verification stage, due to the characteristics of high customization degree, high data parallelism and the like, the data content of the LVDS interfaces is difficult to obtain, and great inconvenience is brought to the work of ground test, fault removal, data content comparison and the like of the satellite.
The customized data transmission protocol is an important component of the complete autonomy of satellite development in China, designers can get rid of various limitations of data formats, interface hardware, channel bandwidth and the like in standard protocols, and more efficient interface protocols are designed according to the actual requirements of application functions. This provides a more efficient solution for satellite functionality, but also places higher demands on ground test equipment for functional testing. The common solution is to design a specific decoding single machine for a specific protocol, and convert an interface of a specific data format into an ethernet protocol format and output the ethernet protocol format to a server or an information testing terminal. Although the method can effectively solve the problem of difficult test of customized protocol data, the hardware design is often relatively high in pertinence, namely, a special single machine for testing the special test equipment cannot realize that one set of hardware is suitable for all or most test environments, so that the problem is that the hardware needs to be redesigned if the interface protocol is slightly changed, and thus, great waste is caused in the aspects of test cost, personnel consumption, equipment development cycle and the like. In addition, the conventional interface switching system is usually in the form of a single machine or a cabinet, and has a large volume and heavy weight, and is very inconvenient to move in a complex test plant environment. Therefore, designing a multi-channel high-speed data interface conversion module which can meet the requirement of a protocol customized data transmission protocol and has strong universality is an important problem to be solved urgently in the field of satellite testing at present.
Disclosure of Invention
The purpose of the invention is: in order to solve the problem that the data information of a customized high-speed parallel interface is difficult to obtain in the satellite testing process in the prior art, a multi-channel high-speed data interface conversion module of a customized data transmission protocol is provided.
The technical scheme adopted by the invention to solve the technical problems is as follows: the multi-channel high-speed data interface conversion module for customizing a data transmission protocol, which realizes multi-channel high-speed data transmission, comprises the following steps:
the method comprises the following steps: designing a multi-channel parallel receiving logic unit by using programmable logic resources in ZYNQ UltraScale + MPSoC, and storing received multi-channel data into an on-chip random access memory;
step two: designing a transmission controller by using programmable logic resources, judging whether the data meets transmission conditions by using the transmission controller, and controlling a data transmission unit to carry the received original data if the data meets the transmission conditions;
step three: writing the carried data into a fixed address area of an external cache through a data transmission unit, and completing splicing and packaging of data packets in the cache according to a Cortex HDR protocol format;
step four: transplanting a lightweight Ethernet protocol stack to an ARM processor in ZYNQ UltraScale + MPSoC, and changing a protocol stack program to realize multi-port communication in the same network segment;
step five: writing a receiving and sending function of TCP/IP protocol data, receiving client data request information, directly reading from the cache address and sending data.
Further, the specific steps of the first step are as follows: firstly, an external interface hardware circuit is designed to convert LVDS differential signals into single-ended data signals meeting the input signal requirements of a processor, and the interface circuit is designed to be completely isolated from the interior of a switching module; and then, matching the time sequence relation of the input signals according to a customized interface protocol time sequence diagram, reading the input signals by using a high-speed clock sampling mode, storing the obtained binary signals into an on-chip random access memory, and counting the read data frames.
Further, the second step comprises the following specific steps: firstly, reading a frame count value in the first step, then judging whether the capacity of the on-chip memory reaches a half-full state by using a transmission controller according to the preset capacity of the on-chip memory, if the capacity of the on-chip memory reaches the half-full state, determining that a one-time data transmission condition is met, at the moment, sending a configuration and control instruction to a data transmission unit in the programmable logic resource by the transmission controller through a command control bus, and starting one-time transmission, wherein the transmission data volume is half of the total capacity of the on-chip memory.
Further, the third step comprises the following specific steps: the method comprises the steps of firstly, directly writing data in an on-chip memory into an external cache through a data transmission unit, dividing special cache regions with different sizes according to the total amount of channel data to carry out circular covering type storage, and simultaneously, respectively writing a protocol frame head and a frame tail which are calculated according to a format specified by a Cortex HDR protocol and channel data frame attributes into an address region used for storing a data frame in the cache regions.
Further, the fourth step specifically comprises: firstly, a lightweight Ethernet protocol stack is transplanted to an ARM processor in a ZYNQ UltraScale + platform, then protocol stack parameters are set, and an internet access registration function and an IP matching function in the protocol stack are modified.
Further, the concrete steps of the fifth step are as follows: firstly, writing a receiving and sending function of TCP/IP protocol data, then receiving data sent by a fixed IP address of a designated port, directly reading the content of a cache region in the third step by the sending function after receiving a data sending request, and sending the cache data to client software by a TCP/IP protocol.
The invention has the beneficial effects that: the invention has the advantages of customizable interface protocol, 30% improvement of data transmission speed, multiple accessible channels and the like, can acquire high-speed LVDS interface signals in a specified protocol format, converts the high-speed LVDS interface signals into standard Ethernet protocol data and outputs the standard Ethernet protocol data to a client.
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FIG. 1 is a block diagram of the overall design of the hardware components of the present invention.
FIG. 2 is a functional design block diagram of the present invention.
Detailed Description
The first embodiment is as follows: specifically describing the embodiment with reference to fig. 1 and fig. 2, the embodiment performs interface conversion on 4-channel high-speed data output by a satellite data transmission unit in a Cortex HDR protocol format to implement the intended function, specifically according to the following steps:
step one, receiving multi-channel customized interface protocol data by adopting a high-performance programmable system on a chip.
Firstly, an external interface hardware circuit is designed to convert LVDS differential signals into single-ended data signals meeting the requirement of input signals of a processor, and in order to ensure the safety of satellite testing, an interface circuit is designed in a manner of being completely isolated from the interior of a switching module; and then, designing a customized interface logic circuit by utilizing programmable logic resources (PL part) in the high-performance ZYNQ UltraScale + MPSoC according to a satellite data transmission single-machine output data protocol format, matching the time sequence relation of input signals according to an interface protocol time sequence diagram, reading the input signals in a high-speed clock sampling mode, wherein each 8192bit is a data frame, storing the data frame into a FIFO (first in first out) in a 32-bit width manner, and recording the number of the received data frames in real time. Each group of data channels is designed in the above manner, and interface logic is customized according to a corresponding transmission protocol.
And step two, carrying interface data.
And designing a transmission controller by using the programmable logic resource, reading the count value of the received data frame in real time, when the original data obtained in the step one is accumulated in the FIFO to be more than half of the total capacity, firstly sending a read data request to the FIFO by the transmission controller, then sending a configuration instruction to a DMA unit in the programmable logic resource through an AXI Lite bus and starting one-time DMA transmission, wherein the total amount of the transmitted data is half of the capacity of the FIFO. Each data channel is provided with a DMA unit for data transmission, and the data input and output of the DMA are read and transmitted in an AXI Stream bus form.
Step three, data storage and format encapsulation
And continuously carrying the data in the FIFO of each channel to an external DDR cache through the DMA unit, and dividing the DDR into a plurality of special cache regions with proper sizes according to the data code rate of each channel. Because the satellite load data needs to be sent in a Cortex HDR protocol format, before the data starts to be transmitted, the data content of a protocol frame head and a frame tail is calculated according to the specified format of the Cortex HDR protocol and the attribute of a channel data frame, and the data content is written into a frame head address bit and a frame tail address bit in a corresponding cache region. When the data starts to be transmitted, the data frame of the corresponding channel is only needed to be written into the address interval between the frame head and the frame tail, and the data splicing and the protocol format packaging are completed.
Step four, transplanting and modifying the lightweight Ethernet protocol stack
And transplanting a lightweight Ethernet protocol stack (LWIP) to an ARM processor in a ZYNQ UltraScale + platform to serve as a server, and improving the efficiency of the protocol stack by setting parameters of the protocol stack. Because the lightweight Ethernet protocol stack applicable to the embedded platform only distinguishes IP address devices of different network ends in the data communication process, the communication function of multiple network ports and network segments cannot be realized. Therefore, aiming at the problem of IP address communication in the same network segment, the IP matching function in the protocol stack is modified, the last bit matching function of the IP address is added, and the function of judging different addresses in the same network segment is realized. Meanwhile, based on the protocol stack communication function of the single network port, a network port registration function is added, so that the same-network-segment communication of the multi-channel Ethernet port is realized.
And step five, data transmission based on the lightweight Ethernet protocol stack.
And compiling a receiving and sending function of TCP/IP protocol data. Firstly, a protocol stack starts to receive a data request sent by a fixed IP address of an appointed port, after request information is determined, an ARM controller directly takes out Cortex HDR protocol format data from a corresponding cache space by means of a DDRC hard core module, the Cortex HDR protocol format data is output in a TCP/IP protocol data packet format by a sending function, and the data is sent to a client side of a corresponding address through a multi-channel gigabit Ethernet interface, so that the functions of multi-channel high-speed parallel interface data information acquisition and interface conversion are realized.
In FIG. 1: inputting the data stream into a module cache circuit, and secondly: module buffer circuit to MAC controller data flow, c: MAC controller to ethernet interface data flow.
It should be noted that the detailed description is only for explaining and explaining the technical solution of the present invention, and the scope of protection of the claims is not limited thereby. It is intended that all such modifications and variations be included within the scope of the invention as defined in the following claims and the description.
Claims (5)
1. The multi-channel high-speed data interface conversion module of the customized data transmission protocol is characterized in that the module realizes multi-channel high-speed data transmission and comprises the following steps:
the method comprises the following steps: designing a multi-channel parallel receiving logic unit by using programmable logic resources in ZYNQ UltraScale + MPSoC, and storing received multi-channel data into an on-chip random access memory;
step two: designing a transmission controller by using programmable logic resources, judging whether the data meets transmission conditions by using the transmission controller, and controlling a data transmission unit to carry the received original data if the data meets the transmission conditions;
step three: writing the carried data into a fixed address area of an external cache through a data transmission unit, and completing splicing and packaging of data packets in the cache according to a Cortex HDR protocol format;
step four: transplanting a lightweight Ethernet protocol stack to an ARM processor in ZYNQ UltraScale + MPSoC, and changing a protocol stack program to realize multi-port communication in the same network segment;
step five: compiling a receiving and sending function of TCP/IP protocol data, receiving client data request information, directly reading from a cache address and sending data;
the fourth step comprises the following specific steps: firstly, a lightweight Ethernet protocol stack is transplanted to an ARM processor in a ZYNQ UltraScale + platform, then protocol stack parameters are set, and an internet access registration function and an IP matching function in the protocol stack are modified.
2. The multi-channel high-speed data interface conversion module of the customized data transmission protocol according to claim 1, wherein the specific steps of the first step are: firstly, an external interface hardware circuit is designed to convert LVDS differential signals into single-ended data signals meeting the input signal requirements of a processor, and the interface circuit is designed to be completely isolated from the interior of a switching module; and then, matching the time sequence relation of the input signals according to a customized interface protocol time sequence diagram, reading the input signals by using a high-speed clock sampling mode, storing the obtained binary signals into an on-chip random access memory, and counting the read data frames.
3. The multi-channel high-speed data interface conversion module of the customized data transmission protocol according to claim 2, wherein the specific steps of the second step are: firstly, reading a frame count value in the first step, then judging whether the capacity of the on-chip memory reaches a half-full state by using a transmission controller according to the preset capacity of the on-chip memory, if the capacity of the on-chip memory reaches the half-full state, determining that a one-time data transmission condition is met, at the moment, sending a configuration and control instruction to a data transmission unit in the programmable logic resource by the transmission controller through a command control bus, and starting one-time transmission, wherein the transmission data volume is half of the total capacity of the on-chip memory.
4. The multi-channel high-speed data interface conversion module of the customized data transmission protocol according to claim 3, wherein the specific steps of the third step are: the method comprises the steps of firstly, directly writing data in an on-chip memory into an external cache through a data transmission unit, dividing special cache regions with different sizes according to the total amount of channel data to carry out circular covering type storage, and simultaneously, respectively writing a protocol frame head and a frame tail which are calculated according to a format specified by a Cortex HDR protocol and channel data frame attributes into an address region used for storing a data frame in the cache regions.
5. The multi-channel high-speed data interface conversion module of the customized data transmission protocol according to claim 1, wherein the concrete steps of the fifth step are: firstly, writing a receiving and sending function of TCP/IP protocol data, then receiving data sent by a fixed IP address of a designated port, directly reading the content of a cache region in the third step by the sending function after receiving a data sending request, and sending the cache data to client software by a TCP/IP protocol.
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| CN111313997B (en) * | 2020-02-11 | 2021-10-19 | 哈尔滨工业大学 | Remote sensing satellite multi-priority non-equilibrium rate load data dynamic multiplexer simulation system |
| CN111460015B (en) * | 2020-03-10 | 2023-04-11 | 哈尔滨工业大学 | Customized multi-channel real-time accurate satellite data loading device |
| CN112835829B (en) * | 2021-02-10 | 2022-10-28 | 西南电子技术研究所（中国电子科技集团公司第十研究所） | Method for multi-channel DMA transmission measurement and control signal |
| CN114070386B (en) * | 2022-01-17 | 2022-04-26 | 成都国星宇航科技有限公司 | Satellite-borne Ethernet communication system |
| CN114896183B (en) * | 2022-05-25 | 2023-08-08 | 安徽隼波科技有限公司 | ZYNQ-based serial port data transmission method |
| CN115174701A (en) * | 2022-06-30 | 2022-10-11 | 江苏科瑞恩自动化科技有限公司 | Data transmission method and device, computer equipment and storage medium |
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