CN115622896A

CN115622896A - AXI4 high-speed bus and multi-queue simulation verification method and simulation verification device

Info

Publication number: CN115622896A
Application number: CN202110789997.3A
Authority: CN
Inventors: 宋曼谷; 王可; 沙猛; 郭志川
Original assignee: Institute of Acoustics CAS
Current assignee: Zhengzhou Xinrand Network Technology Co ltd
Priority date: 2021-07-13
Filing date: 2021-07-13
Publication date: 2023-01-17

Abstract

The invention belongs to the technical field of communication, in particular to an AXI4 high-speed bus and multi-queue simulation verification method, which utilizes python language to construct an AXI4 bus protocol simulation logic and a multi-queue simulation logic; the method comprises the following steps: obtaining data packets supporting different formats according to an AXI4 bus protocol and an Ethernet message structure; wherein, the data packet is added with AXI4 bus protocol control signals which are synchronously transmitted in parallel; calling a python MyHDL extension packet, interacting the obtained data packet supporting different formats with a multi-queue signal to be tested through a MyHDL signal transmission interface, and observing and comparing whether the output result is the same as the expected result.

Description

AXI4 high-speed bus and multi-queue simulation verification method and simulation verification device

Technical Field

The invention belongs to the technical field of computer network communication, and particularly relates to an AXI4 high-speed bus and multi-queue simulation verification method and a simulation verification device.

Background

With the rapid development of computer network communication technology, various network application scenarios are in progress, and with the increasing network traffic of data centers, the network application scenarios present challenges to the high-performance processing of network data packets. At a server side, a traditional data packet processing mode adopting software is difficult to realize the hundred percent line speed in high-speed data packet processing, and particularly for repeated calculation operation, excessive system resources are occupied, and the processing performance of a CPU is limited to a certain extent. Compared with a software processing method, the FPGA has the characteristics of programmability, parallelism, instantaneity and the like, so that the FPGA becomes one of mainstream platforms for high-speed data packet processing. By adopting the heterogeneous mode of FPGA and CPU, part of high-speed computing operation is unloaded to FPGA hardware for processing, and the method gradually becomes a research hotspot in the industry.

At present, hardware description language is mainly adopted in the industry as the development language of the FPGA, and the design complexity based on the FPGA is higher and higher due to simple language specification. The development difficulty is high, the development cycle is long, the updating iteration speed and the marketization process of the FPGA engineering are greatly influenced, and particularly in a logic verification link, simulation test and performance verification work developed based on Verilog or VHDL occupies at least 50% of the time of the overall design. In order to reduce the difficulty of FPGA development, shorten the engineering development time and improve the system verification efficiency, the key for solving the problem is provided.

The design of simulation modules using higher level programming languages instead of hardware description languages is certainly a better choice. Recently, decaluweJ proposed a Python extension package called MyHDL that provides powerful software and hardware description capabilities for the Python language. The MyHDL extension package provides an interface for a hardware language and a python language and supports the cooperative work of hardware engineering design and software simulation.

Through investigation and research, in the development of a high-speed FPGA network side of 40G or more, in order to support high-performance processing of data packets, an AXI4-stream protocol with high bandwidth and low delay is mostly adopted as a data transfer protocol between acceleration units, and the high-performance address mapping protocol AXI4 is mainly used for interaction with an external storage device. The simulation design provides effective and reasonable input signals for the functional module to be tested according to the design requirements of the module, so that the management of data stream generation, read-write dual-channel bus protocol interface signals of various specifications and multi-queue descriptor signals in data parallel transmission is a main consideration factor of the simulation design. Therefore, the existing simulation verification method has the problems of low development efficiency and high development difficulty, and the comprehensiveness of simulation design is difficult to ensure.

Disclosure of Invention

Aiming at the requirement of high-performance processing of data packets in high-speed network communication, the method supports FPGA engineering simulation verification of common Ethernet communication protocol and data packet processing operation in a software and hardware cooperative working mode, provides a perfect simulation verification flow and a modularized design idea, supports more flexible and efficient simulation file design, saves development and verification time, provides configurable module parameters for upper-layer users, and facilitates the users to carry out multi-specification verification according to the requirement.

The invention provides an AXI4 high-speed bus and multi-queue simulation verification method, which utilizes python language to construct AXI4 bus protocol simulation logic and multi-queue simulation logic; the method comprises the following steps:

obtaining data packets supporting different formats according to an AXI4 bus protocol and an Ethernet message structure; the method comprises the following steps that an AXI4 bus protocol control signal which is synchronously transmitted in parallel is added to a data packet;

calling a python MyHDL extension packet, interacting the obtained data packet supporting different formats with a multi-queue signal to be tested through a MyHDL signal transmission interface, and observing and comparing whether the output result is the same as the expected result.

As an improvement of the above technical solution, the data packet supporting different formats is obtained according to the AXI4 bus protocol and the ethernet message structure; the specific process comprises the following steps:

constructing a data packet frame structure class and a signal generating function according to an AXI4 bus protocol and an Ethernet message structure;

encapsulating frame structure classes layer by layer, generating data packets with different formats, calling a signal generation function, generating continuous data stream, and parallelly transmitting AXI4 bus data stream control signals;

the two are combined with AXI4 bus protocol or multi-queue in independent or random combination mode respectively to obtain data packets supporting different formats.

As an improvement of the above technical solution, the method further includes:

constructing a frame structure class according to an AXI4 bus protocol and an Ethernet message structure; according to the frame structure class, based on python, calling a signal generation function to construct a test signal frame structure, and encapsulating layer by layer from a high layer to a low layer in a class inheritance manner to obtain an encapsulated test signal frame structure;

calling a signal generation function to generate a data packet to be detected and a corresponding AXI4 bus control signal, and combining the data packet to be detected and the corresponding AXI4 bus control signal to obtain a continuous data packet to be detected;

and observing the comparison result of the layer address, the frame start mark, the frame end symbol and the effective field of the data packet supporting different formats and the continuous data packet to be detected, and further observing whether the comparison result is the same as the expected result.

The invention also provides an AXI4 high-speed bus and multi-queue simulation verification system, which comprises:

the software packet sending test module is used for obtaining data packets supporting different formats according to an AXI4 bus protocol and an Ethernet message structure and sending the data packets capable of supporting different formats; wherein, the data packet is added with AXI4 bus protocol control signals which are synchronously transmitted in parallel; and

and the multi-queue simulation module is used for calling the python MyHDL extension packet, interacting the obtained data packet supporting different formats with the multi-queue signal to be tested through the MyHDL signal transmission interface, and observing and comparing whether the output result is the same as the expected result.

As an improvement of the above technical solution, the specific process of the software package sending test module is as follows:

As an improvement of the above technical solution, the system further includes:

the AXI4 bus protocol simulation module is used for constructing a frame structure class according to an AXI4 bus protocol and an Ethernet message structure; according to the frame structure class, based on python, calling a signal generation function to construct a test signal frame structure, and encapsulating layer by layer from a high layer to a low layer in a class inheritance manner to obtain an encapsulated test signal frame structure;

calling a signal generating function to generate a data packet to be tested and a corresponding AXI4 bus control signal, and combining the data packet to be tested and the corresponding AXI4 bus control signal to obtain a continuous data packet to be tested;

The invention also provides a computer device comprising a memory, a processor and a computer program stored on the memory and executable on the processor, the processor implementing the method when executing the computer program.

The invention also provides a computer-readable storage medium having stored thereon a computer program which, when executed by a processor, causes the processor to carry out the method.

Compared with the prior art, the invention has the beneficial effects that:

1. based on the task calling of the python extension packet MyHDL, the method has good visibility and adjustability, and developers and testers can well understand the test logic;

2. the method comprises the steps of performing modular design on a verification platform of the high-speed network communication system, simulating common engineering units such as package generation, queue management, bus protocol interfaces, DMA (direct memory access) data transmission and the like, and flexibly combining various simulation modules in modes such as a modifier, function calling, class inheritance and the like to enhance the reusability of the simulation system;

3. the MyHDL signal transmission interface is provided as a main parameter interface, so that a user can modify the MyHDL signal transmission interface conveniently on a software side, multi-specification testing can be performed according to requirements, and the test comprehensiveness is improved;

4. the method of the invention provides an AXI4 high-speed bus and multi-queue simulation verification method aiming at bus protocol access and multi-queue management developed by an FPGA network side, and improves the flexibility of simulation case design, thereby reducing the simulation design difficulty, shortening the development period and ensuring the comprehensiveness of the simulation verification;

5. the method utilizes python language and MyHDL library thereof to design modularized simulation units aiming at data flow construction, bus protocol interaction and queue management logic. In the design of the actual simulation use case, all simulation units are flexibly combined in modes of class inheritance, function call and the like;

6. the method supports complex simulation logic development, supports wider function verification, reduces the development complexity of the test case and improves the development efficiency.

Drawings

FIG. 1 is a flow chart of an AXI4 high speed bus and multi-queue emulation verification method of the present invention;

fig. 2 is a structural diagram of an AXI4 high-speed bus and multi-queue simulation verification method according to the present invention, which is directed to the function test of an FPGA;

FIG. 3 is a diagram of a data frame encapsulation structure (which is a diagram of FIG. 4, where a packet structure is first generated and a data stream is being generated);

FIG. 4 is a diagram of a data flow generation architecture;

FIG. 5 is a logic diagram internal to an AXI4 bus signal generation function write operation;

FIG. 6 is a diagram of a multiple queue management simulation design.

Detailed Description

The invention will now be further described with reference to the accompanying drawings.

The invention provides an AXI4 high-speed bus and multi-queue simulation verification method, which utilizes the object-oriented structural characteristics of python language to construct AXI4 high-speed bus protocol simulation and multi-queue management simulation logic, thereby realizing the rapid simulation verification of an FPGA network accelerator card functional module.

The method has the advantages that a test module for network high-performance processing is designed by utilizing a python language and a corresponding MyHDL library, generated continuous data streams can be used as input data packets required by testing independently or spliced with an AXI4 high-speed bus protocol or multiple queues, different formats are supported, the input data packets are used as test modules, high-performance simulation verification of the multiple queues is supported, and FPGA network development verification efficiency is effectively improved.

obtaining data packets supporting different formats according to an AXI4 bus protocol and an Ethernet message structure; wherein, the data packet is added with AXI4 bus protocol control signals which are synchronously transmitted in parallel;

specifically, according to an AXI4 bus protocol and an Ethernet message structure, a data packet frame structure class and a signal generation function are constructed;

the two methods are respectively independent or combined randomly, and are combined randomly with an AXI4 bus protocol or a multi-queue to obtain data packets supporting different formats. Wherein, the flow and size of the data packet are controlled by a parameter interface;

The method further comprises the following steps: constructing a frame structure class according to an AXI4 bus protocol and an Ethernet message structure; according to the frame structure class, based on python, calling a signal generation function to construct a test signal frame structure, and encapsulating layer by layer from a high layer to a low layer in a class inheritance manner to obtain an encapsulated test signal frame structure;

the software packet sending test module is used for obtaining data packets supporting different formats according to the AXI4 bus protocol and the Ethernet message structure and sending the data packets capable of supporting different formats; wherein, the data packet is added with AXI4 bus protocol control signals which are synchronously transmitted in parallel;

encapsulating frame structure classes layer by layer, generating data packets with different formats, calling a signal generation function, generating continuous data streams, and generating AXI4 bus data stream control signals transmitted in parallel;

the two are combined with AXI4 bus protocol or multi-queue in independent or random combination mode respectively to obtain data packets supporting different formats. And

Wherein the system further comprises: the AXI4 bus protocol simulation module is used for constructing a frame structure class according to an AXI4 bus protocol and an Ethernet message structure; according to the frame structure class, based on python, calling a signal generation function to construct a test signal frame structure, and encapsulating layer by layer from a high layer to a low layer in a class inheritance manner to obtain an encapsulated test signal frame structure;

and observing the comparison result of the layer address, the frame start mark, the frame end mark and the effective field of the obtained data packet supporting different formats and the continuous data packet to be detected, and further observing whether the comparison result is the same as an expected result.

The invention also provides a computer device comprising a memory, a processor and a computer program stored on the memory and executable on the processor, the processor implementing any of the methods when executing the computer program.

The AXI4 is used as a main interface for data transmission of an acceleration unit and an external storage module arranged in the FPGA, and a stream mode transmission protocol AXI4-stream is used for data interaction between functional modules arranged in the FPGA, so that an AXI4 high-speed bus protocol signal is generated according to handshake logic, and a host side or slave side bidirectional interface signal in a read-write double channel is selected and generated through a parameter configuration interface.

The test case realizes multi-queue simulation through the descriptor queue, the completion queue, the event management queue and corresponding configuration.

However, in the conventional simulation logic development adopting Verilog or VHDL, because the structural characteristics of hardware language often only can individually simulate each function module provided in FPGA, even if repeated logic implementation is not possible to be easily called in a plurality of simulation files, development progress is affected, and due to simple language design rules, it is difficult to support complex simulation design of each function module provided in FPGA, and it is difficult to ensure the comprehensiveness of simulation design. The simulation verification system based on software design utilizes powerful functions and class library resources of python language, reduces the development difficulty of a simulation module, and invokes to _ MyHDL and from _ MyHDL through the task of a python extension packet MyHDL to construct a data transmission channel for hardware engineering and software simulation, thereby realizing the realization of software and hardware collaborative simulation based on python.

The simulation verification method is a combined simulation verification method of Verilog and python aiming at data packet processing by simulating the language characteristics of python and Verilog on the basis of the conventional hardware simulation verification process. The method comprises the following specific processes:

firstly, writing an input/output interface of a module according to a requirement column;

secondly, module division is carried out according to the function of a design unit, and a combinational logic module which is high in algorithm complexity and insensitive to time sequence is designed by python language;

then, the function ToVerilog () of the MyHDL extension packet is converted into a corresponding hardware language to realize, the converted logic unit is checked and debugged according to the design thought of the hardware description language,

then, adding a hardware engineering module designed by Verilog; in order to simplify the development period, in the simulation verification part, a hardware simulation verification platform is built by adopting a python language, an input interface signal is assigned, and a synchronous relation is set according to engineering design requirements;

and finally, performing simulation verification according to the software and hardware collaborative simulation flow.

And when the simulation test result is in error or does not accord with the system design requirement, readjusting the engineering logic or the simulation code according to the problem.

In order to facilitate the calling of hardware integration development environments such as vivado and ISE, the simulation test file based on python can be converted into Verilog code after the simulation is passed.

As shown in fig. 2, software and hardware engineering code programming is divided according to system design, and testing for the FPGA functional unit mainly comprises three parts: hardware engineering module (module.v), software simulation file (test _ module.py), and top test file (testbench.v) connected with software and hardware interfaces. The cooperation relationship of the three is shown in fig. 2.

The hardware engineering module mainly has two generation modes: one is engineering code written directly in Verilog language; the other is written by python language according to design logic and then converted into Verilog code through the toverilog () function of MyHDL.

Because the difference between the writing specifications of the python language and the hardware description languages such as Verilog is large, logic errors may exist in direct conversion, and in order to ensure the accuracy and flexible design of the design, the hardware engineering module is mainly designed by the hardware description language. The simulation design mainly functions to generate matched interface signals, and whether internal logic is reasonable or not does not need to be concerned, so that the development efficiency of the simulation design can be improved by adopting the python design.

The top layer test file is mainly used for interface signal transmission of software and hardware communication, and comprises the following components: the system comprises a from _ myhdl module, a to _ myhdl module and a hardware engineering module;

the from _ myhdl module is used for transmitting an input signal designed by python software, the simulation design function is to simulate the change of the input signal, and the continuously changed input signal generated by the software can be sent to an input interface of the hardware unit through the from _ myhdl module;

correspondingly, the to _ myhdl module is used for receiving an output signal output by the hardware unit;

similar to traditional hardware simulation, the invocation of the hardware engineering module is also required in the simulation file.

Finally, introducing Verilog system task $ dumpfile () and $ dumpvars () to generate a simulation file, wherein the $ dumpfile () is used for creating an executable simulation record file according to the current test, and allowing a gtkwave instruction to execute observation simulation waveforms, the type files supported by the gtkwave comprise vcd, lxt2 and the like, the lxt2 is a compression format, and the occupied space is small, so the method adopts the lxt2 format;

$ dumpvars () records the input-output interface signals required to hold the simulation waveform data in the file specified by $ dumpfile ().

The core part of the invention is a simulation system design based on python. In the traditional simulation design adopting the hardware description language, because the hardware language structure facing the bottom layer design is simple, and the constructed logic function is inconvenient to flexibly call in a plurality of simulation units, each function unit in the FPGA engineering is often required to be designed and simulated independently, so that the redundancy of the simulation verification work is large, and the development of the complicated simulation logic period is long. In contrast, the invention establishes a universal simulation verification system according to the requirement of high-performance processing of the data packet in high-speed network communication, modularly designs the simulation file by using the class structure and the function characteristic of the python language, integrates by using a modifier, function call, class inheritance and other modes, generates more flexible and complex simulation logic, and supports the realization of software simulation in hardware engineering by using the function and the data type aiming at hardware design provided by the MyHDL extension packet. Through research and discovery, the network communication accelerator card developed by the current industry based on the FPGA is mainly responsible for constructing a main data transmission path from an optical port to PCIe (peripheral component interface express) and upper computer interaction, the specific design comprises the work of analyzing, shunting, filtering, matching and the like of a data packet, and the performance of each functional unit in the FPGA engineering is better verified.

First is the design of data stream generation. The invention designs a software package sending test module for testing a hardware functional module based on python language, adopts the concept that an object is python, and the structural characteristics of the object, calls a signal generating function, and constructs two-layer and three-layer data packages. And carrying out layered design on the data packet, and then encapsulating the data packet layer by layer in a class inheritance mode.

Specifically, as shown in fig. 3, three class files and a data stream generation file are designed for the formats of the xgmii, ETH and IP layer packets (universal standard format), and the three data packets are sequentially encapsulated layer by layer from the upper layer to the lower layer in a class inheritance manner.

As shown in fig. 3, for the xgmii data stream signal with specific IP identification and ETH identification to be tested, specific flag information may be input according to the provided parameter interface, the protocol layer may be encapsulated layer by layer in a class inheritance manner, and the test data signal may be produced

Fig. 4 shows the frame structure class and frame generation function composition of the class library file and the data stream generation process. The frame structure class provides a configuration parameter interface of an Ethernet frame format and an optional user-defined field setting interface; the signal generating function calls and outputs the configured frame field and the control signal synchronously output, the xgmii control signal is correspondingly generated in the xgmii data generation, and the data packet of the configured mac layer address and signals such as sop (frame start mark), eop (frame end mark), valid (valid field) and the like are synchronously output at the mac layer. And finally, generating continuous data packets by the data stream generating function (the signal function covers all signals, and the data stream generating function refers to data stream signals in particular) and sending the continuous data packets to the input signal interface of the hardware module to be tested.

As shown in fig. 4, a user calls a signal generating function to generate a specific data stream and a corresponding control signal according to an ethernet frame format required by the design of the ethernet frame configuration interface, generates a data packet to be continuously output by the data stream generating function and sends the data packet to the input signal interface of the hardware module to be tested, and the hardware module to be tested reads the signal to complete data interaction with the simulation unit

If only the input of the xgmii signal is verified, class (xgmii) needs to be introduced first, a preamble is set according to the provided configuration interface, or private fields such as a timestamp are added, then the corresponding generation function xgmii _ create is selected and called in the data stream generation function through the generation frame type, and the MAC layer interface data signal and the corresponding control signal are generated.

If the multi-module is subjected to the joint simulation test, the data packet is required to contain an effective xgmii field, a mac layer address, a vlan field and ip layer header information, the ip frame structure class, the ethFrame class and the xgmii class need to be set layer by layer respectively, the ip layer field information and the mac layer field information are inherited in a frame generated by xgmii in a class inheritance mode, and then a generating function is called to generate an xgmii data stream with two-layer and three-layer protocol characteristics.

In order to support the test comprehensiveness and effectively ensure the correct logic of a hardware module, a plurality of control parameter interfaces are provided in a data stream generating function, the flow rate is controlled by adjusting a frame interval field through a flow control interface, a packet length option configuration payload field is provided, the provided packet length field can also be used as a reference, a payload field with a fixed length and an increasing, decreasing and decreasing rate is configured through mode selection, and the specific payload information adopts a regular design, so that a user can conveniently detect packet loss and errors.

In the development of an intelligent network card based on FPGA high-performance data packet processing, mainly used bus protocols include AXI4 (used as a data internal transmission bus), AXI4-lite (a lightweight address mapping single transmission interface, which is commonly used for a read-write design of a register) AXIs (streaming mode data transmission bus). These protocols are complex in structure and frequently referred to, and a hardware description language-based functional unit-specific simulation design requires a bus protocol generation signal to be designed separately for each module, a matching relationship of address data to be redesigned each time, and validity of handshake signals to ensure synchronous input of corresponding signals, which results in high complexity of the simulation design. The AXI4 protocol can be divided into a read data channel and a write data channel according to the data flow direction, and can be divided into a host side and a slave side according to an operation object, wherein the host side is an interface data transmission module of an FPGA board card connected with a DDR, and the slave side is a space representing a DDR ram. The invention makes modular design for AXI4 series bus protocol, generates read-write operation signals of master and slave sides through determined handshake, and flexibly and efficiently generates bus protocol signals in a simulation file design through function calling mode.

The AXI4 bus protocol simulation module mainly comprises an AXIMmaster type and an AXIRam type, wherein the AXIMmaster type is responsible for supporting generation of host side data receiving and transmitting channel signals. The bus signal generating device mainly comprises a read-write channel initialization function, a signal waiting function, a signal extracting function and a bus signal generating function. The call of the initialization function is to allocate a signal initial value for the read (write) operation; the signal waiting function is called when no data is transmitted, and each signal interface is set to be zero; the signal extraction function is used for extracting data in the signal list and using the data as signal verification; the generating function generates corresponding read-write operation signals according to the signal initial values and the selected read-write operation modes, chip selection enabling logic, write response logic, write address interface logic, write data interface logic and write interface response logic are instantiated in the generating function, and logic units related to read operation and response are arranged correspondingly. Taking write data transmission as an example, first, a write channel initialization function init _ write (address, data, burst =0b01, size = none, lock =0b0, cache =0b0011, prot =0b010, qos =0b0000, region =0b0000, and user =0b0000 is called in an interface order, and other signals may be initialized by default values, or according to AXI4 bus protocol specification, burst mode setting of maximum 256 cycles is supported, selection of fixed burst, incremental burst, or loopback burst is supported, and then a bus signal generation function critical _ logic () is called with the values as references to generate a continuous bus write signal data stream, the generation function includes host-side read-write signal generation logic, and read or write logic signals are generated by configuring enable port selection.

As shown in fig. 5, when the read/write operation is determined according to the chip select enable signal input by function call, taking the write operation as an example, a signal of an initialization parameter is extracted through write _ logic, an initial value of a handshake signal is extracted, in order to ensure efficient transmission of data, alignment processing is performed according to the provided address and data, an address bus and data bus signal list is generated, the burst size and depth are extracted, and a burst transmission period is determined; the write _ resp sets a one-time burst completion list according to the burst completion condition; generating a continuous address signal and data signal list according to the burst length, and generating a corresponding continuous response signal stream according to the burst completion condition; and finally, outputting the sequential data streams in the list in a parallelization manner according to the bus protocol sequence through generator packaging so as to match with the FPGA parallelization signal interface. The signal wait function construct idle state may be invoked when there is no data transfer requirement.

The corresponding AXIRam is used on the DDR side and is responsible for generating DDR data writing and extracting signals, data and addresses in the DDR are updated in the operation form of a ring buffer by calling a python mmap library function, and corresponding handshake signals are generated by designing an AXIRam signal generation function create _ port. And finally, generating the bus handshake signals by construction in the design of the corresponding test module, and performing synchronous processing on the generated bus handshake signals according to the edge trigger state of the clock signals.

As shown in fig. 6, compared with a pipeline mechanism of a CPU, an FPGA has a parallel transmission feature, and in order to meet high throughput, the current high-performance FPGA accelerator card may choose to offload load balancing work in hardware, which requires multi-queue management in the FPGA. Aiming at the function, the invention designs a queue management simulation module which is used for verifying the high-performance queue scheduling logic. The method mainly comprises three types of queue management, completion queue management and event queue management, and is used for updating the transmission state of data in a queue. Taking a queue management module as an example, a queue management list is designed in hardware engineering, and each queue entry consists of parameters such as a queue corner mark, a queue address, an operation table corner mark, a descriptor read-write pointer address, an enabling port, an active state and the like. For packet receiving operation, a transmission queue is distributed to a data packet through a hash load balancing algorithm, a queue management module needs to check a queue enabling state and a pointer interval to determine whether the data packet can be transmitted in the queue, if the transmission is allowed, a corresponding transmission channel is distributed to the data packet and a head pointer address is updated, and a driving side updates a corresponding tail pointer state according to the receiving condition of the data packet and dequeues the data packet. According to the characteristics, a corresponding queue management simulation module is set for simulating the receiving state of the drive data packet, a maximum 8192-bit queue operation list is designed in the module, when the data packet is received, corresponding receiving queue information is added to the starting position of the operation list, queue information is managed according to the FIFO first-in first-out structure, queue updating at the outlet position of the operation list is sequentially processed, a queue tail pointer is updated, and processed queue entries are released, so that efficient management of the queue state is realized.

The specific module design has two technical points, namely, the parallelization processing of the mapping FPGA is realized, and @ always _ comb modifiers in MyHDL are introduced to respectively correspond to the realization of sequential logic and combinational logic. And secondly, the transmission of continuous data flow is carried out, if the generated data is recorded in a list, and the whole list is returned after the simulation is finished, a large amount of memory resources are consumed, and a data list with a large volume is transmitted at one time, so that segment errors are easily generated. The design of the generator can calculate the subsequent generated data while circulating, and continuously return data signals, thereby ensuring the stability of signal transmission.

Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and are not limited. Although the present invention has been described in detail with reference to the embodiments, it will be understood by those skilled in the art that various changes may be made and equivalents may be substituted without departing from the spirit and scope of the invention as defined in the appended claims.

Claims

1. An AXI4 high-speed bus and multi-queue simulation verification method, an AXI4 bus protocol simulation logic and a multi-queue simulation logic are constructed by utilizing python language; the method comprises the following steps:

2. The AXI4 high-speed bus and multi-queue emulation verification method of claim 1, wherein the data packets supporting different formats are obtained according to an AXI4 bus protocol and an Ethernet message structure; the specific process comprises the following steps:

encapsulating frame structure classes layer by layer, generating data packets with different formats, calling a signal generation function, generating continuous data streams, and generating AXI4 bus data stream control signals transmitted synchronously in parallel;

3. The AXI4 high speed bus and multi-queue emulation verification method of claim 1, further comprising:

and observing the comparison result of the obtained address information, the frame start mark, the frame end mark, the characteristic field of payload and the flow interval of the continuous data stream supporting the data packets with different formats, and further observing whether the comparison result is the same as an expected result.

4. An AXI4 high-speed bus and multi-queue emulation verification system, comprising:

5. The AXI4 high speed bus and multi-queue emulation verification system of claim 4, wherein the software packet issuing test module comprises:

the two methods are respectively independent or combined randomly, and are combined randomly with an AXI4 bus protocol or a multi-queue to obtain data packets supporting different formats.

6. The AXI4 high speed bus and multi-queue emulation verification system of claim 4, further comprising:

calling a signal generating function to generate a data packet to be tested and a corresponding AXI4 bus control signal, and combining the data packet to be tested and the corresponding AXI4 bus control signal to obtain a continuous test data stream;

7. A computer arrangement comprising a memory, a processor and a computer program stored on the memory and executable on the processor, characterized in that the processor implements the method of any of claims 1-3 when executing the computer program.

8. A computer-readable storage medium, characterized in that the computer-readable storage medium stores a computer program which, when executed by a processor, causes the processor to carry out the method of any one of claims 1-3.