CN112702313A

CN112702313A - High-speed UDP data transmission system and method

Info

Publication number: CN112702313A
Application number: CN202011386522.1A
Authority: CN
Inventors: 蒲鹤升; 彭祥吉
Original assignee: Shenzhen Ziguang Tongchuang Electronics Co ltd
Current assignee: Shenzhen Ziguang Tongchuang Electronics Co ltd
Priority date: 2020-12-01
Filing date: 2020-12-01
Publication date: 2021-04-23
Anticipated expiration: 2040-12-01
Also published as: CN112702313B

Abstract

The invention provides a high-speed UDP data transmission system and a method, wherein the high-speed UDP data transmission system comprises a processor, a sending accelerator in communication connection with the processor, a sending data selector in communication connection with the sending accelerator and the processor, a three-speed MAC in communication connection with the sending data selector, and a physical layer (PHY) in communication connection with the three-speed MAC. Through the mode, the transmission accelerator is mounted in the processor, so that a large amount of real-time data can be quickly and efficiently transmitted in an FPGA hardware logic acceleration mode under the cooperation of the LwIP protocol stack, the UDP transmission efficiency and the data bandwidth can be greatly improved, and the accelerated transmission requirement in practical application can be met.

Description

High-speed UDP data transmission system and method

Technical Field

The invention relates to the technical field of high-speed network data transmission, in particular to a high-speed UDP data sending system and a high-speed UDP data sending method.

Background

In an application scenario where a large amount of real-time data is transmitted by using an ethernet technology and accidental transmission errors are tolerated, considering communication efficiency and data bandwidth requirements, a simple and fast end-to-end communication Protocol, UDP (User Datagram Protocol), is generally selected.

If a complete multi-layer UDP communication process is realized only by means of FPGA hardware logic, although UDP has high sending efficiency and large data bandwidth, a large amount of logic resources are consumed and the system complexity is high; if the UDP branch in the LwIP protocol stack is realized only by using an ARM Cortex M1 processor embedded SoC System (abbreviated as System on Chip) equipped with a CACHE Memory and an ethernet DMA (Direct Memory Access) device, although resources are saved and System complexity is reduced, due to the host frequency and processing capability of the Cortex M1 soft core itself, the multiple operating cycles of the CACHE and the limited capacity of the DMA, UDP transmission efficiency is low and data bandwidth is small, and the actual requirements cannot be met.

Therefore, it is desirable to provide a new high speed UDP data transmission system and method to solve the existing drawbacks.

Disclosure of Invention

Based on the above, the invention provides a high-speed UDP data transmission system and method.

The invention provides a high-speed UDP data transmission system, comprising: a processor, a transmit accelerator communicatively coupled to the processor, a transmit data selector communicatively coupled to the transmit accelerator and the processor, a three-speed MAC communicatively coupled to the transmit data selector, a physical layer (PHY) communicatively coupled to the three-speed MAC,

the processor receives and analyzes an ARP data frame of an external network, establishes an ARP cache table, and sends information stored in the ARP cache table to the sending accelerator, wherein the information stored in the ARP cache table comprises an IP address and an MAC address which are matched with each other;

the sending accelerator receives and stores information transmitted by an external source data bus, calculates a UDP checksum and an IP header checksum according to the information transmitted by the processor and the information transmitted by the source data bus, packages an Ethernet data frame and a chip selection signal according to the UDP checksum and the IP header checksum, and sends the encapsulated Ethernet data frame and the chip selection signal to the sending data selector as encapsulation information;

the sending data selector selects the authority attribution of the three-speed MACIP in the processor and the sending accelerator according to the encapsulation information;

and sending the Ethernet data which accords with the sending time sequence of the three-speed MACIP to the physical layer PHY according to the authority attribution result of the three-speed MACIP.

Preferably, the transmission accelerator includes a communication interface, a FIFO buffer module, a UDP checksum calculation module, an IP header checksum calculation module, and an ethernet frame packing and transmitting module.

Preferably, the communication interface is an AHB bus interface.

Preferably, the processor is a soft core processor Cortex M1.

Preferably, the processor is embedded in an SOC system, and the SOC system is configured to analyze UDP in the LwIP protocol stack.

Preferably, the transmission interface between the three-speed MAC and the physical layer PHY is an RGMII interface.

The invention also provides a high-speed UDP data sending method, comprising the following steps:

receiving and analyzing an ARP data frame of an external network, and establishing an ARP cache table;

acquiring information stored in the ARP cache table, wherein the information stored in the ARP cache table comprises an IP address and an MAC address which are matched with each other;

receiving and storing information transmitted by an external source data bus;

calculating a UDP checksum and an IP header checksum according to the information stored in the ARP cache table and the information transmitted by the source data bus, and encapsulating an Ethernet data frame and a chip selection signal according to the UDP checksum and the IP header checksum and using the encapsulated Ethernet data frame and the chip selection signal as encapsulation information;

selecting the authority affiliation of the three-speed MAC IP in the processor and the sending accelerator according to the encapsulation information;

and sending the Ethernet data according with the sending time sequence of the three-speed MAC IP according to the authority attribution result of the three-speed MAC IP.

Preferably, the calculating a UDP checksum and an IP header checksum according to the information stored in the ARP cache table and the information transmitted by the source data bus further includes:

acquiring a state signal in a transmitting accelerator;

and obtaining the chip selection signal according to the state signal.

Preferably, the selecting the right attribution of the three-speed MAC IP in the processor and the transmission accelerator according to the encapsulation information includes: and selecting the authority affiliation of the three-speed MAC IP according to the chip selection signal.

The invention has the beneficial effect of providing a high-speed UDP data transmission system and a method, wherein the high-speed UDP data transmission system comprises a processor, a sending accelerator in communication connection with the processor, a sending data selector in communication connection with the sending accelerator and the processor, a three-speed MAC in communication connection with the sending data selector, and a physical layer PHY in communication connection with the three-speed MAC. Through the mode, the transmission accelerator is mounted in the processor, so that a large amount of real-time data can be quickly and efficiently transmitted in an FPGA hardware logic acceleration mode under the cooperation of the LwIP protocol stack, the UDP transmission efficiency and the data bandwidth can be greatly improved, and the accelerated transmission requirement in practical application can be met.

Drawings

Fig. 1 is a schematic structural diagram of a high-speed UDP data transmission system according to the present invention.

Description of the drawings: a high-speed UDP data transmission system 100; a processor 1; an acceleration transmitter 2; a communication interface 21; FIFO buffer logic 22; a UDP checksum calculation module 23; an IP header checksum calculation block 24; an ethernet frame packing and transmitting module 25; a transmission data selector 3; three-speed MAC 4; the physical layer PHY 5.

Detailed Description

To facilitate an understanding of the invention, the invention will now be described more fully with reference to the accompanying drawings. Preferred embodiments of the present invention are shown in the drawings. This invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.

It will be understood that when an element is referred to as being "secured to" another element, it can be directly on the other element or intervening elements may also be present. When an element is referred to as being "connected" to another element, it can be directly connected to the other element or intervening elements may also be present.

Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. The terminology used in the description of the invention herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention.

Referring to fig. 1, which is a schematic diagram of a high speed UDP data transmission system according to an embodiment of the present invention, as shown in fig. 1, a high speed UDP data transmission system 100 includes a processor 1, a transmission accelerator 2 communicatively connected to the processor 1, a transmission data selector 3 communicatively connected to the transmission accelerator 2 and the processor 1, a three-speed MAC4 communicatively connected to the transmission data selector 3, and a physical layer PHY5 communicatively connected to the three-speed MAC 4. In the embodiment of the present invention, the processor 1 adopts a soft core processor Cortex M1, and the Cortex M1 is embedded in an SoC system (SoC integrated circuit), and is accompanied by various peripheral functions, which can realize complete UDP parsing capability in an LwIP protocol stack, and meanwhile, the high-speed UDP data transmission system 100 of the present invention uses a system clock (HCLK) and a system reset (SYSRESETn) of a Cortex M1 embedded SoC; the sending accelerator 2 is UDP _ HW _ SPEEDUP and performs information interaction with a source data bus and the processor 1; the transmission data selector 3 is TSMAC MUX; the third-speed MAC4 is TSMAC; the physical layer PHY5 is an Ethernet PHY. Optionally, the transmission interface between the three-speed MAC4 and the physical layer PHY5 is an RGMII interface (not shown).

The transmission accelerator 2 includes a communication interface 21, a FIFO buffer module 22, a UDP checksum calculation module 23, an IP header checksum calculation module 24, and an ethernet frame packing and transmitting module 25.

And the communication interface 21 adopts an AHB bus interface to realize information interaction and state control between Cortex M1 and UDP _ HW _ SPEEDUP, including that Cortex M1 configures destination MAC/IP/PORT and source MAC/IP/PORT information required by Ethernet frame through the AHB interface, and realizes master-slave state information interaction at the same time.

The FIFO buffer module 22 implements buffering of source data (i.e. datai [7:0], dbusy, dready; when dready is high, the source data input operation can be performed, and when dbusy is high, it indicates that the input data datai at this time is valid), and it fixes the data of 1460 byte length in the buffer in order to assist the UDP checksum calculation and prevent the loss of valid data.

The UDP checksum calculation module 23 implements checksum calculation of source data (i.e., datai [7:0], dbusy, dready; when dready is high, the source data input operation can be performed, and when dbusy is high, it indicates that the input data datai at this time is valid) and a UDP header by checking a pseudo header + data of a UDP datagram and summing up by using binary bar codes, i.e., after 16-bit data are added, adding a carry and 16-bit data lower until the carry is 0, and finally, negating the 16-bit data.

The IP header checksum calculation block 24 implements the checksum calculation of the IP header by "checking the header of the IP datagram, and using binary inverse summation, i.e., adding 16 bits of data, adding the carry and the lower 16 bits until the carry is 0, and finally negating the 16 bits", where the IP identifier is a counter that increments by 1, and increments by 1 every time the identifier is issued.

The ethernet frame group packing and sending module 25 implements ethernet frame group packing and TSMAC IP sending logic, and substantially sends the complete ethernet frame to the TSMAC IP according to the TX user side interface timing sequence of the TSMAC IP, and finally sends the ethernet frame to an external PHY chip through the RGMII interface. In order to meet the maximized data bandwidth, a buffer is opened in the packet packing logic of the Ethernet frame to store the header of the Ethernet frame in advance, and the header of the Ethernet frame is directly called when needed, so that the frame gap is shortened to the maximum extent.

First, the LwIP protocol stack is implemented using Cortex M1 to support a complete UDP protocol parsing function. When the LwIP protocol stack is successfully operated, the Cortex M1 receives and analyzes the ARP data frame of the external network device, and establishes a matching APR cache table, that is, stores the IP address and the MAC address that are matched with each other.

Then, Cortex M1 realizes the interaction of configuration information and state information with the UDP _ HW _ SPEEDUP module through the AHB bus, and its purpose is to issue the destination and source MAC/IP/PORT (stored in the ARP cache table) information required by UDP _ HW _ SPEEDUP, and at the same time, realize the state interaction between the master and slave devices, and provide reliable basis for the MAC authority allocation.

Then, the source data bus (i.e. datai [7:0], dbusy, dready; when dready is high, the source data input operation can be performed, and when dbusy is high, the input data datai at this time is valid) is accessed into UDP _ HW _ SPEEDUP, and simultaneously, the UDP checksum and the IP header checksum are calculated by combining the configured destination and source MAC/IP/PORT information.

And then, transmitting the encapsulated Ethernet data frame and udp _ cs chip selection signals to a TSMAC MUX (TSMAC multiplexer) by utilizing Ethernet frame group package and transmission logic and FIFO (first in first out) buffer logic, and determining the permission attribution of TSMAC IP (time stamp MAC) after udp _ cs selection.

And finally, sending the Ethernet data frame conforming to the TSMAC IP TX time sequence to an external PHY layer through an RGMII interface, namely finishing all operations.

Since UDP _ HW _ speed is to receive configuration information, it is necessary to plan an AHB register to implement information interaction between the Cortex M1 soft core and the UDP _ HW _ speed module, and the specific register plan is shown in table 1.

TABLE 1 AHB register Programming

When Cortex M1 needs to send its own UDP packet, it needs to send a request to UDP _ HW _ speed, and when UDP _ HW _ speed is idle, it will yield the TSMAC IP right to be used by Cortex M1 until the right is returned to UDP _ HW _ speed after the use.

The data sending accelerator 3 can realize the permission occupation work of Cortex M1 SoC and UDP _ HW _ SPEEDUP module on the TSMAC IP, and sends the permission occupation work to the TSMAC MUX through UDP _ cs chip selection signal, and determines the permission ownership of the TSMAC IP after the selection of UDP _ cs. The UDP _ cs chip select signal is controlled by a state signal internal to UDP _ HW _ SPEEDUP, which is embodied as:

when UDP _ cs is 1 'b 0, Cortex M1 is occupied, the condition "network unconnected (UDP _ STATU [2] ═ 1' b0) is satisfied; cortex M1 unsolicited (UDP _ STATU [1] ═ 1' b 0); cortex M1 requests and UDP _ HW _ SPEEDUP busy (UDP _ STATU [1:0] ═ 2' b10) "

When UDP _ cs ═ 1 'b 1, UDP _ HW _ SPEEDUP is occupied, the condition is "network connection and Cortex M1 does not request (UDP _ STATU [2:1] ═ 2' b 10)"

Based on the high-speed UDP data sending system, the invention also provides a high-speed UDP data sending method, which comprises the following steps:

step S1, receiving and analyzing ARP data frame of external network, and establishing ARP buffer list;

step S2, obtaining the information stored in the ARP cache table, wherein the information stored in the ARP cache table comprises an IP address and an MAC address which are matched with each other;

step S3, receiving and storing the information transmitted by the external source data bus;

step S4, calculating UDP checksum and IP header checksum according to the information stored in the ARP cache table and the information transmitted by the source data bus, and encapsulating Ethernet data frame and chip selection signal according to the UDP checksum and the IP header checksum as encapsulation information;

step S5, selecting the authority affiliation of the three-speed MAC IP in the processor and the transmission accelerator according to the encapsulation information;

and step S6, sending the Ethernet data according with the three-speed MAC IP sending time sequence according to the authority attribution result of the three-speed MAC IP.

Wherein, the chip selection signal in step S4 is to acquire the status signal in the transmission accelerator 2; and obtaining the chip selection signal according to the state signal. And step S5, selecting the authority attribution of the three-speed MAC IP according to the chip selection signal.

Specifically, first, the initialization process: required register planning: destination MAC high four byte register-D _ MAC _ H [31:0], destination MAC low two byte register-D _ MAC _ L [31:16], source MAC high four byte register-S _ MAC _ H [31:0], source MAC low two byte register-S _ MAC _ L [31:16], destination IP number register-D _ IP [31:0], source IP number register-S _ IP [31:0], PORT register-PORT [31:0], STATUs register-UDP _ STATU [2 ];

the Cortex M1 SoC implements an LwIP protocol stack (the LwIP protocol stack implementation process is not described here, and the Cortex M1 SoC can be used as a black box), receives and analyzes an ARP data frame of an external network device, and establishes a matched APR cache table, that is, stores an IP address and an MAC address which are matched with each other;

cortex M1 extracts the corresponding D _ MAC _ H [31:0], D _ MAC _ L [31:16], S _ MAC _ H [31:0], S _ MAC _ L [31:16], D _ IP [31:0], S _ IP [31:0] information and self-defined PORT [31:0] information in the ARP cache table and sequentially sends the information to UDP _ HW _ SPEEDUP;

cortex M1 sends UDP _ STATUs [2] ═ 1 to UDP _ HW _ SPEEDUP, indicating that the network is connected, otherwise, indicating that the network is not connected;

when the network is connected, the initialization phase is completed, otherwise, the network connection state is always waited, namely the UDP _ STATU [2] is waited to be pulled high.

Second, TX transmission flow: required register planning, STATUs register-UDP _ STATU [2:0 ];

when UDP needs to be sent, UDP network connection is guaranteed, so that the FPGA logic needs to read the current value of UDP _ STATU [2 ]; when the UDP _ STATU [2] is 1, connecting the network; when the UDP _ STATU [2] is 0, the network is disconnected;

when the network is normally connected, the TSMAC IP is occupied by UDP _ HW _ SPEEDUP by default, and real-time data can be sent all the time;

when Cortex M1 needs to send its own UDP data frame through TSAMC IP, it needs to send a sending request to UDP _ HW _ SPEEDUP through AHB interface first, that is, it determines whether UDP _ STATU [1] is high;

when the network is normally connected and a sending request occurs to Cortex M1, reading the value of UDP _ STATU [0] through an AHB bus, and when the UDP _ STATU [0] is 1, UDP _ HW _ SPEEDUP is busy and the Cortex M1 is not allowed to send UDP frames; when UDP _ STATUs [0] is 0, UDP _ HW _ SPEEDUP is idle and Cortex M1 is allowed to send UDP frames;

when the Cortex M1 requests to be maintained and the UDP _ HW _ SPEEDUP is idle, the TSAMC IP right is switched to the Cortex M1, the Cortex M1 cancels the request after sending the UDP data frame by using the Lwip protocol stack (when the UDP _ STATU [2] ═ 1' b0), and the TSAMC IP right can be handed back to the UDP _ HW _ SPEEDUP

TSAMC IP permission switching is controlled by the UDP _ HW _ SPEEDUP signal when UDP _ CS is high, otherwise occupied by Cortex M1.

According to the high-speed UDP data sending system 100, the UDP sending hardware accelerator is mounted in the Cortex M1 embedded SoC system, so that a large amount of real-time data can be sent quickly and efficiently in an FPGA hardware logic acceleration mode under the cooperation of the LwIP protocol stack, the UDP sending efficiency and the data bandwidth can be greatly improved, and the requirement of acceleration sending in practical application can be met. Firstly, a UDP TX hardware acceleration scheme is realized at the cost of lower resource consumption, the highest UDP data transmission bandwidth can reach 990Mbps, and the Ethernet communication requirement of mass real-time data transmission is successfully met; secondly, the link with the external network equipment is realized by utilizing the LwIP protocol stack, so that other complicated UDP protocol analysis circuits are not needed, the overall complexity of the system is greatly reduced, and the system is more simplified and is easy to realize; in addition, a reasonable TSMAC IP (three-speed MAC IP) authority management mechanism is established, and the problem of data loss or confusion caused by malignant competition is prevented; finally, the IP of the PANGO FPGA is utilized to realize the modular design of system functions, thereby effectively reducing the transplantation difficulty of different FPGA platforms and having better universality.

The technical features of the above embodiments can be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features in the above embodiments are not described, but should be considered as the scope of the present specification as long as there is no contradiction between the combinations of the technical features.

The above examples only express preferred embodiments of the present invention, and the description thereof is more specific and detailed, but not construed as limiting the scope of the invention. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the inventive concept, which falls within the scope of the present invention. Therefore, the protection scope of the present patent shall be subject to the appended claims.

Claims

1. A high speed UDP data transmission system, comprising: a processor, a transmit accelerator communicatively coupled to the processor, a transmit data selector communicatively coupled to the transmit accelerator and the processor, a three-speed MAC communicatively coupled to the transmit data selector, a physical layer (PHY) communicatively coupled to the three-speed MAC,

the sending data selector selects the authority affiliation of the three-speed MAC IP in the processor and the sending accelerator according to the encapsulation information;

and sending the Ethernet data which accords with the sending time sequence of the three-speed MAC IP to the physical layer PHY according to the authority attribution result of the three-speed MAC IP.

2. The high-speed UDP data transmission system of claim 1 wherein the transmission accelerator includes a communication interface, a FIFO buffer module, a UDP checksum calculation module, an IP header checksum calculation module, and an ethernet frame packing and transmitting module.

3. The high-speed UDP data transmission system of claim 2, wherein the communication interface is an AHB bus interface.

4. The high speed UDP data transmission system of claim 1 wherein the processor is a soft core processor Cortex M1.

5. The high speed UDP data transmission system of claim 4, wherein the processor is embedded in an SOC system configured to parse UDP in the LwIP protocol stack.

6. The high speed UDP data transmission system of claim 1 wherein the transmission interface between the three speed MAC and the physical layer PHY is an RGMII interface.

7. A method for transmitting high-speed UDP data, comprising:

receiving and storing information transmitted by an external source data bus;

8. The method for transmitting high speed UDP data according to claim 7, wherein the calculating of the UDP checksum and the IP header checksum according to the information held in the ARP cache table and the information transmitted by the source data bus further comprises:

acquiring a state signal in a transmitting accelerator;

and obtaining the chip selection signal according to the state signal.

9. The method for transmitting high speed UDP data according to claim 8, wherein the selecting the right attribution of the three-speed MAC IP in the processor and the transmission accelerator according to the encapsulation information comprises: and selecting the authority affiliation of the three-speed MAC IP according to the chip selection signal.