CN220401778U - Multi-interface protocol conversion system and equipment - Google Patents
Multi-interface protocol conversion system and equipment Download PDFInfo
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Abstract
The utility model is applicable to the technical field of protocol conversion, and provides a multi-interface protocol conversion system and equipment, wherein the multi-interface protocol conversion system comprises a first field programmable gate array, a second field programmable gate array, a third field programmable gate array, three DDR particles, ten gigabit network chips, a first connector, a second connector, an SMA connector, a power module, a third connector, a fourth connector, a fifth connector, a sixth connector, a seventh connector, an eighth connector, a first high-speed connector and an optical module. The multi-interface protocol conversion system in the embodiment increases the interface types and has higher cost performance.
Description
Technical Field
The present utility model belongs to the technical field of protocol conversion, and in particular, relates to a multi-interface protocol conversion system and device.
Background
Protocol conversion equipment is also called a protocol converter or an interface converter, and can enable hosts which are positioned on a communication network and adopt different protocols to still cooperate with each other so as to complete various distributed application works; a protocol conversion device is a protocol for adapting standard or device-specific protocols to other apparatuses or tools of a device to achieve interoperability. The protocol is software installed on the router that can convert the data format, data rate and protocol of a network into the network protocol in which the data is being navigated. A variety of protocols are used in different fields of power generation, power transmission and distribution, oil and gas, automation, utilities and remote monitoring applications. The primary protocol conversion messages relate to the conversion of data messages, events, commands and time synchronization.
The standard 2U single machine is an application of protocol conversion equipment, has data processing and protocol conversion functions, but has fewer interface types, cannot meet the interface requirements, and adopts an expensive V7 series Field Programmable Gate Array (FPGA), so that the price of the standard 2U single machine is higher.
Disclosure of Invention
The embodiment of the utility model provides a multi-interface protocol conversion system, which aims to solve the problems of few types and high price of the existing standard 2U single machine interface.
The embodiment of the utility model provides a multi-interface protocol conversion system, which comprises a first field programmable gate array, a second field programmable gate array, a third field programmable gate array, three DDR particles, ten gigabit network chips, a first connector, a second connector, an SMA connector, a power module, a third connector, a fourth connector, a fifth connector, a sixth connector, a seventh connector, an eighth connector, a first high-speed connector and an optical module;
wherein the first field programmable gate array and the second field programmable gate array together provide 2 optical ports;
the DDR particles are respectively connected to the first field programmable gate array, the second field programmable gate array and the third field programmable gate array in a one-to-one correspondence manner;
one of ten gigabit network chips is connected to the first field programmable gate array and used for providing 1-path gigabit Ethernet interface, the other gigabit network chip is connected to the second field programmable gate array and used for providing 1-path gigabit Ethernet interface, and the other eight gigabit network chips are respectively connected to the third field programmable gate array and used for providing 8-path third field programmable gate array;
the first connector is connected to the third field programmable gate array and provides a 2-way CAN interface;
the second connector is respectively connected to the first field programmable gate array, the second field programmable gate array and the third field programmable gate array;
the SMA connectors are respectively connected to the first field programmable gate array, the second field programmable gate array and the third field programmable gate array and are used for providing clock signals;
the power supply module is respectively connected to the first field programmable gate array, the second field programmable gate array and the third field programmable gate array and is used for providing power supply;
the third connector, the fourth connector, the fifth connector, the sixth connector, the seventh connector, and the eighth connector are connected to the third field programmable gate array, respectively; the third connector is used for providing 7 paths of RS422 interfaces respectively, the fourth connector is used for providing 4 paths of LVDS interfaces and 8 paths of RS422 interfaces respectively, the fifth connector is used for providing 4 paths of RS422 interfaces, the sixth connector is used for providing 4 paths of RS422 interfaces, the seventh connector is used for providing 8 paths of LVDS interfaces and 8 paths of RS422 interfaces respectively, and the eighth connector is used for providing 2 paths of LVDS interfaces and 1 path of RS422 interfaces respectively;
the first high-speed connector is respectively connected to the first field programmable gate array and the second field programmable gate array, and provides a 2-way GTX interface through the first field programmable gate array, and provides a 2-way GTX interface through the second field programmable gate array;
the optical module is respectively connected to the first field programmable gate array and the second field programmable gate array, and provides a 2-way GTX interface through the first field programmable gate array, and provides a 2-way GTX interface through the second field programmable gate array;
the first field programmable gate array, the second field programmable gate array and the third field programmable gate array are all XC7K325T-FGG900I.
Still further, the circuit further comprises a fourth field programmable gate array, a fifth field programmable gate array, a sixth field programmable gate array, three other DDR particles, seven other giga net phy chips, a ninth connector, a tenth connector, a second high-speed connector and a third high-speed connector;
the fourth field programmable gate array, the fifth field programmable gate array and the sixth field programmable gate array together provide 6 optical ports;
the other three DDR particles are respectively connected to the fourth field programmable gate array, the fifth field programmable gate array and the sixth field programmable gate array in a one-to-one correspondence manner;
one of the seven other gigabit network chips is connected to the fourth field programmable gate array and is used for providing a 1-way gigabit ethernet interface, the other two gigabit network chips are connected to the fifth field programmable gate array and are used for providing a 2-way gigabit ethernet interface, and the other four gigabit network chips are connected to the sixth field programmable gate array and are used for providing a 4-way gigabit ethernet interface;
the ninth connector is connected to the sixth field programmable gate array and is used for providing a 4-way LVDS interface and a 4-way RS422 interface respectively;
the tenth connector is connected to the fifth field programmable gate array and is respectively used for providing a 2-way LVDS interface and a 2-way RS422 interface;
the second high-speed connector is respectively connected to the fourth field programmable gate array, the fifth field programmable gate array and the sixth field programmable gate array, and provides 8 paths of GTX interfaces through the fourth field programmable gate array, 8 paths of GTX interfaces through the fifth field programmable gate array and 2 paths of GTX interfaces through the sixth field programmable gate array;
the third high-speed connector is connected to the sixth field programmable gate array and is used for providing a 4-way GTX interface;
the model numbers of the fourth field programmable gate array, the fifth field programmable gate array and the sixth field programmable gate array are XC7K325T-FGG900I.
Still further, the gigabit network chip is model 88E1111.
Still further, the first connector is of the type J30JA-9ZKW-J.
Further, the second connector and the third connector are each of the type J30JA-100ZKW-J.
Still further, the fourth connector, the fifth connector, the sixth connector, the seventh connector, the eighth connector, the ninth connector, and the tenth connector are all of the type J30JA-51ZKW-J.
Still further, the first high-speed connector and the third high-speed connector are each of the type HSMK-04L0-404-282-260-C.
Still further, the second high speed connector is of the type HSJ2-72ZKW3D-JA.
Still further, the model of the light module is HTG8506-MH.
The embodiment of the utility model also provides multi-interface protocol conversion equipment, which comprises a shell and the multi-interface protocol conversion system accommodated in the shell.
The utility model has the beneficial effects that: the V7 series is replaced by adopting a field programmable gate array architecture of 6K 7 series, and the V7 series is optimally arranged, so that the interface types are increased, the price is low, and the cost performance is high.
Drawings
Fig. 1 is a schematic diagram of an overall structure of a multi-interface protocol conversion system according to an embodiment of the present utility model;
fig. 2 is a schematic main structure diagram of a multi-interface protocol conversion system according to an embodiment of the present utility model shown in fig. 1;
fig. 3 is an additional structural schematic diagram of a multi-interface protocol conversion system according to the embodiment of the present utility model shown in fig. 1.
Wherein, 100, a multi-interface protocol conversion system; 1. a first field programmable gate array; 2. a second field programmable gate array; 3. a third field programmable gate array; 4. a fourth field programmable gate array; 5. a fifth field programmable gate array; 6. a sixth field programmable gate array; 7. DDR particles; 8. gigabit network phy chip; 9. a first connector; 10. a second connector; 11. an SMA connector; 12. a power module; 13. a third connector; 14. a fourth connector; 15. a fifth connector; 16. a sixth connector; 17. a seventh connector; 18. an eighth connector; 19. a ninth connector; 20. a tenth connector; 21. a first high-speed connector; 22. a second high-speed connector; 23. a third high-speed connector; 24. an optical module.
Detailed Description
The present utility model will be described in further detail with reference to the drawings and examples, in order to make the objects, technical solutions and advantages of the present utility model more apparent. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the scope of the utility model.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the description of the application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.
It will be understood that when an element is referred to as being "connected" to another element, it can be directly connected to the other element or be connected to the other element through intervening elements. In the following embodiments, "connected" is understood to mean "electrically connected", "communicatively connected", and the like, if the connected circuits, modules, units, and the like have electrical or data transferred therebetween.
As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," and/or the like, specify the presence of stated features, integers, steps, operations, elements, components, or groups thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, or groups thereof. Meanwhile, the term used in the present specification includes any and all combinations of the items listed in association.
Example 1
The present embodiment provides a multi-interface protocol conversion system 100, which is shown in connection with fig. 1 to 3, and includes a first field programmable gate array 1, a second field programmable gate array 2, a third field programmable gate array 3, three DDR particles 7, ten gigabit network chips 8, a first connector 9, a second connector 10, an SMA connector 11, a power module 12, a third connector 13, a fourth connector 14, a fifth connector 15, a sixth connector 16, a seventh connector 17, an eighth connector 18, a first high-speed connector 21, and an optical module 24.
Wherein the first field programmable gate array 1 and the second field programmable gate array 2 together provide 1 optical port. The optical port is a QSFP+ optical port.
Three DDR particles 7 are connected to the first field programmable gate array 1, the second field programmable gate array 2, and the third field programmable gate array 3 in a one-to-one correspondence, respectively.
One gigabit network chip 8 of the ten gigabit network chips 8 is connected to the first field programmable gate array 1 for providing a 1-way gigabit ethernet interface, the other gigabit network chip 8 is connected to the second field programmable gate array 2 for providing a 1-way gigabit ethernet interface, and the other eight gigabit network chips 8 are respectively connected to the third field programmable gate array 3 for providing an 8-way third field programmable gate array.
The first connector 9 is connected to the third field programmable gate array 3 and provides a 2-way CAN interface.
The second connector 10 is connected to the first field programmable gate array 1, the second field programmable gate array 2 and the third field programmable gate array 3, respectively.
SMA connectors 11 are connected to the first, second and third field programmable gate arrays 1, 2, 3, respectively, for providing a clock signal.
The power module 12 is connected to the first field programmable gate array 1, the second field programmable gate array 2 and the third field programmable gate array 3, respectively, for providing power.
The third connector 13, the fourth connector 14, the fifth connector 15, the sixth connector 16, the seventh connector 17, and the eighth connector 18 are connected to the third field programmable gate array 3, respectively; the third connector 13 is used for providing 7 paths of RS422 interfaces respectively, the fourth connector 14 is used for providing 4 paths of LVDS interfaces and 8 paths of RS422 interfaces respectively, the fifth connector 15 is used for providing 4 paths of RS422 interfaces, the sixth connector 16 is used for providing 4 paths of RS422 interfaces, the seventh connector 17 is used for providing 8 paths of LVDS interfaces and 8 paths of RS422 interfaces respectively, and the eighth connector 18 is used for providing 2 paths of LVDS interfaces and 1 path of RS422 interfaces respectively.
The first high-speed connector 21 is connected to the first field programmable gate array 1 and the second field programmable gate array 2, respectively, and provides a 2-way GTX interface through the first field programmable gate array 1, and provides a 2-way GTX interface through the second field programmable gate array 2.
The optical module 24 is connected to the first field programmable gate array 1 and the second field programmable gate array 2, respectively, and provides a 2-way GTX interface through the first field programmable gate array 1, and provides a 2-way GTX interface through the second field programmable gate array 2.
As a solution for increasing the number of interfaces, the multi-interface protocol conversion system 100 in this embodiment further includes a fourth field programmable gate array 4, a fifth field programmable gate array 5, a sixth field programmable gate array 6, three other DDR particles 7, seven other gigabit network chips 8, a ninth connector 19, a tenth connector 20, a second high-speed connector 22, and a third high-speed connector 23.
Wherein the fourth field programmable gate array 4, the fifth field programmable gate array 5 and the sixth field programmable gate array 6 together provide 6 optical ports.
The other three DDR particles 7 are connected to the fourth field programmable gate array 4, the fifth field programmable gate array 5 and the sixth field programmable gate array 6 in a one-to-one correspondence, respectively.
One of the seven other gigabit network chips 8 is connected to the fourth field programmable gate array 4, for providing a 1-way gigabit ethernet interface, the other two gigabit network chips 8 are connected to the fifth field programmable gate array 5, for providing a 2-way gigabit ethernet interface, and the other four gigabit network chips 8 are connected to the sixth field programmable gate array 6, for providing a 4-way gigabit ethernet interface.
The ninth connector 19 is connected to the sixth field programmable gate array 6 for providing a 4-way LVDS interface and a 4-way RS422 interface, respectively.
The tenth connector 20 is connected to the fifth field programmable gate array 5 for providing a 2-way LVDS interface and a 2-way RS422 interface, respectively.
The second high-speed connector 22 is respectively connected to the fourth field programmable gate array 4, the fifth field programmable gate array 5 and the sixth field programmable gate array 6, and provides an 8-way GTX interface through the fourth field programmable gate array 4, an 8-way GTX interface through the fifth field programmable gate array 5 and a 2-way GTX interface through the sixth field programmable gate array 6.
A third high speed connector 23 is connected to the sixth field programmable gate array 6 for providing a 4-way GTX interface.
In this embodiment, the first field programmable gate array 1, the second field programmable gate array 2, the third field programmable gate array 3, the fourth field programmable gate array 4, the fifth field programmable gate array 5 and the sixth field programmable gate array 6 are all XC7K325T-FGG900I. Compared with a V7 series field programmable gate array, the method has the characteristics of low price and high cost performance.
In this embodiment, the gigabit network chip 8 is 88E1111. Of course, according to actual requirements, other models can be selected.
In this embodiment, the first connector 9 is of the type J30JA-9ZKW-J. Of course, according to actual requirements, other models can be selected.
In this embodiment, the second connector 10 and the third connector 13 are each of the type J30JA-100ZKW-J. Of course, according to actual requirements, other models can be selected.
In the present embodiment, the fourth connector 14, the fifth connector 15, the sixth connector 16, the seventh connector 17, the eighth connector 18, the ninth connector 19 and the tenth connector 20 are all of the types J30JA-51ZKW-J. Of course, according to actual requirements, other models can be selected.
In this embodiment, the first high-speed connector 21 and the third high-speed connector 23 are each of the type HSMK-04L0-404-282-260-C. Of course, according to actual requirements, other models can be selected.
In this embodiment, the second high speed connector 22 is of the type HSJ2-72ZKW3D-JA. Of course, according to actual requirements, other models can be selected.
In this embodiment, the model number of the light module 24 is HTG8506-MH. Of course, according to actual requirements, other models can be selected.
The multi-interface protocol conversion system 100 in this embodiment adopts 6 field programmable gate arrays with the model of XC7K325T-FGG900I as a core technology architecture, and adopts SRIO/Auraro protocol, and provides 7 optical ports (each qsfp+ optical port realizes that 4 paths of GTX are converted into 4 paths of light). A total of 30 paths of 10Gbps high-speed GTX interfaces are provided: wherein, 1 MT optical port (each MT optical port realizes that 4 paths of GTX interfaces are converted into 4 paths of light), and the total number of the MT optical ports is 4 paths of high-speed GTX interfaces of 10 Gbps; 1 HSMK-04L0 electric interface, totally comprising 8 paths of 10Gbps high-speed GTX interfaces; 1 HSJ2-72ZKW3D-JA electric port contains 18 paths of 3.2Gbps high-speed GTX interfaces. A17-path gigabit Ethernet interface is provided, and interface protocol conversion between gigabit Ethernet TCP/UDP and RS422/LVDS is realized. A 20-way synchronous full duplex LVDS interface is provided. A 36-way asynchronous RS422 interface (which may be configured as a synchronous RS422 depending on the actual use) is provided. 2-way CAN interface. 1 path SMA-100MHz clock output, 1 path SMA synchronous input clock can be used as clock source for multi-device data synchronization. Namely, the multi-interface protocol conversion system 100 in the present embodiment has the characteristics of multiple interfaces, high performance, high cost performance, portability, and the like.
The multi-interface protocol conversion system 100 in this embodiment is converted by the optical module 24, buffered by the DDR, and input to the above-mentioned field programmable gate array, where the above-mentioned field programmable gate array processes the data in the buffer, and then the data is forwarded out through protocol conversion or directly through an optical port, an electrical port or a gigabit network; the same principle is adopted in low-speed signal processing, data received by a gigabit network port is buffered by DDR3 and then is input into the field programmable gate array, the field programmable gate array carries out operation processing on the data in the buffer memory, protocol conversion and encryption and decryption processing are carried out, and an external synchronous clock is adopted to synchronously communicate with a plurality of external devices through an LVDS/RS422 interface.
The multi-interface protocol conversion system 100 in this embodiment can replace V7 series by adopting at least 3 pieces of field programmable gate array architecture of K7 series, and perform optimized arrangement, so as to increase the kinds and the number of interfaces, and the cost is low and the cost performance is high. Meanwhile, multi-interface data processing and protocol conversion can be realized.
Example two
The present utility model also provides a multi-interface protocol conversion device, which includes a housing and a multi-interface protocol conversion system 100 as in the first embodiment. Since the multi-interface protocol conversion device in the present embodiment includes the multi-interface protocol conversion system 100 in the first embodiment, the technical effects achieved by the multi-interface protocol conversion system 100 in the first embodiment can be achieved, and the description thereof is omitted herein.
The foregoing description of the preferred embodiments of the utility model is not intended to be limiting, but rather is intended to cover all modifications, equivalents, and alternatives falling within the spirit and principles of the utility model.
The technical features of the above-described embodiments may be arbitrarily combined, and all possible combinations of the technical features in the above-described embodiments are not described for brevity of description, however, as long as there is no contradiction between the combinations of the technical features, they should be considered as the scope of the description.
The above examples merely represent a few embodiments of the present application, which are described in more detail and are not to be construed as limiting the scope of the utility model. It should be noted that it would be apparent to those skilled in the art that various modifications and improvements could be made without departing from the spirit of the present application, which would be within the scope of the present application. Accordingly, the scope of protection of the present application is to be determined by the claims appended hereto.
Claims (10)
1. The multi-interface protocol conversion system is characterized by comprising a first field programmable gate array, a second field programmable gate array, a third field programmable gate array, three DDR particles, ten gigabit network chips, a first connector, a second connector, an SMA connector, a power module, a third connector, a fourth connector, a fifth connector, a sixth connector, a seventh connector, an eighth connector, a first high-speed connector and an optical module;
wherein the first field programmable gate array and the second field programmable gate array together provide 1 optical port;
the DDR particles are respectively connected to the first field programmable gate array, the second field programmable gate array and the third field programmable gate array in a one-to-one correspondence manner;
one of ten gigabit network chips is connected to the first field programmable gate array and used for providing 1-path gigabit Ethernet interface, the other gigabit network chip is connected to the second field programmable gate array and used for providing 1-path gigabit Ethernet interface, and the other eight gigabit network chips are respectively connected to the third field programmable gate array and used for providing 8-path third field programmable gate array;
the first connector is connected to the third field programmable gate array and provides a 2-way CAN interface;
the second connector is respectively connected to the first field programmable gate array, the second field programmable gate array and the third field programmable gate array;
the SMA connectors are respectively connected to the first field programmable gate array, the second field programmable gate array and the third field programmable gate array and are used for providing clock signals;
the power supply module is respectively connected to the first field programmable gate array, the second field programmable gate array and the third field programmable gate array and is used for providing power supply;
the third connector, the fourth connector, the fifth connector, the sixth connector, the seventh connector, and the eighth connector are connected to the third field programmable gate array, respectively; the third connector is used for providing 7 paths of RS422 interfaces respectively, the fourth connector is used for providing 4 paths of LVDS interfaces and 8 paths of RS422 interfaces respectively, the fifth connector is used for providing 4 paths of RS422 interfaces, the sixth connector is used for providing 4 paths of RS422 interfaces, the seventh connector is used for providing 8 paths of LVDS interfaces and 8 paths of RS422 interfaces respectively, and the eighth connector is used for providing 2 paths of LVDS interfaces and 1 path of RS422 interfaces respectively;
the first high-speed connector is respectively connected to the first field programmable gate array and the second field programmable gate array, and provides a 2-way GTX interface through the first field programmable gate array, and provides a 2-way GTX interface through the second field programmable gate array;
the optical module is respectively connected to the first field programmable gate array and the second field programmable gate array, and provides a 2-way GTX interface through the first field programmable gate array, and provides a 2-way GTX interface through the second field programmable gate array;
the first field programmable gate array, the second field programmable gate array and the third field programmable gate array are all XC7K325T-FGG900I.
2. The multi-interface protocol conversion system of claim 1, further comprising a fourth field programmable gate array, a fifth field programmable gate array, a sixth field programmable gate array, three other of the DDR particles, seven other of the gigabit phy chips, a ninth connector, a tenth connector, a second high-speed connector, and a third high-speed connector;
the fourth field programmable gate array, the fifth field programmable gate array and the sixth field programmable gate array together provide 6 optical ports;
the other three DDR particles are respectively connected to the fourth field programmable gate array, the fifth field programmable gate array and the sixth field programmable gate array in a one-to-one correspondence manner;
one of the seven other gigabit network chips is connected to the fourth field programmable gate array and is used for providing a 1-way gigabit ethernet interface, the other two gigabit network chips are connected to the fifth field programmable gate array and are used for providing a 2-way gigabit ethernet interface, and the other four gigabit network chips are connected to the sixth field programmable gate array and are used for providing a 4-way gigabit ethernet interface;
the ninth connector is connected to the sixth field programmable gate array and is used for providing a 4-way LVDS interface and a 4-way RS422 interface respectively;
the tenth connector is connected to the fifth field programmable gate array and is respectively used for providing a 2-way LVDS interface and a 2-way RS422 interface;
the second high-speed connector is respectively connected to the fourth field programmable gate array, the fifth field programmable gate array and the sixth field programmable gate array, and provides 8 paths of GTX interfaces through the fourth field programmable gate array, 8 paths of GTX interfaces through the fifth field programmable gate array and 2 paths of GTX interfaces through the sixth field programmable gate array;
the third high-speed connector is connected to the sixth field programmable gate array and is used for providing a 4-way GTX interface;
the model numbers of the fourth field programmable gate array, the fifth field programmable gate array and the sixth field programmable gate array are XC7K325T-FGG900I.
3. The multi-interface protocol conversion system according to claim 2, wherein the gigabit network chip is model 88E1111.
4. The multi-interface protocol conversion system according to claim 1, wherein the first connector is of the type J30JA-9ZKW-J.
5. The multi-interface protocol conversion system according to claim 1, wherein the second connector and the third connector are each of a type J30JA-100ZKW-J.
6. The multi-interface protocol conversion system according to claim 2, wherein the fourth connector, the fifth connector, the sixth connector, the seventh connector, the eighth connector, the ninth connector, and the tenth connector are each of a type J30JA-51ZKW-J.
7. The multi-interface protocol conversion system according to claim 2, wherein the first high-speed connector and the third high-speed connector are each HSMK-04L0-404-282-260-C.
8. The multi-interface protocol conversion system according to claim 2, wherein the second high-speed connector is of the type HSJ2-72ZKW3D-JA.
9. The multi-interface protocol conversion system according to claim 1, wherein the optical module is model HTG8506-MH.
10. A multi-interface protocol conversion device comprising a housing and a multi-interface protocol conversion system according to any one of claims 1 to 9 housed within the housing.
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| Application Number | Priority Date | Filing Date | Title |
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| CN202322110275.8U CN220401778U (en) | 2023-08-07 | 2023-08-07 | Multi-interface protocol conversion system and equipment |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202322110275.8U CN220401778U (en) | 2023-08-07 | 2023-08-07 | Multi-interface protocol conversion system and equipment |
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| CN220401778U true CN220401778U (en) | 2024-01-26 |
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