CN215835409U

CN215835409U - Ten-gigabit single-optical-port Ethernet adapter

Info

Publication number: CN215835409U
Application number: CN202121337748.2U
Authority: CN
Inventors: 不公告发明人
Original assignee: Beijing Guang Runtong Technology Development Co ltd
Current assignee: Beijing Guang Runtong Technology Development Co ltd
Priority date: 2021-06-16
Filing date: 2021-06-16
Publication date: 2022-02-15
Anticipated expiration: 2031-06-16

Abstract

The utility model provides a gigabit single optical port Ethernet adapter which comprises a PCB (printed circuit board), a network card and a radiating fin, wherein the network card and the radiating fin are installed on the PCB; the PCIE conversion chip is connected with the PCIE connector, and the network port control chip is connected with the optical connector through a data interface; the voltage input pin of the voltage conversion chip is connected with a first filter circuit, and the power management module is connected with the power conversion chip and supplies power to other chips and circuits. The adapter can realize fault tolerance and redundancy by simultaneously binding and aggregating a plurality of ports into a group so as to ensure network performance and expand network bandwidth, and realize that communication from a fault port is routed to other members in the same group to continuously operate so as to realize uninterrupted high-performance communication.

Description

Ten-gigabit single-optical-port Ethernet adapter

Technical Field

The utility model belongs to the technical field of network adapters, and particularly relates to a gigabit single-optical-port Ethernet adapter.

Background

With the progress of science and technology, people have more and more demand for information, and optical fiber transmission information has the advantages of large transmission capacity, good confidentiality, rapidness, convenience and the like, so that the optical fiber transmission information gradually becomes the most main transmission medium of network data. At present, the optical fiber network adapter on the host of a personal computer, a workstation or a server takes a PCI express interface as a mainstream, the number of ports on the optical fiber network adapter can be 1 to 4 according to different functions of the host, the ports are electrically connected with a socket, and the socket is used for inserting a small optical signal receiver. After the optical fiber is connected to the small optical signal transceiver, the optical fiber can be used for data transmission. However, for a server which is continuously updated, a traditional network adapter is not suitable any more due to the fact that the number of ports is small or the interfaces are not adaptive, and cannot be deployed in a use environment with multiple network requirements; and uninterrupted communication cannot be achieved when a failed port is signaled.

SUMMERY OF THE UTILITY MODEL

In order to solve the technical problem, the utility model provides a gigabit single optical interface Ethernet adapter.

The specific technical scheme of the utility model is as follows:

the utility model provides a gigabit single optical port Ethernet adapter which comprises a PCB (printed circuit board), a network card and a radiating fin, wherein the network card and the radiating fin are installed on the PCB, the network card comprises a network port control chip U1A, a port expansion control chip U1B, a PCIE conversion chip U1C, PCIE connector J2, an optical port connector J4, a voltage conversion chip U1D, a power management module and a plurality of peripheral circuits, and the port expansion control chip U1B and the PCIE conversion chip U1C are both connected with the network port control chip U1A; the PCIE switching chip U1C is connected to a PCIE connector J2, and the network port control chip U1A is connected to the optical port connector J4 through a data interface; the voltage input pin of the voltage conversion chip U1D is connected with a first filter circuit, and the power supply management module is connected with the power supply conversion chip U1D and supplies power to other chips and circuits.

Further, four SDP protocol port pin groups and two receiving and transmitting pin groups are built in the network port control chip U1A; the network port control chip U1A is also connected with an indicator light circuit through a built-in LED pin, and the indicator light circuit is connected with a jumper connector J1 in parallel; an XTAL pin arranged in the network port control chip U1A is connected with an external clock circuit.

Further, the external clock circuit comprises a crystal oscillator Y1, and two ends of the crystal oscillator Y1 are respectively connected with the network port control chip U1A and are respectively grounded through capacitors.

Further, the port expansion control chip U1B is connected with a bypass module through a built-in GIPO port pin, the port expansion control chip U1B is connected with a FLASH memory chip U2 through a built-in FLASH memory pin, and the port expansion control chip U1B is internally provided with NCSI and SMB communication protocol interfaces.

Further, the bypass module comprises a bypass chip U1G, and the bypass chip U1G is connected with a jumper connector J2 through a power supply pin.

Further, the PCIE connector J2 employs a PCI-EX8 chip.

Further, the optical port connector J4 is an SPF + connector.

Further, the power management module comprises a power chip U7 and a voltage regulation control chip U3 which are connected, and both the power chip U7 and the voltage regulation control chip U3 are connected with a filter circuit.

Still further, the power chip U7 adopts a chip with a model number of TPS54627, and the voltage regulation control chip U3 adopts a chip with a model number of TPS 53353.

The utility model has the following beneficial effects: the utility model provides a gigabit single optical port Ethernet adapter which comprises an optical port control module, a port expansion module and a PCIE interface module, wherein the adapter can be simultaneously bound and aggregated into a group through a plurality of ports to realize fault tolerance and redundancy so as to ensure network performance and expand network bandwidth, can realize real-time self-detection and realize that communication from a fault port is routed to other members in the same group to continuously operate so as to realize uninterrupted high-performance communication; it has the advantage that multiple networks can be deployed and that critical network applications and environments are deployed on high performance servers.

Drawings

Fig. 1 is a schematic structural diagram of a gigabit single optical port ethernet adapter according to an embodiment;

fig. 2 is a circuit configuration diagram of an internet access control chip according to an embodiment;

FIG. 3 is a circuit diagram of a port expansion control chip according to an embodiment;

FIG. 4 is a circuit diagram of a bypass chip according to an embodiment;

fig. 5 is a circuit configuration diagram of a PCIE interface module according to the embodiment;

FIG. 6 is a circuit diagram of a power management module according to an embodiment;

fig. 7 is a circuit structure diagram of a voltage conversion chip according to an embodiment.

Detailed Description

The present invention will be described in further detail with reference to the following examples and drawings.

Examples

As shown in fig. 1, an embodiment of the present invention provides a gigabit single optical port ethernet adapter, where the adapter includes a PCB, a network card and a heat sink mounted on the PCB, the network card includes an internet port control chip U1A, a port expansion control chip U1B, a PCIE conversion chip U1C, a PCIE connector J2, an optical port connector J4, a voltage conversion chip U1D, a power management module, and a plurality of peripheral circuits, and both the port expansion control chip U1B and the PCIE conversion chip U1C are connected to the internet port control chip U1A; the PCIE switching chip U1C is connected to a PCIE connector J2, and the network port control chip U1A is connected to the optical port connector J4 through a data interface; the voltage input pin of the voltage conversion chip U1D is connected with a first filter circuit, and the power supply management module is connected with the power supply conversion chip U1D and supplies power to other chips and circuits.

In the example, the network card chip adopts an XL710 series chip, and a PCIE slot version and bandwidth are supported, wherein a PCIE connector J2 adopts a PCI-EX8 chip, and the slot has flexible double-port 10GbE link rate, so that the network card chip can be conveniently used in a use environment with a plurality of network requirements; the optical port connector J4 is an SPF + connector, and the SFP + optical port connector fully supports full-height and half-height slot heights.

As shown in fig. 2, in a specific implementation, four SDP protocol port pin groups and two transceiving pin groups are built in the network interface control chip U1A, where one transceiving pin group is connected to the transmitting terminal TXB and the receiving terminal RXB. The chip configures a virtual machine load balancing VLMB on a virtualization function, and the VMLB provides load balancing (TX and RX) and has a fault tolerance function. The network port control chip U1A is also connected with an indicator light circuit through a built-in LED pin, and the indicator light circuit is connected with a jumper connector J1 in parallel; wherein, in specific application, the pilot lamp identification state includes: the blue normally-on mark is 10GB/s, the green flashing mark is a link state, and the like, and the indicator light is not on and is marked as a no-network state. An XTAL pin arranged in the network port control chip U1A is connected with an external clock circuit. The external clock circuit comprises a crystal oscillator Y1, the crystal oscillator Y1 adopts 25.00MHz specification, and two ends of the crystal oscillator Y1 are respectively connected with the network port control chip U1A and are respectively grounded through 20pF capacitors.

As shown in fig. 3, in a specific implementation, the port expansion control chip U1B is connected to a bypass module through a built-in GIPO port pin, the port expansion control chip U1B is connected to a FLASH memory chip U2 through a built-in FLASH pin, the FLASH memory chip U2 adopts an AT25DF321A chip, the port expansion control chip U1B is provided with NCSI and SMB communication protocols, and a protocol interface is connected to a slot. As shown in fig. 4, the bypass module includes a bypass chip U1G, and the bypass chip U1G is connected to a jumper connector J2 through a power supply pin (RSVD pin), and is connected to a power supply 3P3V through a jumper connector J2.

As shown in fig. 5, the PCIE conversion chip U1C is connected to the network port control chip U1A through a wiring, the PCIE conversion chip U1C includes a signal receiving pin group (PCIE GEN3 REVEIVE) and a signal conversion pin group (PCIE GEN3 transition), the signal receiving pin group includes 7 pairs of PERxx signals (PERn 0-7, PERp 0-7) for receiving link signals, the signal conversion pin group includes 7 pairs of PETxx signals (PETn 0-7, PETp 0-7) for converting and transmitting link signals, and the signal receiving group is connected through a pin PER. The PCIE connector is provided with a PRSNT pin connected to hardware, and an interface slot of the PCIE connector is configured to correspond to each pin in the PICE conversion chip U1C.

As shown in fig. 6, in a specific implementation, the power management module includes a power chip U7 and a voltage regulation control chip U3, which are connected, and both the power chip U7 and the voltage regulation control chip U3 are connected to a filter circuit. Part of output voltage in the voltage stabilization control chip U3 and special feedback pins of other chips are connected with a voltage stabilization control chip U3, 5 VIN pins of input voltage are arranged in the voltage stabilization control chip U3, and the voltage stabilization control chip U3 is connected with a second filter circuit through 5 LL pins; specifically, the high potential end of the digital power supply is connected with an LL pin of the chip through a second filter circuit; furthermore, the chip also realizes voltage reduction conversion through a feedback mechanism. The switch control pin SW and the reference voltage pin VFB of the power chip U7 are connected to a third filter circuit, and the output voltage is filtered by the filter circuit. In a specific example, the power chip U7 adopts a chip with a model number of TPS54627, and the voltage regulation control chip U3 adopts a chip with a model number of TPS 53353.

As shown in fig. 7, the voltage conversion chip U1D is used for converting an analog power supply high voltage into a digital power supply high voltage to realize power conversion, and the power is output to the voltage regulation control chip U3.

The present invention is not limited to the above-mentioned preferred embodiments, and any other products in various forms can be obtained by anyone in the light of the present invention, but any changes in the shape or structure thereof, which have the same or similar technical solutions as those of the present application, fall within the protection scope of the present invention.

Claims

1. The ten-gigabit single-optical-port Ethernet adapter comprises a PCB (printed circuit board), a network card and a radiating fin, wherein the network card is installed on the PCB and is characterized by comprising an internet port control chip U1A, a port expansion control chip U1B, a PCIE conversion chip U1C, a PCIE connector J2, an optical port connector J4, a voltage conversion chip U1D, a power management module and a plurality of peripheral circuits, wherein the port expansion control chip U1B and the PCIE conversion chip U1C are both connected with the internet port control chip U1A; the PCIE switching chip U1C is connected to a PCIE connector J2, and the network port control chip U1A is connected to the optical port connector J4 through a data interface; the voltage input pin of the voltage conversion chip U1D is connected with a first filter circuit, and the power management module is connected with the voltage conversion chip U1D and supplies power to other chips and circuits.

2. The gigabit single optical port ethernet adapter as claimed in claim 1, wherein said network port control chip U1A has four SDP protocol port pin sets and two receive and transmit pin sets built therein; the network port control chip U1A is also connected with an indicator light circuit through a built-in LED pin, and the indicator light circuit is connected with a jumper connector J1 in parallel; an XTAL pin arranged in the network port control chip U1A is connected with an external clock circuit.

3. The gigabit single optical port ethernet adapter according to claim 2, wherein said external clock circuit comprises a crystal oscillator Y1, and both ends of said crystal oscillator Y1 are respectively connected to said network port control chip U1A and are respectively grounded through capacitors.

4. The gigabit single optical port ethernet adapter as claimed in claim 1, wherein said port expansion control chip U1B is connected to a bypass module via a built-in GIPO port pin, said port expansion control chip U1B is connected to a FLASH memory chip U2 via a built-in FLASH pin, and said port expansion control chip U1B is built-in with NCSI, SMB communication protocol interfaces.

5. The gigabit single optical port ethernet adapter as claimed in claim 4, wherein said bypass module comprises a bypass chip U1G, said bypass chip U1G being connected to a jumper connector J2 via power pins.

6. The gigabit single optical port ethernet adapter as claimed in claim 1, wherein said PCIE connector J2 employs a PCI-EX8 chip.

7. The gigabit single optical port ethernet adapter as claimed in claim 1, wherein said optical port connector J4 is an SPF + connector.

8. The gigabit single optical port ethernet adapter as claimed in claim 1, wherein said power management module comprises a power chip U7 and a voltage regulation control chip U3 connected to each other, and a filter circuit is connected to each of said power chip U7 and said voltage regulation control chip U3.

9. The gigabit single optical port ethernet adapter as claimed in claim 8, wherein said power chip U7 is a chip with model number TPS54627, and said voltage regulation control chip U3 is a chip with model number TPS 53353.