CN213094226U

CN213094226U - CAN communication device based on CPCI bus

Info

Publication number: CN213094226U
Application number: CN202022409403.5U
Authority: CN
Inventors: 吴万杰; 余常恒; 张聪; 雷小江; 孙甲雨; 周苏茂
Original assignee: Hubei Sanjiang Aerospace Wanfeng Technology Development Co Ltd
Current assignee: Hubei Sanjiang Aerospace Wanfeng Technology Development Co Ltd
Priority date: 2020-10-26
Filing date: 2020-10-26
Publication date: 2021-04-30
Anticipated expiration: 2030-10-26

Abstract

The utility model relates to a CAN communication technology field, concretely relates to CAN communication device based on CPCI bus. The CPCI bus controller comprises an FPGA controller, a CPCI bus controller, a CPCI connector, a level shifter, a CAN controller and a CAN isolation receiving and transmitting circuit, wherein a first data transmission port of the FPGA controller is connected with one end of the CPCI bus controller, the other end of the CPCI bus controller is connected with the CPCI connector, the CPCI connector is inserted on a CPCI bottom plate of a computer mainboard, a second data transmission port of the FPGA controller is connected with one end of the level shifter, the other end of the level shifter is connected with one end of the CAN controller, and the other end of the CAN controller is connected with the CAN isolation receiving and transmitting circuit. CPCI bus communication is realized through a PCI bridge chip, and the communication is carried out with the FPGA through a local bus, and the FPGA realizes the CAN communication function through controlling a CAN controller.

Description

CAN communication device based on CPCI bus

Technical Field

The utility model relates to a CAN communication technology field, concretely relates to CAN communication device based on CPCI bus.

Background

CPCI is a bus interface standard proposed by international association of industrial computer manufacturers in 1994, and is a high-performance industrial bus using PCI electrical specification as a standard. The method has the advantages of high performance, support of linear burst transmission, extremely small access delay, adoption of bus master control and synchronous operation, no limitation of a processor, suitability for various types of machines, strong compatibility, reservation of development space, low cost, high benefit, plug and play and the like. The bus width is 32-bit bus, and the communication rate is 33.3 MHz.

As weaponry systems grow in size, the communication networks between individual, components within the systems become more complex. Especially for a ground measurement and control system, one control host generally needs to communicate with a large number of other devices, so that the requirements on the number of communication channels and the communication rate of the host are high, and the communication requirements cannot be met by single CPCI communication.

SUMMERY OF THE UTILITY MODEL

The utility model aims at being exactly to prior art's defect, provide a CAN communication device based on CPCI bus, CAN realize CPCI bus communication through PCI bridge chip to communicate with FPGA through local bus, FPGA realizes the function of CAN communication through controlling the CAN controller, makes the communication channel number and the communication speed of host computer satisfy the communication requirement that gradually becomes high day by day.

The technical scheme of the utility model is that: a CAN communication device based on a CPCI bus comprises an FPGA controller, a CPCI bus controller, a CPCI connector, a level shifter, a CAN controller and a CAN isolation receiving and transmitting circuit, wherein a first data transmission port of the FPGA controller is connected with one end of the CPCI bus controller, the other end of the CPCI bus controller is connected with the CPCI connector, the CPCI connector is inserted on a CPCI bottom plate of a computer mainboard, a second data transmission port of the FPGA controller is connected with one end of the level shifter, the other end of the level shifter is connected with one end of the CAN controller, and the other end of the CAN controller is connected with the CAN isolation receiving and transmitting circuit.

Preferably, the FPGA controller is further connected with an FPGA configurator.

Preferably, the power supply device further comprises a power supply board and a power supply conversion circuit, wherein the power supply conversion circuit is provided with a plurality of power supply output ends, the output voltages of the power supply output ends are different, and the input end of the power supply conversion circuit is connected with the power supply board.

Preferably, the power conversion circuit is an LDO linear power supply, and the plurality of power output ends of the LDO linear power supply are respectively 3.3V, 2.5V, 1.2V, and 1.8V power output ends.

Preferably, the CPCI bus controller is connected to an EEPROM.

Preferably, the CAN controllers connected with the other end of the level shifter are multiple, and each CAN controller is connected with one CAN isolation transceiver circuit.

The utility model has the advantages that: CPCI bus communication is realized through a PCI bridge chip, and the communication is carried out with the FPGA through a local bus, and the FPGA realizes the CAN communication function through controlling a CAN controller. The device adopts a CPCI 6U standard European board card form, and plays a role by inserting a computer system case based on a Loongson processor of a 6U CPCI bus. The method has the advantages of good real-time performance, high reliability and multi-node support.

Drawings

Fig. 1 is a schematic connection diagram of a CAN communication device based on a CPCI bus according to the present invention;

fig. 2 is a schematic connection diagram of the CAN communication device based on the CPCI bus in the chassis of the present invention.

Detailed Description

The invention will be further described in detail with reference to the drawings and the following detailed description, which are provided for the purpose of clearly understanding the invention and are not intended to limit the invention.

A CPCI bus-based CAN communication device adopts a 6U CPCI standard European board card form, one CPCI bus led out from a chassis backboard is subjected to local bus bridging by using an FPGA chip and is converted into an address data bus and related control signals required by a CAN controller, CAN interfaces are subjected to signal isolation by using high-speed optocouplers, and an isolation power supply is provided for each communication channel by using an isolation DC-DC, so that the CAN bus transceiving function is realized.

As shown in fig. 1, a CAN communication device based on a CPCI bus comprises an FPGA controller, a CPCI bus controller, a CPCI connector, a level shifter, a CAN controller, an FPGA configurator and a CAN isolation transceiver circuit, wherein a first data transmission port of the FPGA controller is connected with one end of the CPCI bus controller, the other end of the CPCI bus controller is connected with the CPCI connector, the CPCI connector is inserted into a CPCI bottom plate of a computer motherboard, a second data transmission port of the FPGA controller is connected with one end of the level shifter, the other end of the level shifter is connected with one end of the CAN controller, and the other end of the CAN controller is connected with the CAN isolation transceiver circuit. The CAN controllers connected with the other end of the level shifter are multiple, and each CAN controller is connected with one CAN isolation receiving and transmitting circuit. The FPGA configurator is connected to the FPGA controller, and the CPCI bus controller is connected to the EEPROM.

Preferably, the power supply device further comprises a power supply board and a power supply conversion circuit, wherein the power supply conversion circuit is provided with a plurality of power supply output ends, the output voltages of the power supply output ends are different, and the input end of the power supply conversion circuit is connected with the power supply board. The power conversion circuit is an LDO linear power supply, and a plurality of power output ends of the LDO linear power supply are respectively a 3.3V power output end, a 2.5V power output end, a 1.2V power output end and a 1.8V power output end.

The CPCI bus controller adopts SM9056 of Shenzhen national micro company, and the FPGA adopts SMQ2V1000FG456 of the Shenzhen national micro company. The CPCI bus interface circuit mainly comprises a PCI bridge chip and a CPCI connector. The PCI bridge chip selects SM9056, and the CPCI connector selects a Sichuan Huafeng HM2 series high-speed backboard connector. As known from the CPCI protocol, the AD0-AD31, C/BE0# -C/BE3#, PAR #, FRAME #, IRDY #, TRDY #, STOP #, LOCK #, IDSEL #, DEVSEL #, PERR #, SERR #, RST #, INTA # signals of the 32-bit CPCI bus are used and must BE connected with a10 ohm matching resistor in series. The 64 bit CPCI bus signals are not used, but if the levels of these signals are not constant, the level values of other signals are affected, so the REQ64# and ACK64# signals need to be pulled up through a 10K resistor.

The CPCI bus interface circuit is divided into a master device and a slave device. The master device may control the bus, drive address, data, and control signals. The slave device cannot initiate bus operations and can only rely on the master device to read data from or transfer data to it. Therefore, the bus interface circuit of the CAN communication board is required to be set as a slave device. The data transfer mode between the local bus of the SM9056 and the PCI bus is set to the slave mode. The configuration information of the SM9056 internal register is written in the EEPROM, the serial EEPROM configuration information can be automatically loaded when the EEPROM is powered on, and the configuration register can be read and written through the PCI bus. The EEPROM adopts SM93C66A of Shenzhen national micro company.

The SM9056 mainly comprises 3 working modes including an M mode, a C mode and a J mode. The M mode is an address line and data line non-multiplexing interface prepared for MPCs 850 and MPC860 of Motorola corporation; the address line and the data line of the C mode are not multiplexed; the address lines and data lines of the J-mode are multiplexed. The M mode has a small use range, the J mode has a complex control mode when being used, and the C mode is generally used. The present board card SM9056 is configured in C mode. The configuration can be performed only by pulling down the chip pins a15(Mode0) and B15(Mode1) through a 4.7K resistor.

The FPGA is used as a main control core of the communication device. The control system is mainly connected with a bridge chip, completes LOCAL BUS control and CAN BUS communication control. The JTAG circuit mainly completes the functions of FPGA program downloading and online debugging. The FPGA configurator adopts SM32PVOG48C of Shenzhen national micro company, and the storage capacity is 32 Mbits.

The bridge chip SM9056 needs 2.5V (kernel) and 3.3V (I/O) for power supply; the FPGA needs 3.3V (I/O), 1.2V (kernel) and 2.5V (auxiliary power supply) for power supply; PROM configurators require 1.8V power. Therefore, the system 5V voltage signal needs to be converted into 3.3V, 2.5V, 1.2V and 1.8V to supply power to each module. The LDO power supply selects the Shenzhen national micro power supply module SM4616MPV, the 5V of the system is converted into 3.3V and 1.2V, and the maximum output currents of the two paths of outputs are both 8A. The Shenzhen country micro power supply module SM74401RGW is selected in the auxiliary power supply mode, the 5V of the system is converted into 2.5V and 1.8V, the maximum output current is 3A, and the power supply requirement is met.

Signals coming out of the FPGA are 3.3V signals, and need to be subjected to level conversion and then sent to the CAN controller, and the level converter adopts Shenzhen national micro SM 164245. The CAN controller selects Shenzhen Guomi SMSJA1000, and the transmission rate CAN reach 1 Mbps. The SM1040 of Shenzhen national minister company is selected for use to the CAN transceiver, and transmission rate CAN reach 1Mbps, because the circuit is inside not to take the isolation, needs to add the optical coupling before the transceiver and carry out electrical isolation to the signal, for satisfying CAN communication rate requirement, northern light high-speed opto-coupler GH6431 is selected to the opto-coupler, and transmission rate is 20 MHz. The CAN isolation transceiver is independently powered by a Beijing new lightning energy power module LDC 010505S.

As shown in fig. 2, a computer system of a Loongson processor comprises a computer CPCI motherboard of the Loongson processor and a plurality of CPCI function board cards, and the CAN communication device of the invention is used as one of the CPCI function board cards and is plugged on a CPCI base plate. And communicating with the computer mainboard through the CPCI bus. The CAN communication board may be inserted in peripheral slots other than the system slot.

Details not described in this specification are within the skill of the art that are well known to those skilled in the art.

Claims

1. The utility model provides a CAN communication device based on CPCI bus which characterized in that: the CPCI bus controller comprises an FPGA controller, a CPCI bus controller, a CPCI connector, a level shifter, a CAN controller and a CAN isolation receiving and transmitting circuit, wherein a first data transmission port of the FPGA controller is connected with one end of the CPCI bus controller, the other end of the CPCI bus controller is connected with the CPCI connector, the CPCI connector is inserted on a CPCI bottom plate of a computer mainboard, a second data transmission port of the FPGA controller is connected with one end of the level shifter, the other end of the level shifter is connected with one end of the CAN controller, and the other end of the CAN controller is connected with the CAN isolation receiving and transmitting circuit.

2. A CAN communication device according to claim 1, wherein: and the FPGA controller is also connected with an FPGA configurator.

3. A CAN communication device according to claim 1, wherein: the power supply conversion circuit is provided with a plurality of power supply output ends, the output voltage of each power supply output end is different, and the input end of the power supply conversion circuit is connected with the power supply board.

4. A CAN communication device according to claim 3, wherein: the power conversion circuit is an LDO linear power supply, and a plurality of power output ends of the LDO linear power supply are respectively a 3.3V power output end, a 2.5V power output end, a 1.2V power output end and a 1.8V power output end.

5. A CAN communication device according to claim 1, wherein: and the CPCI bus controller is connected with an EEPROM.

6. A CAN communication device according to claim 1, wherein: the CAN controllers connected with the other end of the level shifter are multiple, and each CAN controller is connected with one CAN isolation receiving and transmitting circuit.