CN213693732U - Data transmission system and router with built-in data transmission system - Google Patents

Abstract

A data transmission system and router with built-in data transmission system, including backboard, master control board, slave control board, service board and HMIM interface card, the said master control board and the said slave control board form a double master control system, when the said master control board and the said slave control board are in place and powered on and started at the same time, the operation of the said master control board is defaulted to be the current state, the said slave control board will increase the delay automatically so as to operate to be the standby state, there is a hardware signal line between the said master control board and the said slave control board, when the said master control board is pulled out or can't work normally because of the fault, the said slave control board will switch over and manage the whole data transmission system automatically; the service board is connected with the back board through two PCIE connectors; and meanwhile, the back plate is connected with a plurality of HMIM interface cards. Compared with the prior art, the utility model has the advantages of it is following: the master control board and the slave control board can be switched at any time, the router can be kept to be stably on line, and meanwhile, a plurality of HMIM interface cards can be accessed as required.

Description

Data transmission system and router with built-in data transmission system

Technical Field

The utility model belongs to the technical field of data transmission communication, concretely relates to data transmission system and built-in this data transmission system's router.

Background

With the large-scale application of cloud services and the deep application of big data, network data transmission becomes a focus of more and more deep attention of people, and users not only need the accuracy, safety and rapidity of network transmission data, but also need the stability of network transmission. The router is a core device in network transmission, a user puts higher requirements on the router device, in the current network data transmission, the router must be ensured to operate normally all the time, because the router is the core of the whole network, if the router has fatal failure, the paralysis of the local network is caused, if the router is a backbone router, the influence range is larger, and the caused loss is difficult to estimate.

In order to avoid fatal trouble of router emergence, the utility model provides a data transmission system and built-in this data transmission system's router, device, data transmission system contain main control board and follow the control board, and main control board and follow the control board can automatic switch over, when the main control board reinserts or trouble shooting resumes normal work again, the slave control board that is working at present still keeps the state of giving first place to, and the main control board can move the state of doing for oneself; when the slave control board is pulled out or can not work normally due to faults, the main control board in place can be converted into a master state again; when the slave control board is reinserted or the fault is removed and the normal work is recovered, the state of the slave control board can be automatically used as a standby state.

SUMMERY OF THE UTILITY MODEL

An object of the utility model is to provide a data transmission system and built-in this data system's router, device aim at satisfying network data transmission and last stable online requirement to the router.

In order to achieve the above object, the present invention provides a data transmission system, which comprises a back plate, a master control board, a slave control board, a service board and an HMIM interface card, wherein a CPU chip in the master control board is electrically connected with the back plate in two directions through a control bus, a MAC chip and a CPLD logic chip in the master control board are electrically connected with the back plate in two directions, a CPU chip in the slave control board is electrically connected with the back plate in two directions through a control bus, a MAC chip and a CPLD logic chip in the slave control board are electrically connected with the back plate in two directions, the master control board and the slave control board form a dual master control system, when the master control board and the slave control board are in place and powered on simultaneously, the master control board is defaulted to be in a current state, the slave control board can automatically increase a delay so as to operate in a standby state, a hardware signal line is arranged between the master control board and the slave control board, when the master control board is pulled out or cannot normally operate due to, the slave control board can automatically switch and manage the whole data transmission system; the service board is connected with the back board through two PCIE connectors; and meanwhile, the back plate is connected with a plurality of HMIM interface cards.

Further, the main control board includes: the device comprises a CPU chip, a DDR4 memory bank, a Flash memory, a clock module, a PWR power supply, a PHY chip, an RJ45 interface, a CON interface, a USB converter, an eMMC multimedia card, an MAC chip and a CPLD logic chip; the CPU chip is electrically connected with a DDR4 memory bank, a Flash memory and a CON interface, the PHY chip is bidirectionally and electrically connected with the CPU chip, and the RJ45 interface is bidirectionally and electrically connected with the PHY chip; the USB converter is in bidirectional electric connection with the CPU chip, and the USB converter is respectively in bidirectional electric connection with a USB interface and an eMMC multimedia card; the MAC chip and the CPLD logic chip are respectively in bidirectional electrical connection with the CPU chip.

Further, the slave control board includes: the device comprises a CPU chip, a DDR4 memory bank, a Flash memory, a clock module, a PWR power supply, a PHY chip, an RJ45 interface, a CON interface, a USB converter, an eMMC multimedia card, an MAC chip and a CPLD logic chip; the CPU chip is electrically connected with a DDR4 memory bank, a Flash memory and a CON interface, the PHY chip is bidirectionally and electrically connected with the CPU chip, and the RJ45 interface is bidirectionally and electrically connected with the PHY chip; the USB converter is in bidirectional electric connection with the CPU chip, and the USB converter is respectively in bidirectional electric connection with a USB interface and an eMMC multimedia card; the MAC chip and the CPLD logic chip are respectively in bidirectional electrical connection with the CPU chip.

Further, the service board includes: the device comprises a CPU chip, a DDR3 memory bank, a Flash memory, a clock module, a PCIE connector, an MAC chip, an RJ45 interface, an SFP28 interface, an SFP + interface and an SFP interface; the DDR3 memory bank and the Flash memory are electrically connected with the CPU chip; the CPU chip is in bidirectional electrical connection with the 2 PCIE connectors; the MAC chip is electrically connected with the CPU chip in a bidirectional way, and the MAC chip is electrically connected with the RJ45 interface, the SFP28 interface, the SFP + interface and the SFP interface respectively.

Further, the number of the RJ45 interfaces is 16.

Further, the number of the SFP28 interfaces is 4.

Furthermore, the number of the SFP + interfaces is 4.

Further, the number of the SFP interfaces is 12.

Further, the router includes at least any one of the above data transmission systems.

Compared with the prior art, the utility model has the advantages of it is following: the master control board and the slave control board can be switched at any time, the router can be kept to be stably on line, and meanwhile, a plurality of HMIM interface cards can be accessed as required.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are required to be used in the embodiments of the present application will be briefly described below, it should be understood that the following drawings only illustrate some embodiments of the present application and therefore should not be considered as limiting the scope, and that those skilled in the art can also obtain other related drawings based on the drawings without inventive efforts.

Fig. 1 the logic structure diagram of the main control board of the present invention.

Fig. 2 is a logical structure diagram of the slave control board of the present invention.

Fig. 3 is a logical structure diagram of the service board of the present invention.

Fig. 4 is a logical structure diagram of the data transmission system of the present invention.

Detailed Description

The following description of the embodiments of the present invention is provided for illustrative purposes, and other advantages and effects of the present invention will be readily apparent to those skilled in the art from the disclosure herein. The present invention can also be implemented or applied through other different specific embodiments, and various details in the present specification can be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

The technical solutions in the embodiments of the present application will be described below with reference to the drawings in the embodiments of the present application.

It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, it need not be further defined and explained in subsequent figures. Meanwhile, in the description of the present application, the terms "first", "second", and the like are used only for distinguishing the description, and are not to be construed as indicating or implying relative importance.

Please refer to fig. 1 to 4. It should be noted that the drawings provided in the present embodiment are only for illustrating the basic idea of the invention in a schematic manner, and only the components related to the invention are shown in the drawings rather than being drawn according to the number, shape and size of the components in actual implementation, and the form, quantity and proportion of the components in actual implementation may be changed at will, and the layout of the components may be more complicated.

The first embodiment.

As shown in fig. 1, the present embodiment provides a logical structure diagram of a main control board.

The main control board includes: the device comprises a CPU chip, a DDR4 memory bank, a Flash memory, a clock module, a PWR power supply, a PHY chip, an RJ45 interface, a CON interface, a USB converter, an eMMC multimedia card, an MAC chip and a CPLD logic chip.

The CPU chip is electrically connected with a DDR4 memory bank, a Flash memory and a CON interface, the PHY chip is bidirectionally and electrically connected with the CPU chip, and the RJ45 interface is bidirectionally and electrically connected with the PHY chip; the USB converter is in bidirectional electric connection with the CPU chip, and the USB converter is respectively in bidirectional electric connection with a USB interface and an eMMC multimedia card; the MAC chip and the CPLD logic chip are respectively in bidirectional electrical connection with the CPU chip.

Flash memory, which belongs to one type of memory devices, is a Non-Volatile (Non-Volatile) memory. The flash memory can hold data for a long time without current supply, and has the storage characteristic equivalent to that of a hard disk, and the characteristic is the basis of the flash memory which becomes a storage medium of various portable digital devices.

The PHY chip is a tiny controller, and integrates an Ethernet Media Access Controller (MAC) and a physical interface transceiver (PHY) into the same chip, so that a plurality of external components can be removed. The scheme can realize good matching between the MAC and the PHY, and can reduce the pin number and the chip area. The single-chip ethernet microcontroller also reduces power consumption, particularly in the case of a power-down mode.

The MAC chip is a data message exchange forwarding chip.

The PWR power supply module is a dual power supply redundant design.

Example two.

As shown in fig. 2, the present embodiment provides a logical structure of the slave control board.

The logical structure of the slave control board is completely the same as that of the master control board.

Example three.

As shown in fig. 3, the present embodiment provides a logical structure diagram of a service board.

The service board comprises: the device comprises a CPU chip, a DDR3 memory bank, a Flash memory, a clock module, a PCIE connector, an MAC chip, an RJ45 interface, an SFP28 interface, an SFP + interface and an SFP interface; the DDR3 memory bank and the Flash memory are electrically connected with the CPU chip.

The CPU chip is in bidirectional electrical connection with the 2 PCIE connectors; the MAC chip is electrically connected with the CPU chip in a bidirectional mode. The MAC chip is electrically connected with the RJ45 interface, the SFP28 interface, the SFP + interface and the SFP interface respectively.

The number of the RJ45 interfaces is 16, the number of the SFP28 interfaces is 4, the number of the SFP + interfaces is 4, and the number of the SFP interfaces is 12.

The PWR power supply module is a dual power supply redundant design.

The RJ45 interface is commonly used for data transmission, and the most common application is a network card interface.

RJ45 is one type of various connectors, RJ45 connectors are two types according to the different methods of the ordering of the wires, one is orange white, orange, green white, blue white, green, brown white, brown, and the other is green white, green, orange white, blue white, orange, brown white, brown, and therefore there are two types of wires using RJ45 connectors: straight lines, cross lines.

The SFP28 interface may address the upcoming 6 th generation (32GFC) optical channel market and future 25 gigabit ethernet applications, and the SFP28 optical module is SFF-8432 compatible and will support data rates of 25.78125 Gbps (for 25GbE) and 28.05 Gbps (for 32 GFC).

The SFP + interface, a hot-pluggable, communication protocol independent optical transceiver, typically transmits light at 850nm, 1310nm or 1550nm for 10 gbps SONET/SDH, fibre channel, gigabit Ethernet, 10 gigabit Ethernet and other applications, including DWDM links. XFP contains a digital diagnostic module similar to SFF-8472, but is expanded to provide a powerful diagnostic tool.

SFP interfaces (which are more than a factor of two smaller in volume than GBIC modules and can be configured with more than a factor of two ports on the same panel, since SFP modules are essentially identical in function to GBICs, they are also called miniaturized GBICs (Mini-GBICs) by some switch manufacturers.

Example four.

As shown in fig. 4, the present embodiment provides a logical structure diagram of a data transmission system.

The utility model provides a data transmission system, including backplate, main control board, follow control board, business board and HMIM interface card, CPU chip in the main control board pass through control bus with the two-way electricity of backplate is connected, MAC chip and CPLD logic chip in the main control board with the two-way electricity of backplate is connected, CPU chip in the follow control board pass through control bus with the two-way electricity of backplate is connected, MAC chip and CPLD logic chip in the follow control board with the two-way electricity of backplate is connected.

The master control board and the slave control boards form a double-master control system, when the two master control boards are in place and powered on and started at the same time, the master control board is defaulted to be in a master operation state, and the slave control board system software can automatically increase delay so as to be in a standby operation state; a hardware signal line is arranged between the two main controllers, and when the main controller is pulled out or can not work normally due to faults, the slave controller can be automatically switched to the main controller to manage the whole router device; when the master control board is reinserted or the fault is eliminated and the normal work is recovered, the slave control board which is currently working still keeps the state of master control board, and the master control board can automatically run to the state of standby; when the slave control board is pulled out or can not work normally due to faults, the main control board in place can be converted into a master state again; when the slave control board is reinserted or the fault is removed and the normal work is recovered, the state of the slave control board can be automatically used as a standby state. As described above, the operation of the two main control boards is switched between these states.

The backplane is a connector of the whole router device, can connect all systems of the master control board, the slave control board, the service board and the HMIM interface card, and is a physical channel among all board card subsystems.

The control bus is a special control bus, and control instructions are transmitted among different main control boards CPU, including the main and standby switching of the main control boards.

The router comprises the data transmission system, and a circuit board inside the router is used as a carrier. The other hardware configuration of the router is not particularly limited. The utility model provides a router has the relevant necessary hardware structures such as shell, antenna that general router possesses.

The embodiments described above are only a part of the embodiments of the present invention, and not all of them. The components of embodiments of the present invention, as generally described and illustrated herein and in the figures, may be arranged and designed in a wide variety of different configurations. Thus, the following detailed description of the embodiments of the present invention, presented in the accompanying drawings, is not intended to limit the scope of the invention, as claimed, but is merely representative of selected embodiments of the invention. Based on the embodiments of the present invention, all other changes or substitutions obtained by those skilled in the art without creative efforts belong to the protection scope of the present invention.

Claims (9)

1. A data transmission system is characterized by comprising a backboard, a master control board, a slave control board, a service board and an HMIM interface card, wherein a CPU chip in the master control board is in bidirectional electric connection with the backboard through a control bus, an MAC chip and a CPLD logic chip in the master control board are in bidirectional electric connection with the backboard, a CPU chip in the slave control board is in bidirectional electric connection with the backboard through a control bus, an MAC chip and a CPLD logic chip in the slave control board are in bidirectional electric connection with the backboard, the master control board and the slave control board form a double master control system, when the master control board and the slave control board are in place and powered on simultaneously, the master control board is defaulted to be in a current state, the slave control board can automatically increase delay so as to be in a standby state, a hardware signal line is arranged between the master control board and the slave control board, when the master control board is pulled out or can not normally work due to faults, the slave control board can automatically switch and manage the whole data transmission system; the service board is connected with the back board through two PCIE connectors; and meanwhile, the back plate is connected with a plurality of HMIM interface cards.

2. The data transmission system of claim 1, wherein the master control board comprises: the device comprises a CPU chip, a DDR4 memory bank, a Flash memory, a clock module, a PWR power supply, a PHY chip, an RJ45 interface, a CON interface, a USB converter, an eMMC multimedia card, an MAC chip and a CPLD logic chip; the CPU chip is electrically connected with a DDR4 memory bank, a Flash memory and a CON interface, the PHY chip is bidirectionally and electrically connected with the CPU chip, and the RJ45 interface is bidirectionally and electrically connected with the PHY chip; the USB converter is in bidirectional electric connection with the CPU chip, and the USB converter is respectively in bidirectional electric connection with a USB interface and an eMMC multimedia card; the MAC chip and the CPLD logic chip are respectively in bidirectional electrical connection with the CPU chip.

3. The data transmission system according to claim 1 or 2, wherein the slave control board comprises: the device comprises a CPU chip, a DDR4 memory bank, a Flash memory, a clock module, a PWR power supply, a PHY chip, an RJ45 interface, a CON interface, a USB converter, an eMMC multimedia card, an MAC chip and a CPLD logic chip; the CPU chip is electrically connected with a DDR4 memory bank, a Flash memory and a CON interface, the PHY chip is bidirectionally and electrically connected with the CPU chip, and the RJ45 interface is bidirectionally and electrically connected with the PHY chip; the USB converter is in bidirectional electric connection with the CPU chip, and the USB converter is respectively in bidirectional electric connection with a USB interface and an eMMC multimedia card; the MAC chip and the CPLD logic chip are respectively in bidirectional electrical connection with the CPU chip.

4. The data transmission system of claim 3, wherein the service board comprises: the device comprises a CPU chip, a DDR3 memory bank, a Flash memory, a clock module, a PCIE connector, an MAC chip, an RJ45 interface, an SFP28 interface, an SFP + interface and an SFP interface; the DDR3 memory bank and the Flash memory are electrically connected with the CPU chip; the CPU chip is in bidirectional electrical connection with the 2 PCIE connectors; the MAC chip is electrically connected with the CPU chip in a bidirectional way, and the MAC chip is electrically connected with the RJ45 interface, the SFP28 interface, the SFP + interface and the SFP interface respectively.

5. The data transmission system of claim 4, wherein said RJ45 interfaces are 16.

6. The data transmission system of claim 4, wherein the number of SFP28 interfaces is 4.

7. The data transmission system of claim 4, wherein the number of SFP + interfaces is 4.

8. The data transmission system of claim 4, wherein the number of SFP interfaces is 12.

9. A router, characterized in that it comprises at least a data transmission system according to any one of claims 1 to 8.

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