CN204650513U - Distributed structure/architecture equipment and serial port circuit thereof - Google Patents
Distributed structure/architecture equipment and serial port circuit thereof Download PDFInfo
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- CN204650513U CN204650513U CN201520243886.2U CN201520243886U CN204650513U CN 204650513 U CN204650513 U CN 204650513U CN 201520243886 U CN201520243886 U CN 201520243886U CN 204650513 U CN204650513 U CN 204650513U
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Abstract
The utility model provides a kind of distributed structure/architecture equipment and serial port circuit thereof, comprise: at least two CPU, select commutation circuit, level transferring chip and data transmitting serial port, the serial ports of each described CPU is connected with the input end of described selection commutation circuit respectively, and the output terminal of described selection commutation circuit connects described data transmitting serial port by level transferring chip; The control port of described selection commutation circuit receives the switching signal of described CPU.The serial port circuit of above-mentioned distributed structure/architecture equipment selects commutation circuit to select corresponding CPU and data transmitting serial port to form passage by utilizing, realizing multiple CPU distributed structure/architecture utilizes a number to realize data transmission according to transmitting serial port, the equipment that solves constantly converts the problem of plug Serial Port Line in debugging and application process, improves production debugging efficiency and ease for use.
Description
Technical field
The utility model relates to mechanics of communication, particularly relates to distributed structure/architecture equipment and serial port circuit thereof.
Background technology
MCP (Multi Core Platform multinuclear hardware platform) is the hardware platform in the field such as the network-oriented safety based on multi-core CPU exploitation and data acquisition.
UART (Universal Asynchronous Receiver/Transmitter, UART Universal Asynchronous Receiver Transmitter) be the functional module changed for the transmission between serial data transmission and parallel data transmission, usually convert chip with the signal amplitude of support RS-232C standard to arrange in pairs or groups, as the interface connecting external unit.
FPGA (Field-Programmable Gate Array, field programmable gate array) be at PAL (Programmable Array Logic, programmable logic array), GAL (Generic Array Logic, generic array logic), product that the basis of the programming device such as CPLD (Complex Programmable Logic Device, CPLD) further develops.It occurs as a kind of semi-custom circuit in special IC (ASIC) field, has both solved the deficiency of custom circuit, overcomes again the shortcoming that original programming device gate circuit number is limited.
SMI (Serial Management Interface, serial management bus), SMI interface comprises two signal wire: MDC (Management Data Controller) and MDIO (Management DataInput/Output, management data input and output), by SMI interface, MAC layer (Media AccessControl) chip (or other control chip) can access the register (Parasites Fauna introduced in 100M physical chip of physical chip above, but be not limited only to 100M physical chip, 10M physical chip also can have these registers), and by these registers, control and management is carried out to physical chip.
Prior art is that the mode by being separated realizes, that is: two CPU divide to open and connect separately RS232 serial port chip and RJ45 leaves the position connecing serial ports on cabinet panel.The shortcoming of prior art needs constantly to plug Serial Port Line and is unfavorable for debugging when being debugging, sacrifice service port density for needing during 1U box-shaped device high density port (48 SFP+ optical interfaces) application scenario and increase Material Cost and reduce product competitiveness.
Utility model content
The utility model object is the serial port circuit providing a kind of distributed structure/architecture equipment, solves distributed structure/architecture equipment constantly conversion plug Serial Port Line, debugging efficiency density that is low, product service port is large and Material Cost is high problem in debugging and application process if be intended to.
A kind of serial port circuit of distributed structure/architecture equipment, comprise: at least two CPU, select commutation circuit, level transferring chip and data transmitting serial port, the serial ports of each described CPU is connected with the input end of described selection commutation circuit respectively, and the output terminal of described selection commutation circuit connects described data transmitting serial port by level transferring chip; The control port of described selection commutation circuit receives the switching signal of described CPU.
Further, described selection commutation circuit comprises selector switch.
Further, described selection commutation circuit comprises CPLD controller.
Further, described selection commutation circuit comprises CPLD controller and selector switch, the input end of described selector switch is connected with the serial ports of described each described CPU respectively, export level transferring chip described in termination, control port connects described CPLD controller, and described CPLD controller connects the switching signal of described CPU.
Further, described selector switch is TS3A44159PWR chip.
Further, described level transferring chip is MAX3232 chip.
Further, described data transmitting serial port is RJ45 serial ports or BD9 serial ports.
The utility model additionally provides a kind of distributed structure/architecture equipment, comprises the serial port circuit of above-mentioned distributed structure/architecture equipment.
The serial port circuit of above-mentioned distributed structure/architecture equipment selects commutation circuit to select corresponding CPU and data transmitting serial port to form passage by utilizing, realizing multiple CPU distributed structure/architecture utilizes a number to realize data transmission according to transmitting serial port, the equipment that solves constantly converts the problem of plug Serial Port Line in debugging and application process, improves production debugging efficiency and ease for use.Reduce the density of product service port simultaneously, also save panel device arrangement areas, thus service port density can be improved, reduce the cost of product.
Accompanying drawing explanation
Fig. 1 is the structural representation of serial port circuit in the utility model preferred embodiment;
Fig. 2 is the structural representation of serial port circuit in the utility model embodiment one;
Fig. 3 is the circuit theory diagrams of the serial port circuit of the equipment of distributed structure/architecture shown in Fig. 2;
Fig. 4 is the structural representation of serial port circuit in the utility model embodiment two;
Fig. 5 is the structural representation of serial port circuit in the utility model embodiment three.
Embodiment
In order to make the technical problems to be solved in the utility model, technical scheme and beneficial effect clearly understand, below in conjunction with drawings and Examples, the utility model is further elaborated.Should be appreciated that specific embodiment described herein only in order to explain the utility model, and be not used in restriction the utility model.
Refer to Fig. 1, the serial port circuit of the distributed structure/architecture equipment in the utility model preferred embodiment in distributed structure/architecture equipment comprises at least two CPU (110 and 120), selects commutation circuit 200, level transferring chip 300 and data transmitting serial port 400, the serial ports of each described CPU is connected with the input end of described selection commutation circuit 200 respectively, and the output terminal of described selection commutation circuit 200 connects described data transmitting serial port 400 by level transferring chip 300; The control port of described selection commutation circuit 200 receives the switching signal of described CPU.
Data transmitting serial port 400 is RJ45 serial ports or BD9 serial ports.In the present embodiment, data transmitting serial port 400 is RJ45 serial ports
Embodiment one:
With reference to figure 2, commutation circuit 200 is selected to comprise selector switch 210 and CPLD controller 220, the input end of described selector switch 210 is connected with the serial ports of described each described CPU respectively, export level transferring chip 300 described in termination, control port connects described CPLD controller 220, and described CPLD controller 220 connects the switching signal of described CPU.
Composition graphs 2 and Fig. 3, in the present embodiment, described selector switch 210 is TS3A44159PWR chip.Described level transferring chip 300 is MAX3232 chip.
One CPU 110: also can work as business CPU for CPU management and use, traffic handing capacity is relatively weak.
2nd CPU 120: CPU management can be worked as business CPU simultaneously and use.
Selector switch 210 (chip TS3A44159PWR): be 2 select 1 selector switch, major function is the selection of the signal to UART (Universal Asynchronous Receiver/Transmitter, universal asynchronous receiving-transmitting transmitter).Namely being high level when a CPU 110 needs when using serial ports by the level of control port IN1-2, IN3-4 of CPLD controller 220 controlled selector 210, is low level when the 2nd CPU 120 needs to use serial ports by the level of control port IN1-2, IN3-4 of CPLD controlled selector 210.
CPLD controller 220: accessed and control port IN1-2, IN3-4 signal level of controlled selector 210 by the smi signal of a CPU 110 or the 2nd CPU 120.
Level transferring chip 300 (chip MAX3232): be UART serial port level conversion chip, due to the logic negative level that UART level adopts, and CPU employing is logic positive level.
Be defined as follows about the PHY address of modules or register address:
One CPU 110 (CPU management) PHY address is: 0b10001
2nd CPU 120 (business CPU) PHY address is: 0b10010
The serial ports that CPLD controller 220 defines switches register address: 0x0d
Embodiment two:
With reference to figure 3, described selection commutation circuit 200 is selector switch 210.The input end of selector switch 210 connects a CPU 110 respectively and is connected with the output input serial ports of the 2nd CPU 120, and the output terminal of selector switch 210 connects described data transmitting serial port 400 by level transferring chip 300; The control port of selector switch 210 receives the switching signal of a CPU 110 and the 2nd CPU 120
In the present embodiment, the rs 232 serial interface signal of CPU is connected directly to selector switch 210, controls corresponding signal export when one of them CPU needs to use serial ports by the mode writing register.
Embodiment three:
With reference to figure 4, described selection commutation circuit 200 is CPLD controller 220.The input end of CPLD controller 220 connects a CPU 110 respectively and is connected with the output input serial ports of the 2nd CPU 120, and the output terminal of CPLD controller 220 connects described data transmitting serial port 400 by level transferring chip 300; The control port of CPLD controller 220 receives the switching signal of a CPU 110 and the 2nd CPU 120
In the present embodiment, the rs 232 serial interface signal of CPU is connected directly to CPLD controller 220, controls corresponding signal export when one of them CPU needs to use serial ports by the mode writing register.
The serial port circuit of above-mentioned distributed structure/architecture equipment selects commutation circuit 200 to select corresponding CPU and data transmitting serial port 400 to form passage by utilizing, realizing multiple CPU distributed structure/architecture utilizes a number to realize data transmission according to transmitting serial port 400, the equipment that solves constantly converts the problem of plug Serial Port Line in debugging and application process, improves production debugging efficiency and ease for use.Reduce the density of product service port simultaneously, also save panel device arrangement areas, thus service port density can be improved, reduce product and reduce product Material Cost and PCB layout area.
The foregoing is only preferred embodiment of the present utility model; not in order to limit the utility model; all do within spirit of the present utility model and principle any amendment, equivalent to replace and improvement etc., all should be included within protection domain of the present utility model.
Claims (8)
1. the serial port circuit of a distributed structure/architecture equipment, it is characterized in that, comprise: at least two CPU, select commutation circuit, level transferring chip and data transmitting serial port, the serial ports of each described CPU is connected with the input end of described selection commutation circuit respectively, and the output terminal of described selection commutation circuit connects described data transmitting serial port by level transferring chip; The control port of described selection commutation circuit receives the switching signal of described CPU.
2. the serial port circuit of distributed structure/architecture equipment as claimed in claim 1, it is characterized in that, described selection commutation circuit comprises selector switch.
3. the serial port circuit of distributed structure/architecture equipment as claimed in claim 1, it is characterized in that, described selection commutation circuit comprises CPLD controller.
4. the serial port circuit of distributed structure/architecture equipment as claimed in claim 1, it is characterized in that, described selection commutation circuit comprises CPLD controller and selector switch, the input end of described selector switch is connected with the serial ports of described each described CPU respectively, export level transferring chip described in termination, control port connects described CPLD controller, and described CPLD controller connects the switching signal of described CPU.
5. the serial port circuit of the distributed structure/architecture equipment as described in claim 2 or 4, is characterized in that, described selector switch is TS3A44159PWR chip.
6. the serial port circuit of the distributed structure/architecture equipment as described in any one of Claims 1-4, is characterized in that, described level transferring chip is MAX3232 chip.
7. the serial port circuit of the distributed structure/architecture equipment as described in any one of Claims 1-4, is characterized in that, described data transmitting serial port is RJ45 serial ports or BD9 serial ports.
8. a distributed structure/architecture equipment, is characterized in that, comprises the serial port circuit of the distributed structure/architecture equipment described in any one of claim 1 to 7.
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| CN201520243886.2U CN204650513U (en) | 2015-04-21 | 2015-04-21 | Distributed structure/architecture equipment and serial port circuit thereof |
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| CN201520243886.2U CN204650513U (en) | 2015-04-21 | 2015-04-21 | Distributed structure/architecture equipment and serial port circuit thereof |
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Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105334781A (en) * | 2015-12-11 | 2016-02-17 | 天津市津达执行器有限公司 | Single chip microcomputer double-serial port structure of electric actuator |
| CN109582226A (en) * | 2018-11-14 | 2019-04-05 | 北京中电华大电子设计有限责任公司 | A kind of high speed storing access logical construction and its control method |
| CN109582620A (en) * | 2018-12-21 | 2019-04-05 | 郑州云海信息技术有限公司 | A kind of UART interface conversion equipment and interface conversion method |
| CN109597778A (en) * | 2018-11-02 | 2019-04-09 | 山东超越数控电子股份有限公司 | A kind of multi-channel serial port signal list interface duplex output system and its implementation |
| CN110262993A (en) * | 2019-06-11 | 2019-09-20 | 浙江华创视讯科技有限公司 | Input the read method and circuit, storage medium, electronic device of information |
| CN111078603A (en) * | 2019-10-30 | 2020-04-28 | 苏州浪潮智能科技有限公司 | Method and system for controlling access of internal serial port of multi-node equipment |
| CN111708726A (en) * | 2020-06-18 | 2020-09-25 | 深圳市信锐网科技术有限公司 | Port sharing method, device, equipment, system and readable storage medium |
-
2015
- 2015-04-21 CN CN201520243886.2U patent/CN204650513U/en active Active
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105334781A (en) * | 2015-12-11 | 2016-02-17 | 天津市津达执行器有限公司 | Single chip microcomputer double-serial port structure of electric actuator |
| CN109597778A (en) * | 2018-11-02 | 2019-04-09 | 山东超越数控电子股份有限公司 | A kind of multi-channel serial port signal list interface duplex output system and its implementation |
| CN109582226A (en) * | 2018-11-14 | 2019-04-05 | 北京中电华大电子设计有限责任公司 | A kind of high speed storing access logical construction and its control method |
| CN109582620A (en) * | 2018-12-21 | 2019-04-05 | 郑州云海信息技术有限公司 | A kind of UART interface conversion equipment and interface conversion method |
| CN109582620B (en) * | 2018-12-21 | 2021-11-26 | 郑州云海信息技术有限公司 | UART interface conversion device and method |
| CN110262993A (en) * | 2019-06-11 | 2019-09-20 | 浙江华创视讯科技有限公司 | Input the read method and circuit, storage medium, electronic device of information |
| CN111078603A (en) * | 2019-10-30 | 2020-04-28 | 苏州浪潮智能科技有限公司 | Method and system for controlling access of internal serial port of multi-node equipment |
| CN111078603B (en) * | 2019-10-30 | 2021-08-20 | 苏州浪潮智能科技有限公司 | Method and system for controlling access of internal serial port of multi-node equipment |
| CN111708726A (en) * | 2020-06-18 | 2020-09-25 | 深圳市信锐网科技术有限公司 | Port sharing method, device, equipment, system and readable storage medium |
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Denomination of utility model: Distributed architecture equipment and serial ports multiplex circuit thereof Effective date of registration: 20160112 Granted publication date: 20150916 Pledgee: Shenzhen SME financing Company limited by guarantee Pledgor: SEMPTIAN TECHNOLOGIES LTD. Registration number: 2016990000030 |
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Address after: 518000 Guangdong city of Shenzhen province Nanshan District Guangdong streets two Haitian Road No. 14, block 5D 8 layer software industry base Patentee after: Shenzhen Hengxin data Limited by Share Ltd Address before: 518000, Guangdong Shenzhen hi tech Southern District, Haitian two road 14, software industry base, 5D block, 7, Nanshan District Patentee before: SEMPTIAN TECHNOLOGIES LTD. |
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Denomination of utility model: Distributed architecture equipment and serial ports multiplex circuit thereof Effective date of registration: 20170214 Granted publication date: 20150916 Pledgee: Shenzhen high tech investment and financing Company limited by guarantee Pledgor: Shenzhen Hengxin data Limited by Share Ltd Registration number: 2017990000104 |
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Date of cancellation: 20180730 Granted publication date: 20150916 Pledgee: Shenzhen high tech investment and financing Company limited by guarantee Pledgor: Shenzhen Hengxin data Limited by Share Ltd Registration number: 2017990000104 |
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| PE01 | Entry into force of the registration of the contract for pledge of patent right | ||
| PE01 | Entry into force of the registration of the contract for pledge of patent right |
Denomination of utility model: Distributed architecture equipment and serial ports multiplex circuit thereof Effective date of registration: 20180730 Granted publication date: 20150916 Pledgee: Shenzhen high tech investment and financing Company limited by guarantee Pledgor: Shenzhen Hengxin data Limited by Share Ltd Registration number: 2018990000617 |
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Date of cancellation: 20190131 Granted publication date: 20150916 Pledgee: Shenzhen high tech investment and financing Company limited by guarantee Pledgor: Shenzhen Hengxin data Limited by Share Ltd Registration number: 2018990000617 |