CN2876850Y - Series parallel integrated bus system - Google Patents
Series parallel integrated bus system Download PDFInfo
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- CN2876850Y CN2876850Y CNU200620020418XU CN200620020418U CN2876850Y CN 2876850 Y CN2876850 Y CN 2876850Y CN U200620020418X U CNU200620020418X U CN U200620020418XU CN 200620020418 U CN200620020418 U CN 200620020418U CN 2876850 Y CN2876850 Y CN 2876850Y
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P90/00—Enabling technologies with a potential contribution to greenhouse gas [GHG] emissions mitigation
- Y02P90/02—Total factory control, e.g. smart factories, flexible manufacturing systems [FMS] or integrated manufacturing systems [IMS]
Abstract
The utility model discloses a series parallel integrated bus system which relates to a series parallel integrated bus system for a numerical control system and which eliminates the problem in the existing numerical control system that data switching with remote peripheral units can not work because of the adoption of parallel communication in the mainframe. The invention has an interface converter circuit (3-2) which converts the parallel interface of the main unit to a standard serial interface and the said interface converter circuit comprises a data input interface (A), a data input interface (B) and an address output interface (C). The bus system of the invention can automatically configure addresses to the slave units on the bus by the supporting of the control signal output port (ID) provided in the main unit. The series parallel integrated bus of the invention has the speed of the parallel communication mode and prolongs the transmission distance of the bus. The bus system of the invention is particularly suitable to be used in a computerized numerical control system on the basis of a personal computer, so as to allow the computerized numerical control system use the universal parallel bus extended slot in the personal computer to extend the capacity of the system to control peripheral units.
Description
Technical field
The present invention relates to a kind of string and comprehensive bus system that is applied to digital control system.
Background technology
Usually, the data communication in network is divided into two kinds of parallel communications and serial communications, wherein, parallel communications can transmit long numeric data simultaneously, communication speed is very fast, but should not carry out telecommunication, so the internal bus of computing machine adopts parallel mode to transmit data; During serial communication, data are to transmit by one one order, and the speed that serial data transmits is low, but the distance that transmits can be very long, so the exchanges data between computing machine and the peripherals mostly adopts serial communication mode.In digital control system (CNC) based on PC, because the parallel bus poor anti jamming capability of PC inside, and transmission range is limited, do not possess ability direct and remote external device communication, and the traffic rate of CNC and external unit is particularly important, so just be necessary to develop a kind of rapidity of existing parallel communications mode, can carry out the more effective bus system of long-distance transmissions again.
Summary of the invention
Because main frame adopts parallel communications and can't realize and the problem of remote external device communication, the invention provides also comprehensive bus system of a kind of string in order to solve in the existing digital control system.
String of the present invention and comprehensive bus system, comprise main equipment 1 and at least one slave unit 2 that contains parallel bus interface, described string and comprehensive bus system also comprise bus cable 3-1 and interface conversion circuit 3-2 who is used to connect described main equipment and described at least one slave unit, and described interface conversion circuit 3-2 comprises that a conversion of signals that meets Centronics interface standard Centronics that is used for described main equipment 1 output is the data output interface A that meets the serial interface standard signal, a conversion of signals that meets serial interface standard that is used for the above slave unit 2 output of bus is the Data Input Interface B that meets the Centronics interface standard Centronics signal, a conversion of signals that meets Centronics interface standard Centronics that is used for described main equipment 1 output is the address output interface C that meets the serial interface standard signal, a reference ground output terminal that provides by main equipment 1, a control signal output ends ID who provides by main equipment 1;
Two connectors that the output terminal with above-mentioned interface circuit is complementary about slave unit 2 in described string and the comprehensive bus system all is provided with, be that described left connector 2-1 is respectively arranged with a plurality of data input pins, a plurality of data output end, a plurality of address input end, reference ground end, control input end IDI, described right connector 2-2 is respectively arranged with a plurality of data input pins, a plurality of data output end, a plurality of address input end, holds and control output end IDO with reference to ground; A plurality of output terminals of the data output interface A of interface conversion circuit 3-2 on the described main equipment 1 link to each other by bus cable 3-1 with a plurality of data input pins of the left connector 2-1 of first slave unit 2, the a plurality of input ends of Data Input Interface B on the described main equipment 1 link to each other by bus cable 3-1 with a plurality of data output ends of the left connector 2-1 of first slave unit 2, address output interface C on the described main equipment 1 links to each other by bus cable 3-1 with a plurality of address input ends of the left connector 2-1 of first slave unit 2, reference ground output terminal on the described main equipment 1 links to each other by bus cable 3-1 with the reference ground end of the left connector 2-1 of first slave unit 2, control signal output ends ID on the described main equipment 1 links to each other by bus cable 3-1 with the control input end IDI of the left connector 2-1 of first slave unit 2, a plurality of data input pins of the right connector 2-2 of described first slave unit 2, a plurality of data output ends, a plurality of address input ends, with reference to ground end and control output end IDO respectively with a plurality of data input pins of the left connector 2-1 of second slave unit 2, a plurality of data output ends, a plurality of address input ends, link to each other by bus cable 3-1 with control input end IDI with reference to the ground end, a plurality of data input pins of the right connector 2-2 of second slave unit 2, a plurality of data output ends, a plurality of address input ends, with reference to ground end and control output end IDO respectively with a plurality of data input pins of the left connector 2-1 of next slave unit 2, a plurality of data output ends, a plurality of address input ends, link to each other by bus cable 3-1 with control input end IDI with reference to the ground end, the right connector 2-2 of last slave unit 2 links to each other with terminator terminating junctor; Link to each other with a plurality of data input pins of right connector 2-2, a plurality of data output end, a plurality of address input end with reference to the ground end respectively at a plurality of data input pins of a left side, the inside of each slave unit 2 connector 2-1, a plurality of data output end, a plurality of address input end with reference to the ground end.The slave unit of string and comprehensive bus is connected in series on bus.
String of the present invention and comprehensive bus system are converted to the parallel interface in the main equipment interface that meets serial interface standard.As depicted in figs. 1 and 2, data output interface A and address interface C are the circuit that is used for the parallel signal of main equipment is converted into two paths of differential signals, so the two structure is identical.The conversion of signals part of data output interface A of the present invention as shown in Figure 3 is made up of a plurality of difference channel A1, the number of difference channel A1 equals the figure place of parallel data output, and the signal of each and line output all is converted into two paths of differential signals by a difference channel A1.As Fig. 2 and shown in Figure 4; The conversion of signals part of Data Input Interface B is made up of a plurality of differential signal change-over circuit B1, the number of differential signal change-over circuit B1 equals the figure place of parallel data input, and the two paths of differential signals of each parallel input all is converted into one road parallel signal by a differential signal change-over circuit B1.
In sum, the A that the present invention links to each other with main equipment, B, three interface circuits of C, remain the parallel bus transmission, different is that the data of transmitting on bus cable are the signals with serial interface standard, therefore, string of the present invention and comprehensive bus had both had the rapidity of parallel communications mode, simultaneously owing to strengthened the driving force of bus, thereby had prolonged the transmission range of bus.By the setting of A, B, three interface circuits of C as can be seen, bus system of the present invention " master " arrived " from " output of the data of equipment, " from " to the data input of " master " equipment and " master " to " from " address of equipment exports whole separating, transmit with different cables, avoid system to carry out the lot of data analysis, saved working time.Bus system of the present invention adopts the autoconfigured address mode, so also address conflict can not take place without the hardware address deploy switch.String of the present invention and comprehensive bus are particularly useful for the digital control system (CNC) based on PC, make CNC can expand the ability of control external unit by the general parallel bus expansion slot of PC.
Description of drawings
Fig. 1 is string of the present invention and comprehensive bus system structural representation; Fig. 2 is the annexation synoptic diagram of the parallel bus interface of the interface conversion circuit 3-2 of string of the present invention and comprehensive bus and main equipment; Fig. 3 is the conversion of signals part inner structure synoptic diagram of data output interface A; Fig. 4 is the conversion of signals part inner structure synoptic diagram of Data Input Interface B; Fig. 5 is the conversion of signals partial circuit structural representation of data output interface A in the embodiment; Fig. 6 is the conversion of signals partial circuit structural representation of output interface C in address in the embodiment; Fig. 7 is the conversion of signals partial circuit structural representation of Data Input Interface B in the embodiment; Fig. 8 is the view that string of the present invention and comprehensive bus are carried out the slave unit control signal before the address disposes automatically; Fig. 9 is the view that string of the present invention and comprehensive bus are carried out the slave unit control signal after the address disposes automatically; Figure 10 is the sequential chart that string of the present invention and comprehensive bus system carry out " writing " operation; Figure 11 is the sequential chart that string of the present invention and comprehensive bus system carry out " reading " operation.
Embodiment
To shown in Figure 9, string of this embodiment and comprehensive bus system are applied in the digital control system based on PC as Fig. 1, and following main equipment 1 is an Industrial PC Computer, and it has the parallel bus expansion slot.String of this embodiment and comprehensive bus system comprise the main equipment 1 and at least one slave unit 2 that contain parallel bus interface, described string and comprehensive bus system also comprise bus cable 3-1 and interface conversion circuit 3-2 who is used to connect described main equipment and described at least one slave unit, and described interface conversion circuit 3-2 comprises that a conversion of signals that meets Centronics interface standard Centronics that is used for described main equipment 1 output is the data output interface A that meets the differential signal of serial interface standard, a Data Input Interface B who is used for the differential signal that meets serial interface standard of the above slave unit 2 output of bus is converted to the signal that meets Centronics interface standard Centronics, a conversion of signals that meets Centronics interface standard Centronics that is used for described main equipment 1 output is the address output interface C that meets the differential signal of serial interface standard, a reference ground output terminal that provides by main equipment 1, a control signal output ends ID who provides by main equipment 1; Two connectors that the output terminal with above-mentioned interface circuit is complementary about slave unit 2 in described string and the comprehensive bus system all is provided with, be that described left connector 2-1 is respectively arranged with 16 data input ends, 16 data output terminals, 16 address input ends, with reference to the ground end, control input end IDI, described right connector 2-2 is respectively arranged with 16 data input ends, 16 data output terminals, 16 address input ends, with reference to ground end and control output end IDO, 16 output terminals of the data output interface A of interface conversion circuit 3-2 on the described main equipment 1 link to each other by bus cable 3-1 with 16 data input ends of the left connector 2-1 of first slave unit 2,16 input ends of Data Input Interface B on the described main equipment 1 link to each other by bus cable 3-1 with 16 data output terminals of the left connector 2-1 of first slave unit 2, address output interface C on the described main equipment 1 links to each other by bus cable 3-1 with 16 address input ends of the left connector 2-1 of first slave unit 2, reference ground output terminal on the described main equipment 1 links to each other by bus cable 3-1 with the reference ground end of the left connector 2-1 of first slave unit 2, control signal output ends ID on the described main equipment 1 links to each other by bus cable 3-1 with the control input end IDI of the left connector 2-1 of first slave unit 2,16 data input ends of the right connector 2-2 of described first slave unit 2,16 data output terminals, 16 address input ends, with reference to ground end and control output end IDO respectively with 16 data input ends of the left connector 2-1 of second slave unit 2,16 data output terminals, 16 address input ends, link to each other by bus cable 3-1 with control input end IDI with reference to the ground end, 16 data input ends of the right connector 2-2 of second slave unit 2,16 data output terminals, 16 address input ends, with reference to ground end and control output end IDO respectively with 16 data input ends of the left connector 2-1 of next slave unit 2,16 data output terminals, 16 address input ends, link to each other by bus cable 3-1 with control input end IDI with reference to the ground end, the right connector 2-2 of last slave unit 2 links to each other with terminator terminating junctor, terminator terminating junctor is used for the restricting signal reflection, at 16 data input ends of the left side, inside of each slave unit 2 connector 2-1,16 data output terminals, 16 address input ends and with reference to the ground end respectively with 16 data input ends of right connector 2-2,16 data output terminals, 16 address input ends link to each other with holding with reference to ground.
Main equipment adopts the mode of eight bit parallels communication in string of this embodiment and the comprehensive bus system.Above-mentioned data output interface A is identical with the structure of address output interface C.As shown in Figure 3, the conversion of signals of data output interface A part is made up of eight difference channel A1, and the signal of each and line output all is converted into two paths of differential signals+DIFF and-DIFF by a difference channel A1.As shown in Figure 5 and Figure 6, it is first chip IC, 1 formation of AM26LS31 that eight difference channel A1 adopt two models, in data output interface A, IOA (0～7) the eight bit parallel TTL signals that are used for data output of main equipment output respectively by two first chip IC 1 be converted into the two-way parallel transmission the balanced differential signal+DIFFA (0～7) that meets the RS-422 interface standard and-DIFFA (0～7); In the output interface C of address, the IOC that is used for address transfer (0～7) the eight bit parallel signals of main equipment 1 output respectively by two first chip IC I be converted into the two-way parallel transmission the balanced differential signal+DIFFC (0～7) that meets the RS-422 interface standard and-DIFFC (0～7).As shown in Figure 4, the conversion of signals of Data Input Interface B part is made up of eight differential signal change-over circuit B1, and each road differential signal+DIFF and-DIFF are converted into one road signal by a differential signal change-over circuit B1.As shown in Figure 7, it is second chip IC, 2 formations of AM26LS32 that eight differential signal change-over circuit B1 adopt two models, differential signal+the DIFFB (0～7) of the parallel transmission of slave unit output and-DIFFB (0～7) is converted into the eight bit parallel signal IOB (0～7) that can be read by main equipment by two second chip IC 2 respectively, 1,7,9,15 pin of two second chip IC 2 pass through one first resistance R 1 respectively and link to each other with the output terminal of direct supply VCC.In sum, above-mentioned interface conversion circuit 3-2 has 50 output terminals.
The slave unit of string of this embodiment and comprehensive bus is connected in series on bus, and its data transferring method carries out according to the following steps:
As Fig. 8 and shown in Figure 9, autoconfigured address at first: after system powers on, each slave unit 2 on the bus all has a default address, main equipment 1 sends the control input end IDI that control signal is transferred to first slave unit 2 left connector 2-1 by control signal output ends ID, thereby activate first slave unit 2, according to the type of first slave unit 2, main equipment 1 carries out address configuration to first slave unit 2 again; After first slave unit 2 address configuration are finished, first slave unit 2 can send the control input end IDI that a control signal is transferred to the left connector 2-1 of second slave unit 2 by the control output end IDO of right connector 2-2, thereby activate second slave unit 2, main equipment 1 carries out address configuration to second slave unit 2 again according to the type of second slave unit 2; After second slave unit 2 address configuration finished, second slave unit 2 can send the control input end IDI that a control signal is transferred to the left connector 2-1 of next slave unit 2 by the control output end IDO of right connector 2-2, thereby activate next slave unit 2, and it is carried out address configuration, all finish address configuration up to all slave units 2, as shown in Figure 9;
As shown in figure 10, described bus system is when carrying out " writing " operation, address output interface C is provided with an initial address " 0 ", main equipment 1 at first sends to data data output interface A, the address of main equipment 1 slave unit 2 that will communicate with main equipment 1 again sends to address output interface C then, effective through address behind data T2 transit time, again after the time-delay of the maximum cycle T1 that transmits through computational data, main equipment 1 is sent to address output interface C with initial address " 0 " again, so just finished a data write cycle;
As shown in figure 11, described bus system is when carrying out " reading " operation, address output interface C begins also to be arranged on initial address " 0 ", main equipment 1 at first sends to address output interface C with the address of slave unit 2, effective through address behind data T2 transit time, this address information will make and will learn with the slave unit that main equipment communicates then, and the data that this slave unit 2 will transmit are sent on the bus, and the cable of several data input usefulness by bus sends Data Input Interface B to, after main equipment 1 has read data, again initial address " 0 " is sent to address output interface C, so just finished a read operation cycle.
The string of present embodiment and comprehensive bus system are from main equipment 1 eight address wires of having come out, addressing range is 0～FF, wherein address 0 is as " free time " state address of acquiescence, keep as the idle condition between two bus address signals, address 1 and 2 general addresses as bus, everybody definition and purposes sees table 1 in this bus general-purpose register.
The purposes of table 1 bus general-purpose register
| Bus | Item | Purposes | |
| 1 | 7 | The all devices plot that initialization string and | |
| 6～3 | Reserve, can not be set to " 1 " in these positions. | ||
| 2 | The overtime sign of the house dog that resets 0-- | ||
| 1 | The house dog counter is set to | ||
| 0 | The house dog counter is set to | ||
| 2 | 0～7 | Reserve, the position in can not this byte is set to " 1 ". |
The string of present embodiment and comprehensive bus are divided into 32 logic areas with address 3 and address afterwards, each logic area can corresponding slave unit, make a string and comprehensive bus system can connect 32 slave units at most, bus carry out the address when disposing automatically according to the form below 2 distribute the plot of each slave unit.
The address configuration of slave unit on table 2 string and the comprehensive bus
| Bus address | Device number | Bus address | Device number | Bus address | Device number | Bus address | Device number |
| 03～07 | 1 | 40～47 | 9 | 80～87 | 17 | C0～C7 | 25 |
| 08～0F | 2 | 48～4F | 10 | 88～8F | 18 | C8～CF | 26 |
| 10～17 | 3 | 50～57 | 11 | 90～97 | 19 | D0～D7 | 27 |
| 18～ | 4 | 58～5F | 12 | 98～9F | 20 | D8～DF | 28 |
| 20～27 | 5 | 60～67 | 13 | A0～A7 | 21 | E0～E7 | 29 |
| 28～ | 6 | 68～6F | 14 | A8～AF | 22 | E8～EF | 30 |
| 30～37 | 7 | 70～77 | 15 | B0～B7 | 23 | F0～F7 | 31 |
| 38～3F | 8 | 78～7F | 16 | B8～BF | 24 | F8～FF | 32 |
As can be seen from the above table, the addressing range of first slave unit 2 is 5 bytes, and the addressing range of other 31 slave units is 8 bytes, and the definition and the function of these 8 bytes see table 3, and the meaning of 5 bytes of first slave unit 2 also sees table 3.
The address byte definition of each slave unit of table 3
For most of slave units, the addressing range of 8 bytes is not enough, and therefore, string and comprehensive bus have also adopted modifier register to come the addressing range of expansion bus.As shown in table 3, each equipment all has 3 bytes to be used for modifier register is operated, and one of them byte is used to control the write operation to modifier register, and another byte control read operation also has a byte as general-purpose register.Each modifier register can 256 bytes of addressing, and the function of modifier register and definition are referring to table 4.Bus can increase addressing range to slave unit by modifier register.
Table 4
| The modifier | Meaning | |
| 7～256 | The function of self-defining | |
| 6～5 | Keep | |
| 4 | Read or write the | |
| 3 | | |
| 2 | Read | |
| 1 | | |
| 0 | Read states |
Claims (3)
1, a kind of string and comprehensive bus system, described string and comprehensive bus system comprise the main equipment (1) and at least one slave unit (2) that contain parallel bus interface, it is characterized in that described string and comprehensive bus system also comprise a bus cable (3-1) and an interface conversion circuit (3-2) that is used to connect described main equipment and described at least one slave unit, described interface conversion circuit (3-2) comprises that a Centronics interface standard Centronics conversion of signals that meets that is used for described main equipment (1) output is the data output interface (A) that meets the differential signal of serial interface standard, one is used for the differential signal that meets serial interface standard of the above slave unit of bus (2) output is converted to the Data Input Interface (B) that meets the Centronics interface standard Centronics signal, a conversion of signals that meets Centronics interface standard Centronics that is used for described main equipment (1) output is the address output interface (C) that meets the serial interface standard signal, a reference ground output terminal that provides by main equipment (1), a control signal output ends (ID) that provides by main equipment (1);
Two connectors that the output terminal with above-mentioned interface circuit is complementary about slave unit in described string and the comprehensive bus system (2) all is provided with, be that described left connector (2-1) is respectively arranged with a plurality of data input pins, a plurality of data output ends, a plurality of address input ends, with reference to the ground end, control input end (IDI), described right connector (2-2) is respectively arranged with a plurality of data input pins, a plurality of data output ends, a plurality of address input ends, with reference to ground end and control output end (IDO), a plurality of output terminals of the data output interface (A) of the interface conversion circuit (3-2) on the described main equipment (1) link to each other by bus cable (3-1) with a plurality of data input pins of the left connector (2-1) of first slave unit (2), a plurality of input ends of the Data Input Interface (B) on the described main equipment (1) link to each other by bus cable (3-1) with a plurality of data output ends of the left connector (2-1) of first slave unit (2), address output interface (C) on the described main equipment (1) links to each other by bus cable (3-1) with a plurality of address input ends of the left connector (2-1) of first slave unit (2), reference ground output terminal on the described main equipment (1) links to each other by bus cable (3-1) with the reference ground end of the left connector (2-1) of first slave unit (2), output terminal (ID) on the described main equipment (1) links to each other by bus cable (3-1) with the control input end (IDI) of the left connector (2-1) of first slave unit (2), a plurality of data input pins of the right connector (2-2) of described first slave unit (2), a plurality of data output ends, a plurality of address input ends, with reference to ground end and control output end (IDO) respectively with a plurality of data input pins of the left connector (2-1) of second slave unit (2), a plurality of data output ends, a plurality of address input ends, link to each other by bus cable (3-1) with control input end (IDI) with reference to the ground end, a plurality of data input pins of the right connector (2-2) of second slave unit (2), a plurality of data output ends, a plurality of address input ends, with reference to ground end and control output end (IDO) respectively with a plurality of data input pins of the left connector (2-1) of next slave unit (2), a plurality of data output ends, a plurality of address input ends, link to each other by bus cable (3-1) with control input end (IDI) with reference to the ground end, the right connector (2-2) of last slave unit (2) links to each other with terminator terminating junctor, at a plurality of data input pins of the inside of each slave unit (2) left side connector (2-1), a plurality of data output ends, a plurality of address input ends and with reference to ground end respectively with a plurality of data input pins of right connector (2-2), a plurality of data output ends, a plurality of address input ends link to each other with holding with reference to ground.
2, a kind of string according to claim 1 and comprehensive bus system, the conversion of signals part that it is characterized in that described data output interface (A) is made up of a plurality of difference channels (A1), the number of difference channel (A1) equals the figure place of parallel data output, and the signal of each and line output all is converted into two paths of differential signals by a difference channel (A1); The conversion of signals partial circuit structure of data output interface (A) and address output interface (C) is identical.
3, a kind of string according to claim 1 and comprehensive bus system, the conversion of signals part that it is characterized in that described Data Input Interface (B) is made up of a plurality of differential signal change-over circuits (B1), the number of differential signal change-over circuit (B1) equals the figure place of parallel data input, and the two paths of differential signals of each parallel input all is converted into one road parallel signal by a differential signal change-over circuit (B1).
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| CNU200620020418XU CN2876850Y (en) | 2006-03-20 | 2006-03-20 | Series parallel integrated bus system |
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| CNU200620020418XU CN2876850Y (en) | 2006-03-20 | 2006-03-20 | Series parallel integrated bus system |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100363915C (en) * | 2006-03-20 | 2008-01-23 | 哈尔滨工业大学 | Parallel and serial comprehensive bus system and data transmitting method |
| CN102255978A (en) * | 2010-05-20 | 2011-11-23 | 凹凸电子（武汉）有限公司 | Address configuration device, method and system |
| CN102615647A (en) * | 2012-04-09 | 2012-08-01 | 邓世海 | Multi-axis movement control method of industrial robot |
| US8525477B2 (en) | 2010-07-15 | 2013-09-03 | O2Micro, Inc. | Assigning addresses to multiple cascade battery modules in electric or electric hybrid vehicles |
-
2006
- 2006-03-20 CN CNU200620020418XU patent/CN2876850Y/en not_active Expired - Fee Related
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100363915C (en) * | 2006-03-20 | 2008-01-23 | 哈尔滨工业大学 | Parallel and serial comprehensive bus system and data transmitting method |
| CN102255978A (en) * | 2010-05-20 | 2011-11-23 | 凹凸电子（武汉）有限公司 | Address configuration device, method and system |
| CN102255978B (en) * | 2010-05-20 | 2014-08-13 | 凹凸电子（武汉）有限公司 | Address configuration device, method and system |
| US8525477B2 (en) | 2010-07-15 | 2013-09-03 | O2Micro, Inc. | Assigning addresses to multiple cascade battery modules in electric or electric hybrid vehicles |
| CN102615647A (en) * | 2012-04-09 | 2012-08-01 | 邓世海 | Multi-axis movement control method of industrial robot |
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