CN107645638B - Video processor and backplane communication method - Google Patents
Video processor and backplane communication method Download PDFInfo
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- CN107645638B CN107645638B CN201710866792.4A CN201710866792A CN107645638B CN 107645638 B CN107645638 B CN 107645638B CN 201710866792 A CN201710866792 A CN 201710866792A CN 107645638 B CN107645638 B CN 107645638B
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Abstract
The embodiment of the invention discloses a kind of video processors, comprising: video input processing unit, video output processing apparatus, master control set and back board device；Wherein, the back board device includes: matrix switch module, video input processing unit connector, video output processing apparatus connector, master control set connector, expanding unit connector and programmable logic device；The programmable logic device connects the master control set connector and connects the video input processing unit connector with the expanding unit connector and by the first ethernet PHY transceiver group and connect the video output processing apparatus connector by the second ethernet PHY transceiver group.The invention also discloses a kind of backplane communication methods.The present invention can be improved traffic rate and realize point-to-point communication.
Description
Technical field
The present invention relates to video display technology field more particularly to a kind of video processor and a kind of backplane communication sides
Method.
Background technique
In video display technology field, when the boards such as input, output, control are interacted by backboard, this is just needed
Certain communication mode is designed on backboard to realize.Backplane communication mode more general at present, generallys use matrix switch core
Piece+ARM or MCU is generally basede on the agreements such as RS485, SPI, I2C and is transmitted, using a pair of of multi-communication mode.Control card hair
Broadcasting instructions out, by each subcard (input card, output board card) according to address choice, by data feedback to bus, then by controlling
Making sheet card wheel, which is followed, to access, and often traffic rate is lower for these communication means, this is greatly lowered the performance of product.
Summary of the invention
The embodiment of the present invention provides a kind of video processor and a kind of backplane communication method, and traffic rate can be improved
And realize point-to-point communication.
On the one hand, a kind of video processor is provided, comprising: video input processing unit, video output processing apparatus, master
Control device and back board device；Wherein, the back board device includes: matrix switch module, video input processing unit connector, view
Frequency output processing apparatus connector, master control set connector, expanding unit connector and programmable logic device；The matrix is handed over
Mold changing block is connected between the video input processing unit connector and the video output processing apparatus connector, the square
Battle array Switching Module is also connected with the master control set connector and the expanding unit connector；The programmable logic device connection
The master control set connector and the expanding unit connector and described in being connected by the first ethernet PHY transceiver group
Video input processing unit connector and video output processing dress is connected by the second ethernet PHY transceiver group
Set connector；The master control set includes: microcontroller, first interface circuit and second interface circuit；The first interface electricity
Road connects the microcontroller and the communication interface including being adapted to host computer, micro-control described in the second interface circuit connection
The connector of device processed and the master control set connector including connecting the back board device.
In one embodiment of the invention, the video input processing unit connector, video output processing dress
It sets connector and passes through serializer/deserializers bus respectively with the expanding unit connector and connect the matrix switch module.
In one embodiment of the invention, the master control set connector passes through universal serial bus and the matrix switch mould
Block connection, the programmable logic device connect the master control set connector by FMC bus or FSMC bus and pass through
Third ethernet PHY transceiver group is connect with the expanding unit connector.
In one embodiment of the invention, the first ethernet PHY transceiver group and the second Ethernet object
Managing layer transceiver group includes 100 m ethernet physical layer transceiver or gigabit Ethernet physical layer transceiver.
On the other hand, a kind of backplane communication method is additionally provided, the backplane communication method is suitable for foregoing view
Frequency processor and to include: the back board device receive via the master control set connector from the master control set described the
The data of two interface circuits；Data described in the master control set connection port transmission are patrolled to described may be programmed on the back board device
Collect device；The programmable logic device passes through the first ethernet PHY transceiver group and the second Ethernet physics
Layer transceiver group is in a manner of point-to-point communication by the data via the video input processing unit connector and the video
Output processing apparatus connector is sent to the video input processing unit and the video output processing apparatus.
In one embodiment of the invention, the backplane communication method further include: the back board device is via the master
Control the switching command that device connector receives the second interface circuit from the master control set；The master control set connection
Switching command described in port transmission is to the matrix switch module on the back board device；The matrix on the back board device
Switching Module switches between the video input processing unit and the video output processing apparatus according to the switching command
Data exchange relationship.
In one embodiment of the invention, the backplane communication method further include: make the back board device by with institute
State expanding unit connector connection expanding unit and another video processor formed cascade, with at another described video
It manages device and carries out data interaction.
In one embodiment of the invention, the first ethernet PHY transceiver group and the second Ethernet object
Managing layer transceiver group includes 100 m ethernet physical layer transceiver or gigabit Ethernet physical layer transceiver.
In another aspect, additionally providing a kind of video matrix processor, comprising: at video input processing unit, video output
Manage device, master control set, expanding unit, matrix switch module and programmable logic device；The matrix switch module connects institute
State video input processing unit, the video output processing apparatus and the expanding unit；The programmable logic device connection
The expanding unit simultaneously connects the video input processing unit by the first ethernet PHY transceiver group and by the
Two ethernet PHY transceiver groups connect the video output processing apparatus；The master control set includes: microcontroller, first
Interface circuit and second interface circuit；Microcontroller described in the first interface circuit connection and including being adapted to host computer
Communication interface, microcontroller, the matrix switch module and the programmable logic device described in the second interface circuit connection
Part.
In one embodiment of the invention, the second interface circuit of the master control set passes through universal serial bus and institute
The connection of matrix switch module is stated, the programmable logic device is connect by described second that FSMC bus connects the master control set
It mouthful circuit and is connect by third ethernet PHY transceiver group with the expanding unit.
Above-mentioned technical proposal can have following one or more advantages: back board device is by the inclusion of microcontroller, first
The master control set of interface circuit and second interface circuit by data distributing to programmable logic device, again by programmable logic device
Each video input processing unit and video output are connected by the ethernet PHY transceiver of 100,000,000 or gigabit transmission rate
Processing unit, so that realization and the point-to-point high speed between each video input processing unit and video output processing apparatus are led to
Letter, reaches the high efficiency of transmission of data.In addition, can realize more views by expanding unit by setting expanding unit connector
Cascade between frequency processor.
Detailed description of the invention
In order to illustrate the technical solution of the embodiments of the present invention more clearly, required use in being described below to embodiment
Attached drawing be briefly described, it should be apparent that, drawings in the following description are only some embodiments of the invention, for this
For the those of ordinary skill of field, without creative efforts, it can also be obtained according to these attached drawings others
Attached drawing.
Figure 1A is a kind of structural schematic diagram of the back board device of video processor of first embodiment of the invention；
Figure 1B is a kind of structural schematic diagram of the master control set of video processor of first embodiment of the invention；
Fig. 2 is a kind of flow diagram of backplane communication method of second embodiment of the invention；
Fig. 3 is a kind of structural schematic diagram of video processor of third embodiment of the invention.
Specific embodiment
Following will be combined with the drawings in the embodiments of the present invention, and technical solution in the embodiment of the present invention carries out clear, complete
Site preparation description, it is clear that described embodiments are only a part of the embodiments of the present invention, instead of all the embodiments.It is based on
Embodiment in the present invention, it is obtained by those of ordinary skill in the art without making creative efforts every other
Embodiment shall fall within the protection scope of the present invention.
First embodiment
As shown in Figure 1A, a kind of video processor that first embodiment of the invention provides specifically includes that video input is handled
Device 121, video output processing apparatus 131, master control set 141 and back board device 10；Wherein, back board device 10 includes: matrix
Switching Module 11, video input processing unit connector 12, video output processing apparatus connector 13, master control set connector
14, expanding unit connector 15 and programmable logic device 16；Matrix switch module 11 is connected to video input processing unit company
Between interface 12 and video output processing apparatus connector 13, matrix switch module 11 is also connected with master control set connector 14 and expands
Extending apparatus connector 15；Programmable logic device 16 connects master control set connector 14 and expanding unit connector 15 and passes through
First ethernet PHY transceiver group 17 connects video input processing unit connector 12 and passes through the second Ethernet physics
Layer transceiver group 18 connects video output processing apparatus connector 13.Matrix switch module 11 is for example including high speed matrix switch core
Piece is as CrossPoint Switch chip etc.；Video input processing unit connector 12, can be with for example including multi-wad join notch
Connection is all the way or multi-channel video input processing device 121；Video output processing apparatus connector 13 is for example including multi-wad join
Notch can connect all the way or multi-channel video output processing apparatus 131；Video input processing unit connector 12, video are defeated
Processing unit connector 13 and expanding unit connector 15 are for example contour by serializer/deserializers bus (SERDES) respectively out
Fast universal serial bus connection matrix Switching Module 11；Programmable logic device 16 is, for example, FPGA (Field Programmable
Gate Array, field programmable gate array) etc..
Specifically, master control set 141 is for example connected by master control set connector 14 with back board device 10, and master control set connects
Interface 14 is connect by universal serial bus such as SPI with matrix switch module 11, and programmable logic device 16 for example passes through variable storage
Controller (Flexible Memory Controller, FMC) bus or variable static storage controller (Flexible
Static Memory Controller, FSMC) bus connection master control set connector 14 and pass through third Ethernet physics
Layer transceiver group 19 is connect with expanding unit connector 15.
Specifically, the first ethernet PHY transceiver group 17 is for example including multichannel ethernet PHY transceiver 171, from
And it can connect multi-channel video input processing device connector 12；Second ethernet PHY transceiver group 18 is for example including multichannel
Ethernet PHY transceiver 181, so as to connect multi-channel video output processing apparatus connector 13；Ethernet physical layer is received
It sends out device 171 and ethernet PHY transceiver 181 is, for example, 100 m ethernet physical layer transceiver or gigabit Ethernet physical layer
Transceiver (when using 100 m ethernet physical layer transceiver, traffic rate 100Mbps；When using gigabit Ethernet physics
When layer transceiver, traffic rate 1000Mbps)；Extension of the back board device 10 for example by being connect with expanding unit connector 15
Device and another video processor, which are formed, to be cascaded.
Specifically, master control set 141 is specifically included that for example, by using master control set 20 as shown in Figure 1B, master control set 20
Circuit board 21, and the microcontroller 22, first interface circuit 23 and the second interface circuit 24 that are arranged on circuit board 21.First
Interface circuit 23 connects microcontroller 22 and is provided with the communication interface 231 for being adapted to host computer such as computer, and second connects
Mouth circuit 24 connects microcontroller 23 and is provided with the connector 241 for being adapted to back board device 10.Wherein, connector 241
For example FCI interface, microcontroller chip of the microcontroller 22 for example including model STM32F4 series, 22 conduct of microcontroller
The main logic unit of master control set 20.
Specifically, communication interface 231 is for example including serial ports such as RS232 interface (asynchronous transmission standard interface) 1311, USB
Interface (Universal Serial Bus Interface) 2313 and RJ45 (Registered Jack 45) interface (or network interface) 2315, master control dress
It sets 20 and is interconnected host computer and the microcontroller 22 in master control set 20 by providing these interfaces, so as to pass through host computer
It is interacted with master control set 20.
Further, first interface circuit 23 is for example further include: transceiver module 233 is connected to microcontroller 22 and logical
Between communication interface 231；Transceiver module 233 is for example including serial ports transceiver 2331, USB transceiver 2333 and ethernet physical layer
Transceiver 2335, certainly in certain embodiments, transceiver module 233 be also possible to include three select one or secondly.Wherein,
Serial ports transceiver 2331 is for example including RS232 serial ports transponder chip, and ethernet PHY transceiver 2335 is for example including 100,000,000
(100M) ethernet PHY chip.More specifically, 2315 three of aforementioned RS232 interface 2311, USB interface 2313 and RJ45 interface
Such as respectively with the serial ports transceiver 2331 of transceiver module 233, USB transceiver 2333 and ethernet PHY transceiver 2335
It is connected.
Further, second interface circuit 24 is for example further include: data bus module 243 is connected to 22 He of microcontroller
Between connector 241；Data bus module 243 for example, FMC/FSMC (Flexible Memory Controller/
Flexible Static Memory Controller can be changed storage control/variable static storage controller) bus 2431,
I2C bus 2433 and spi bus 2435.More specifically, FMC/FSMC bus 2431, I2C_(Inter-Integrated
Circuit) bus 2433 and SPI (Serial Peripheral Interface, Serial Peripheral Interface (SPI)) bus 2435 are for example divided
It is not connected between microcontroller 22 and connector 241, so that master control set 20 can be with back board device 10 by connector 241
Realize connection and data transmission.
Further, master control set 20 is for example further include: memory module 25 connects microcontroller 22.Memory module
25 preferably include eMMC (Embedded Multi Media Card, embedded multi-media card) memory 251 and flash memory
(Flash)253.Wherein, eMMC memory 251 and flash memory 253 store the caching function with program for realizing data.
Further, master control set 20 is for example further include: USB flash disk driver 26 and USB interface 27, USB interface 27 pass through USB flash disk
Driver 26 is connected to microcontroller 22.Wherein, master control set 20 for example connects peripheral hardware such as USB flash disk by USB interface 27, realizes
Save the functions such as off-line files and upgraded in offline.
Further, master control set 20 is for example further include: wireless communication module 28.Wireless communication module 28 for example,
WIFI (Wireless Fidelity) module 281 and antennal interface 283；Antennal interface 283 is connected micro- by WIFI module 281
Controller 22.Wherein, for example external WIFI antenna of antennal interface 283, so as to allow other mobile devices to be connected to master control dress
20 are set, realizes the wireless communication between master control set 20 and other mobile devices.
Further, master control set 20 is for example further include: RTC (Real Time Clock, real-time clock) module 29, even
Connect microcontroller 22.Wherein, RTC block 29 is, for example, that master control set 20 provides real-time clock.
In conclusion including microcontroller 22, first interface circuit 23 and second interface electricity in first embodiment of the invention
The master control set 20 on road 24 is connected by the master control set connector 14 being connected with programmable logic device 16, so as to count
According to being handed down to programmable logic device 16；Connected again by programmable logic device 16 by the first ethernet PHY transceiver group 17
It connects video input processing unit connector 12 and video output processing is connected by the second ethernet PHY transceiver group 18
Device connector 13, thus realization and the point pair between each video input processing unit 121 and video output processing apparatus 131
Point high-speed communication, reaches the high efficiency of transmission of data；In addition, by setting expanding unit connector 15, it can be by being filled with extension
It sets the connected expanding unit of connector 15 and realizes cascade between more video processors.Realize the high efficiency of transmission of data.
Second embodiment
As shown in Fig. 2, for a kind of backplane communication method that second embodiment of the invention provides, the backplane communication method is suitable
For the video processor of such as aforementioned first embodiment, the concrete function detail with reference of the video processor aforementioned first is real
The description in example is applied, details are not described herein；The backplane communication method it is main comprising steps of
S11: back board device 10 receives the second interface circuit 24 from master control set 141 via master control set connector 14
Data；
S13: master control set connector 14 transmits the data to the programmable logic device 16 on back board device 10；
S15: programmable logic device 16 passes through the first ethernet PHY transceiver group 17 and the second ethernet physical layer
Transceiver group 18 in a manner of point-to-point communication by the data via video input processing unit connector 12 and video output at
Reason device connector 13 is sent to video input processing unit 121 and video output processing apparatus 131.
Further, backplane communication method further include: back board device 10 receives to come independently via master control set connector 14
Control the switching command of the second interface circuit 24 of device 141；Master control set connector 14 transmits the switching command and fills to backboard
Set the matrix switch module 11 on 10；Matrix switch module 11 on back board device 10 is defeated according to the switching command Switch Video
Enter the data exchange relationship between processing unit 121 and video output processing apparatus 131.
Further, backplane communication method further include: make back board device 10 by connecting with expanding unit connector 15
Expanding unit and another video processor, which are formed, to be cascaded, to carry out data interaction with another described video processor.
In conclusion second embodiment of the invention dorsulum device 10 is by the inclusion of microcontroller 22, first interface circuit
23 and second interface circuit 24 master control set 20 by data distributing to programmable logic device 16, by programmable logic device 16
Each video input processing unit is connected by the ethernet PHY transceiver 171 and 181 of 100,000,000 or gigabit transmission rate again
121 and video output processing apparatus 131, to realize and each video input processing unit 121 and video output processing apparatus
Point-to-point high-speed communication between 131, reaches the high efficiency of transmission of data；Pass through matrix switch module 11 on back board device 10
According to the data exchange relationship between the switching command Switch Video input processing device 121 and video output processing apparatus 131；
In addition, can realize the cascade between more video processors by expanding unit by setting expanding unit connector 15.
3rd embodiment
As shown in figure 3, a kind of video processor 30 provided for third embodiment of the invention, comprising: video input processing
Device 32, video output processing apparatus 33, master control set 34, expanding unit 35, matrix switch module 31 and programmable logic device
Part 36；Matrix switch module 31 connects video input processing unit 32, video output processing apparatus 33 and expanding unit 35；It can compile
Journey logical device 36 connects expanding unit 35 and connects video input processing dress by the first ethernet PHY transceiver group 37
It sets 32 and video output processing apparatus 33 is connected by the second ethernet PHY transceiver group 38.Matrix switch module 31
It such as include high speed matrix switch chip as CrossPoint Switch chip；Video input processing unit 32 is for example including more
A video input processing unit 321；Video output processing apparatus 33 is for example including multiple video output processing apparatus 331；Video
Input processing device 32, video output processing apparatus 33 and expanding unit 35 for example pass through serializer/deserializers bus respectively
(SERDES) the high-speed serial bus connection matrix Switching Module 31 such as；Programmable logic device 36 is, for example, FPGA (Field
Programmable Gate Array, field programmable gate array) etc..
Specifically, master control set 34 for example, by using the master control set 20 of aforementioned first embodiment, ask by concrete function details
With reference to the description in aforementioned first embodiment, details are not described herein；
Specifically, the second interface circuit 24 of master control set 20 is connected by the universal serial bus such as SPI and matrix switch module 31
It connects, programmable logic device 36 connects the second interface circuit 24 of master control set 20 by FMC bus or FSMC bus and leads to
Third ethernet PHY transceiver group 39 is crossed to connect with expanding unit 35.First ethernet PHY transceiver group 37 is for example wrapped
Multichannel ethernet PHY transceiver 371 is included, so as to connect multiple video input processing units 321；Second Ethernet object
Layer transceiver group 38 is managed for example including multichannel ethernet PHY transceiver 381, so as to connect multiple video output processing
Device 331；Ethernet PHY transceiver 371 and ethernet PHY transceiver 381 are, for example, that 100 m ethernet physical layer is received
(when using 100 m ethernet physical layer transceiver, traffic rate is for hair device or gigabit Ethernet physical layer transceiver
100Mbps；When using gigabit Ethernet physical layer transceiver, traffic rate 1000Mbps).
In conclusion including microcontroller 22, first interface circuit 23 and second interface electricity in third embodiment of the invention
The master control set 34 on road 24 by being connected with programmable logic device 36, so as to by data distributing to programmable logic device
36；Again by programmable logic device 36 by the first ethernet PHY transceiver group 37 connect video input processing unit 32 with
And video output processing apparatus 33 is connected by the second ethernet PHY transceiver group 38, to realize and each video input
Point-to-point high-speed communication between processing unit 321 and video output processing apparatus 331, reaches the high efficiency of transmission of data；In addition,
By the way that expanding unit 35 is arranged, the cascade between more video processors can be realized by expanding unit 35.
In several embodiments provided herein, it should be understood that disclosed system, device and method can be with
It realizes by another way.For example, the apparatus embodiments described above are merely exemplary, for example, the unit
It divides, only a kind of logical function partition, there may be another division manner in actual implementation, such as multichannel unit or component
It can be combined or can be integrated into another system, or some features can be ignored or not executed.Another point, it is shown or
The mutual coupling, direct-coupling or communication connection discussed can be through some interfaces, the indirect coupling of device or unit
It closes or communicates to connect, can be electrical property, mechanical or other forms.
The unit as illustrated by the separation member may or may not be physically separated, aobvious as unit
The component shown may or may not be physical unit, it can and it is in one place, or may be distributed over multichannel
In network unit.It can select some or all of unit therein according to the actual needs to realize the mesh of this embodiment scheme
's.
Finally, it should be noted that the above embodiments are merely illustrative of the technical solutions of the present invention, rather than its limitations；Although
Present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that: it still may be used
To modify the technical solutions described in the foregoing embodiments or equivalent replacement of some of the technical features；
And these are modified or replaceed, technical solution of various embodiments of the present invention that it does not separate the essence of the corresponding technical solution spirit and
Range.
Claims (10)
1. a kind of video processor characterized by comprising video input processing unit, video output processing apparatus, master control dress
It sets and back board device；
Wherein, the back board device includes: matrix switch module, video input processing unit connector, video output processing dress
Set connector, master control set connector, expanding unit connector and programmable logic device；The matrix switch module is connected to
Between the video input processing unit connector and the video output processing apparatus connector, the matrix switch module is also
Connect the master control set connector and the expanding unit connector；The programmable logic device connects the master control set
Connector connects the video input processing with the expanding unit connector and by the first ethernet PHY transceiver group
Device connector and the video output processing apparatus connector is connected by the second ethernet PHY transceiver group；
The master control set includes: microcontroller, first interface circuit and second interface circuit；The first interface circuit connection
The microcontroller and the communication interface including being adapted to host computer, microcontroller described in the second interface circuit connection is simultaneously
Connector including connecting the master control set connector of the back board device.
2. video processor according to claim 1, which is characterized in that the video input processing unit connector, institute
Video output processing apparatus connector and the expanding unit connector is stated to pass through respectively described in serializer/deserializers bus connects
Matrix switch module.
3. video processor according to claim 1, which is characterized in that the master control set connector passes through universal serial bus
It is connect with the matrix switch module, the programmable logic device connects the master control dress by FMC bus or FSMC bus
It sets connector and is connect by third ethernet PHY transceiver group with the expanding unit connector.
4. video processor according to claim 1, which is characterized in that the first ethernet PHY transceiver group and
The second ethernet PHY transceiver group includes 100 m ethernet physical layer transceiver or gigabit Ethernet physical layer transceiver
Device.
5. a kind of backplane communication method, which is characterized in that the backplane communication method is suitable for video as described in claim 1
Processor and include:
The back board device receives the second interface circuit from the master control set via the master control set connector
Data；
Data described in the master control set connection port transmission are to the programmable logic device on the back board device；
The programmable logic device passes through the first ethernet PHY transceiver group and second ethernet physical layer
Transceiver group is defeated via the video input processing unit connector and the video by the data in a manner of point-to-point communication
Processing unit connector is sent to the video input processing unit and the video output processing apparatus out.
6. backplane communication method according to claim 5, which is characterized in that further include:
The back board device receives the second interface circuit from the master control set via the master control set connector
Switching command；
Switching command described in the master control set connection port transmission is to the matrix switch module on the back board device；
The matrix switch module on the back board device switches the video input processing unit according to the switching command
Data exchange relationship between the video output processing apparatus.
7. backplane communication method according to claim 5, which is characterized in that further include:
The back board device is set to pass through the expanding unit connecting with the expanding unit connector and another video processor shape
At cascade, to carry out data interaction with another described video processor.
8. backplane communication method according to claim 5, which is characterized in that the first ethernet PHY transceiver group
It include that 100 m ethernet physical layer transceiver or gigabit Ethernet physical layer are received with the second ethernet PHY transceiver group
Send out device.
9. a kind of video processor characterized by comprising video input processing unit, video output processing apparatus, master control dress
It sets, expanding unit, matrix switch module and programmable logic device；The matrix switch module connects the video input processing
Device, the video output processing apparatus, the master control set and the expanding unit；The programmable logic device connects institute
It states master control set and connects the video input processing dress with the expanding unit and by the first ethernet PHY transceiver group
It sets and the video output processing apparatus is connected by the second ethernet PHY transceiver group；
The master control set includes: microcontroller, first interface circuit and second interface circuit；The first interface circuit connection
The microcontroller and the communication interface including being adapted to host computer, microcontroller described in the second interface circuit connection,
And the master control set is connect by the second interface circuit with the matrix switch module and the programmable logic device.
10. video processor as claimed in claim 9, which is characterized in that
The second interface circuit of the master control set is connect by universal serial bus with the matrix switch module, described to compile
Journey logical device connects the second interface circuit of the master control set by FMC bus or FSMC bus and passes through third
Ethernet PHY transceiver group is connect with the expanding unit.
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Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6959003B1 (en) * | 1998-09-22 | 2005-10-25 | Kabushiki Kaisha Toshiba | Serial transmission path switching system |
| CN201001167Y (en) * | 2006-12-30 | 2008-01-02 | 深圳洪迪实业有限公司 | Video matrix conversion device |
| CN102082919A (en) * | 2009-11-28 | 2011-06-01 | 天津七所信息技术有限公司 | Digital video matrix |
| CN102223490A (en) * | 2011-06-22 | 2011-10-19 | 上海博康智能网络科技有限公司 | Digital switching matrix supporting synchronic switching and synchronic switching method of digital image |
| CN102883110A (en) * | 2012-09-19 | 2013-01-16 | 旗瀚科技有限公司 | Video signal switching matrix system and system main board and service daughter board thereof |
| CN203645769U (en) * | 2013-10-17 | 2014-06-11 | 杭州中威电子股份有限公司 | High definition digital video monitoring device based on optical fiber network |
| CN105100681A (en) * | 2014-04-28 | 2015-11-25 | 浙江大华技术股份有限公司 | Video matrix cascade control method, device and system |
-
2017
- 2017-09-22 CN CN201710866792.4A patent/CN107645638B/en active Active
Patent Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6959003B1 (en) * | 1998-09-22 | 2005-10-25 | Kabushiki Kaisha Toshiba | Serial transmission path switching system |
| CN201001167Y (en) * | 2006-12-30 | 2008-01-02 | 深圳洪迪实业有限公司 | Video matrix conversion device |
| CN102082919A (en) * | 2009-11-28 | 2011-06-01 | 天津七所信息技术有限公司 | Digital video matrix |
| CN102223490A (en) * | 2011-06-22 | 2011-10-19 | 上海博康智能网络科技有限公司 | Digital switching matrix supporting synchronic switching and synchronic switching method of digital image |
| CN102223490B (en) * | 2011-06-22 | 2013-04-10 | 博康智能网络科技股份有限公司 | Digital switching matrix supporting synchronic switching and synchronic switching method of digital image |
| CN102883110A (en) * | 2012-09-19 | 2013-01-16 | 旗瀚科技有限公司 | Video signal switching matrix system and system main board and service daughter board thereof |
| CN203645769U (en) * | 2013-10-17 | 2014-06-11 | 杭州中威电子股份有限公司 | High definition digital video monitoring device based on optical fiber network |
| CN105100681A (en) * | 2014-04-28 | 2015-11-25 | 浙江大华技术股份有限公司 | Video matrix cascade control method, device and system |
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