CN107645638A - Video processor and backplane communication method - Google Patents
Video processor and backplane communication method Download PDFInfo
- Publication number
- CN107645638A CN107645638A CN201710866792.4A CN201710866792A CN107645638A CN 107645638 A CN107645638 A CN 107645638A CN 201710866792 A CN201710866792 A CN 201710866792A CN 107645638 A CN107645638 A CN 107645638A
- Authority
- CN
- China
- Prior art keywords
- connector
- processing unit
- master control
- video
- control set
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Abstract
The embodiment of the invention discloses a kind of video processor, including：Video input processing unit, video frequency output processing unit, master control set and back board device；Wherein, the back board device includes：Matrix switch module, video input processing unit connector, video frequency output processing unit connector, master control set connector, expanding unit connector and PLD；The PLD connects the master control set connector with the expanding unit connector and connects the video input processing unit connector by the first ethernet PHY transceiver group and connect the video frequency output processing unit connector by the second ethernet PHY transceiver group.The invention also discloses a kind of backplane communication method.The present invention can improve traffic rate and realize point-to-point communication.
Description
Technical field
The present invention relates to video display technology field, more particularly to a kind of video processor and a kind of backplane communication side
Method.
Background technology
In video display technology field, when the boards such as input, output, control are interacted by backboard, this is just needed
Certain communication mode is designed on backboard to realize.Backplane communication mode more general at present, generally use matrix switch core
Piece+ARM or MCU, it is generally basede on the agreements such as RS485, SPI, I2C and is transmitted, using a pair of multi-communication modes.Control card is sent out
Go out broadcasting instructions, by each subcard (input card, output board card) according to address choice, by data feedback to bus, then by controlling
Making sheet card wheel, which is followed, to conduct interviews, and often traffic rate is relatively low for these communication means, and this is greatly lowered the performance of product.
The content of the invention
Embodiments of the invention provide a kind of video processor and a kind of backplane communication method, can improve traffic rate
And realize point-to-point communication.
On the one hand, there is provided a kind of video processor, including：Video input processing unit, video frequency output processing unit, master
Control device and back board device；Wherein, the back board device includes：Matrix switch module, video input processing unit connector, regard
Frequency output processing apparatus connector, master control set connector, expanding unit connector and PLD；The matrix is handed over
Mold changing block is connected between the video input processing unit connector and the video frequency output processing unit connector, the square
Battle array Switching Module is also connected with the master control set connector and the expanding unit connector；The PLD connection
Described in the master control set connector connects with the expanding unit connector and by the first ethernet PHY transceiver group
Video input processing unit connector and pass through the second ethernet PHY transceiver group and connect video frequency output processing dress
Put connector；The master control set includes：Microcontroller, first interface circuit and second interface circuit；The first interface electricity
Road connects the microcontroller and the communication interface including being adapted to host computer, and the second interface circuit connects the micro-control
The connector of device processed and the master control set connector including connecting the back board device.
In one embodiment of the invention, the video input processing unit connector, video frequency output processing dress
Put connector and the matrix switch module is connected by serializer/deserializers bus respectively with the expanding unit connector.
In one embodiment of the invention, the master control set connector passes through universal serial bus and the matrix switch mould
Block connects, and the PLD connects the master control set connector by FMC buses or FSMC buses and passed through
Three-ethernet physical layer transceiver group is connected with the expanding unit connector.
In one embodiment of the invention, the first ethernet PHY transceiver group and the second Ethernet thing
Reason layer transceiver group includes 100 m ethernet physical layer transceiver or gigabit Ethernet physical layer transceiver.
On the other hand, a kind of backplane communication method is additionally provided, the backplane communication method is applied to regard as previously described
Frequency processor and including：The back board device receives described the from the master control set via the master control set connector
The data of two interface circuits；Data are patrolled to described may be programmed on the back board device described in the master control set connection port transmission
Collect device；The PLD passes through the first ethernet PHY transceiver group and the second Ethernet physics
Layer transceiver group is in a manner of point-to-point communication by the data via the video input processing unit connector and the video
Output processing apparatus connector is sent to the video input processing unit and the video frequency output processing unit.
In one embodiment of the invention, the backplane communication method also includes：The back board device is via the master
Control the switching command that device connector receives the second interface circuit from the master control set；The master control set connection
Switching command described in port transmission is to the matrix switch module on the back board device；The matrix on the back board device
Switching Module switches between the video input processing unit and the video frequency output processing unit according to the switching command
Data exchange relation.
In one embodiment of the invention, the backplane communication method also includes：Make the back board device by with institute
Expanding unit and another video processor for stating the connection of expanding unit connector are formed and cascaded, with another described video
Manage device and carry out data interaction.
In one embodiment of the invention, the first ethernet PHY transceiver group and the second Ethernet thing
Reason layer transceiver group includes 100 m ethernet physical layer transceiver or gigabit Ethernet physical layer transceiver.
Another further aspect, a kind of video matrix processor is additionally provided, including：At video input processing unit, video frequency output
Manage device, master control set, expanding unit, matrix switch module and PLD；The matrix switch module connects institute
State video input processing unit, the video frequency output processing unit and the expanding unit；The PLD connection
The expanding unit simultaneously connects the video input processing unit and by the by the first ethernet PHY transceiver group
Two ethernet PHY transceiver groups connect the video frequency output processing unit；The master control set includes：Microcontroller, first
Interface circuit and second interface circuit；The first interface circuit connects the microcontroller and including being adapted to host computer
Communication interface, the second interface circuit connect microcontroller, the matrix switch module and the programmable logic device
Part.
In one embodiment of the invention, the second interface circuit of the master control set passes through universal serial bus and institute
The connection of matrix switch module is stated, the PLD connects by described the second of the FSMC buses connection master control set
Mouthful circuit and it is connected by three-ethernet physical layer transceiver group with the expanding unit.
Above-mentioned technical proposal can have following one or more advantages：Back board device is by including microcontroller, first
The master control set of interface circuit and second interface circuit by data distributing to PLD, by PLD again
Each video input processing unit and video frequency output are connected by the ethernet PHY transceiver of 100,000,000 or gigabit transmission rate
Processing unit, so as to realize that the point-to-point high speed between each video input processing unit and video frequency output processing unit is led to
Letter, reach the high efficiency of transmission of data.In addition, by setting expanding unit connector, more can be realized by expanding unit and is regarded
Cascade between frequency processor.
Brief description of the drawings
In order to illustrate the technical solution of the embodiments of the present invention more clearly, required use in being described below to embodiment
Accompanying drawing be briefly described, it should be apparent that, drawings in the following description are only some embodiments of the present invention, for this
For the those of ordinary skill of field, on the premise of not paying creative work, it can also be obtained according to these accompanying drawings other
Accompanying drawing.
Figure 1A is a kind of structural representation of the back board device of video processor of first embodiment of the invention；
Figure 1B is a kind of structural representation of the master control set of video processor of first embodiment of the invention；
Fig. 2 is a kind of schematic flow sheet of backplane communication method of second embodiment of the invention；
Fig. 3 is a kind of structural representation of video processor of third embodiment of the invention.
Embodiment
Below in conjunction with the accompanying drawing in the embodiment of the present invention, the technical scheme in the embodiment of the present invention is carried out clear, complete
Site preparation describes, it is clear that described embodiment is only part of the embodiment of the present invention, rather than whole embodiments.It is based on
Embodiment in the present invention, those of ordinary skill in the art are obtained every other under the premise of creative work is not made
Embodiment, belong to the scope of protection of the invention.
First embodiment
As shown in Figure 1A, a kind of video processor that first embodiment of the invention provides, mainly includes：Video input processing
Device 121, video frequency output processing unit 131, master control set 141 and back board device 10；Wherein, back board device 10 includes：Matrix
Switching Module 11, video input processing unit connector 12, video frequency output processing unit connector 13, master control set connector
14th, expanding unit connector 15 and PLD 16；Matrix switch module 11 is connected to video input processing unit company
Between interface 12 and video frequency output processing unit connector 13, matrix switch module 11 is also connected with master control set connector 14 and expanded
Extending apparatus connector 15；PLD 16 connects master control set connector 14 and expanding unit connector 15 and passed through
First ethernet PHY transceiver group 17 connects video input processing unit connector 12 and passes through the second Ethernet physics
Layer transceiver group 18 connects video frequency output processing unit connector 13.Matrix switch module 11 is for example including high speed matrix switch core
Piece is as CrossPoint Switch chips etc.；Video input processing unit connector 12, can be with for example including multi-wad join notch
Connection is all the way or multi-channel video input processing device 121；Video frequency output processing unit connector 13 is for example including multi-wad join
Notch, it can connect all the way or multi-channel video output processing apparatus 131；Video input processing unit connector 12, video are defeated
It is for example contour by serializer/deserializers bus (SERDES) respectively to go out processing unit connector 13 and expanding unit connector 15
Fast universal serial bus connection matrix Switching Module 11；PLD 16 is, for example, FPGA (Field Programmable
Gate Array, field programmable gate array) etc..
Specifically, master control set 141 is for example connected by master control set connector 14 with back board device 10, and master control set connects
Interface 14 is connected by universal serial bus such as SPI with matrix switch module 11, and PLD 16 for example passes through variable storage
Controller (Flexible Memory Controller, FMC) bus or variable static storage controller (Flexible
Static Memory Controller, FSMC) bus connection master control set connector 14 and pass through three-ethernet physics
Layer transceiver group 19 is connected with expanding unit connector 15.
Specifically, the first ethernet PHY transceiver group 17 is for example including multichannel ethernet PHY transceiver 171, from
And multi-channel video input processing device connector 12 can be connected；Second ethernet PHY transceiver group 18 is for example including multichannel
Ethernet PHY transceiver 181, so as to connect multi-channel video output processing apparatus connector 13；Ethernet physical layer is received
It is, for example, 100 m ethernet physical layer transceiver or gigabit Ethernet physical layer to send out device 171 and ethernet PHY transceiver 181
Transceiver (when using 100 m ethernet physical layer transceiver, traffic rate 100Mbps；When using gigabit Ethernet physics
During layer transceiver, traffic rate 1000Mbps)；Extension of the back board device 10 for example by being connected with expanding unit connector 15
Device is formed with another video processor and cascaded.
Specifically, master control set 141 mainly includes for example with master control set 20 as shown in Figure 1B, master control set 20：
Circuit board 21, and microcontroller 22, first interface circuit 23 and the second interface circuit 24 being arranged on circuit board 21.First
Interface circuit 23 connects microcontroller 22 and is provided with the communication interface 231 for being adapted to host computer such as computer, and second connects
Mouth circuit 24 connects microcontroller 23 and is provided with the connector 241 for being adapted to back board device 10.Wherein, connector 241
Such as it is FCI interfaces, microcontroller 22 for example includes the microcontroller chip of model STM32F4 series, the conduct of microcontroller 22
The main logic unit of master control set 20.
Specifically, communication interface 231 is for example including serial ports such as RS232 interface (asynchronous transmission standard interface) 1311, USB
Interface (USB) 2313 and RJ45 (Registered Jack 45) interfaces (or network interface) 2315, master control dress
Put 20 and interconnected host computer and the microcontroller 22 in master control set 20 by providing these interfaces, so as to pass through host computer
Interacted with master control set 20.
Further, first interface circuit 23 for example also includes：Transceiver module 233, it is connected to microcontroller 22 and leads to
Between communication interface 231；Transceiver module 233 is for example including serial ports transceiver 2331, USB transceiver 2333 and ethernet physical layer
Transceiver 2335, certainly in certain embodiments, transceiver module 233 can also be include three select one or secondly.Wherein,
Serial ports transceiver 2331 is for example including RS232 serial ports transponder chips, and ethernet PHY transceiver 2335 is for example including 100,000,000
(100M) Ethernet PHY chip.More specifically, foregoing RS232 interface 2311, USB interface 2313 and the three of RJ45 interfaces 2315
Such as the serial ports transceiver 2331 with transceiver module 233, USB transceiver 2333 and ethernet PHY transceiver 2335 respectively
It is connected.
Further, second interface circuit 24 for example also includes：Data bus module 243, it is connected to the He of microcontroller 22
Between connector 241；Data bus module 243 for example including：FMC/FSMC(Flexible Memory Controller/
Flexible Static Memory Controller, variable storage control/variable static storage controller) bus 2431,
I2C buses 2433 and spi bus 2435.More specifically, FMC/FSMC buses 2431, I2C_(Inter-Integrated
Circuit) bus 2433 and SPI (Serial Peripheral Interface, Serial Peripheral Interface (SPI)) bus 2435 are for example divided
It is not connected between microcontroller 22 and connector 241, so as to which master control set 20 can be with back board device 10 by connector 241
Realize connection and data transfer.
Further, master control set 20 for example also includes：Memory module 25, connect microcontroller 22.Memory module
25 preferably include eMMC (Embedded Multi Media Card, embedded multi-media card) memories 251 and flash memory
(Flash)253.Wherein, eMMC memories 251 and flash memory 253 are used for the caching function for realizing data storage and program.
Further, master control set 20 for example also includes：USB flash disk driver 26 and USB interface 27, USB interface 27 pass through USB flash disk
Driver 26 is connected to microcontroller 22.Wherein, master control set 20 for example connects peripheral hardware such as USB flash disk by USB interface 27, realizes
Preserve the function such as off-line files and upgraded in offline.
Further, master control set 20 for example also includes：Wireless communication module 28.Wireless communication module 28 for example including：
WIFI (Wireless Fidelity) modules 281 and antennal interface 283；Antennal interface 283 is connected micro- by WIFI module 281
Controller 22.Wherein, for example external WIFI antennas of antennal interface 283, so as to allow other mobile devices to be connected to master control dress
20 are put, realizes the radio communication between master control set 20 and other mobile devices.
Further, master control set 20 for example also includes：RTC (Real Time Clock, real-time clock) module 29, even
Connect microcontroller 22.Wherein, RTC block 29 is, for example, that master control set 20 provides real-time clock.
In summary, microcontroller 22, first interface circuit 23 and second interface electricity are included in first embodiment of the invention
The master control set 20 on road 24 is connected by the master control set connector 14 that is connected with PLD 16, so as to by number
According to being handed down to PLD 16；Connected again by PLD 16 by the first ethernet PHY transceiver group 17
Connect video input processing unit connector 12 and video frequency output is connected by the second ethernet PHY transceiver group 18 and handle
Device connector 13, so as to realize the point pair between each video input processing unit 121 and video frequency output processing unit 131
Point high-speed communication, reach the high efficiency of transmission of data；In addition, by setting expanding unit connector 15, can be by being filled with extension
Put the connected expanding unit of connector 15 and realize cascade between more video processors.Realize the high efficiency of transmission of data.
Second embodiment
As shown in Fig. 2 a kind of backplane communication method provided for second embodiment of the invention, the backplane communication method are fitted
For the video processor of such as aforementioned first embodiment, the concrete function detail with reference foregoing first of the video processor is real
The description in example is applied, will not be repeated here；The backplane communication method mainly includes step：
S11:Back board device 10 receives the second interface circuit 24 from master control set 141 via master control set connector 14
Data；
S13:Master control set connector 14 transmits the data to the PLD 16 on back board device 10；
S15:PLD 16 passes through the first ethernet PHY transceiver group 17 and the second ethernet physical layer
Transceiver group 18 in a manner of point-to-point communication by the data via video input processing unit connector 12 and video frequency output at
Reason device connector 13 is sent to video input processing unit 121 and video frequency output processing unit 131.
Further, backplane communication method also includes：Back board device 10 receives to come independently via master control set connector 14
Control the switching command of the second interface circuit 24 of device 141；Master control set connector 14 transmits the switching command and filled to backboard
Put the matrix switch module 11 on 10；Matrix switch module 11 on back board device 10 is defeated according to the switching command Switch Video
Enter the data exchange relation between processing unit 121 and video frequency output processing unit 131.
Further, backplane communication method also includes：Make back board device 10 by being connected with expanding unit connector 15
Expanding unit is formed with another video processor and cascaded, to carry out data interaction with another described video processor.
In summary, second embodiment of the invention dorsulum device 10 is by including microcontroller 22, first interface circuit
23 and second interface circuit 24 master control set 20 by data distributing to PLD 16, by PLD 16
Each video input processing unit is connected by the ethernet PHY transceiver 171 and 181 of 100,000,000 or gigabit transmission rate again
121 and video frequency output processing unit 131, so as to realize and each video input processing unit 121 and video frequency output processing unit
Point-to-point high-speed communication between 131, reach the high efficiency of transmission of data；Pass through the matrix switch module 11 on back board device 10
According to the data exchange relation between the switching command Switch Video input processing device 121 and video frequency output processing unit 131；
In addition, by setting expanding unit connector 15, the cascade between more video processors can be realized by expanding unit.
3rd embodiment
As shown in figure 3, a kind of video processor 30 provided for third embodiment of the invention, including：Video input processing
Device 32, video frequency output processing unit 33, master control set 34, expanding unit 35, matrix switch module 31 and programmable logic device
Part 36；Matrix switch module 31 connects video input processing unit 32, video frequency output processing unit 33 and expanding unit 35；It can compile
Journey logical device 36 connects expanding unit 35 and connects video input processing dress by the first ethernet PHY transceiver group 37
Put 32 and video frequency output processing unit 33 is connected by the second ethernet PHY transceiver group 38.Matrix switch module 31
Such as include high speed matrix switch chip as CrossPoint Switch chips；Video input processing unit 32 is for example including more
Individual video input processing unit 321；Video frequency output processing unit 33 is for example including multiple video frequency output processing units 331；Video
Input processing device 32, video frequency output processing unit 33 and expanding unit 35 for example pass through serializer/deserializers bus respectively
(SERDES) the high-speed serial bus connection matrix Switching Module 31 such as；PLD 36 is, for example, FPGA (Field
Programmable Gate Array, field programmable gate array) etc..
Specifically, for master control set 34 for example with the master control set 20 of aforementioned first embodiment, its concrete function details please
With reference to the description in aforementioned first embodiment, will not be repeated here；
Specifically, the second interface circuit 24 of master control set 20 is connected by the universal serial bus such as SPI and matrix switch module 31
Connect, PLD 36 connects the second interface circuit 24 of master control set 20 by FMC buses or FSMC buses and led to
Three-ethernet physical layer transceiver group 39 is crossed to be connected with expanding unit 35.First ethernet PHY transceiver group 37 is for example wrapped
Multichannel ethernet PHY transceiver 371 is included, so as to connect multiple video input processing units 321；Second Ethernet thing
Layer transceiver group 38 is managed for example including multichannel ethernet PHY transceiver 381, so as to connect multiple video frequency output processing
Device 331；Ethernet PHY transceiver 371 and ethernet PHY transceiver 381 are, for example, that 100 m ethernet physical layer is received
(when using 100 m ethernet physical layer transceiver, traffic rate is for hair device or gigabit Ethernet physical layer transceiver
100Mbps；When using gigabit Ethernet physical layer transceiver, traffic rate 1000Mbps).
In summary, microcontroller 22, first interface circuit 23 and second interface electricity are included in third embodiment of the invention
The master control set 34 on road 24 by being connected with PLD 36, so as to by data distributing to PLD
36；Again by PLD 36 by the first ethernet PHY transceiver group 37 connect video input processing unit 32 with
And video frequency output processing unit 33 is connected by the second ethernet PHY transceiver group 38, so as to realize and each video input
Point-to-point high-speed communication between processing unit 321 and video frequency output processing unit 331, reach the high efficiency of transmission of data；In addition,
By setting expanding unit 35, the cascade between more video processors can be realized by expanding unit 35.
In several embodiments provided herein, it should be understood that disclosed system, apparatus and method can be with
Realize by another way.For example, device embodiment described above is only schematical, for example, the unit
Division, only a kind of division of logic function, can there is other dividing mode, such as multichannel unit or component when actually realizing
Another system can be combined or be desirably integrated into, or some features can be ignored, or do not perform.It is another, it is shown or
The mutual coupling discussed or direct-coupling or communication connection can be the indirect couplings by some interfaces, device or unit
Close or communicate to connect, can be electrical, mechanical or other forms.
The unit illustrated as separating component can be or may not be physically separate, show as unit
The part shown can be or may not be physical location, you can with positioned at a place, or can also be distributed to multichannel
On NE.Some or all of unit therein can be selected to realize the mesh of this embodiment scheme according to the actual needs
's.
Finally it should be noted that：The above embodiments are merely illustrative of the technical solutions of the present invention, rather than its limitations；Although
The present invention is described in detail with reference to the foregoing embodiments, it will be understood by those within the art that：It still may be used
To be modified to the technical scheme described in foregoing embodiments, or equivalent substitution is carried out to which part technical characteristic；
And these modification or replace, do not make appropriate technical solution essence depart from various embodiments of the present invention technical scheme spirit and
Scope.
Claims (10)
- A kind of 1. video processor, it is characterised in that including：Video input processing unit, video frequency output processing unit, master control dress Put and back board device；Wherein, the back board device includes：Matrix switch module, video input processing unit connector, video frequency output processing dress Put connector, master control set connector, expanding unit connector and PLD；The matrix switch module is connected to Between the video input processing unit connector and the video frequency output processing unit connector, the matrix switch module is also Connect the master control set connector and the expanding unit connector；The PLD connects the master control set Connector connects the video input processing with the expanding unit connector and by the first ethernet PHY transceiver group Device connector and pass through the second ethernet PHY transceiver group and connect the video frequency output processing unit connector；The master control set includes：Microcontroller, first interface circuit and second interface circuit；The first interface circuit connection The microcontroller and the communication interface including being adapted to host computer, the second interface circuit connect the microcontroller simultaneously Including the connector for the master control set connector for connecting the back board device.
- 2. video processor according to claim 1, it is characterised in that the video input processing unit connector, institute State described in video frequency output processing unit connector and the expanding unit connector connected by serializer/deserializers bus respectively Matrix switch module.
- 3. video processor according to claim 1, it is characterised in that the master control set connector passes through universal serial bus It is connected with the matrix switch module, the PLD connects the master control by FMC buses or FSMC buses and filled Put connector and be connected by three-ethernet physical layer transceiver group with the expanding unit connector.
- 4. video processor according to claim 1, it is characterised in that the first ethernet PHY transceiver group and The second ethernet PHY transceiver group includes 100 m ethernet physical layer transceiver or gigabit Ethernet physical layer transceiver Device.
- A kind of 5. backplane communication method, it is characterised in that the backplane communication method is applied to video as claimed in claim 1 Processor and including：The back board device receives the second interface circuit from the master control set via the master control set connector Data；Data are to the PLD on the back board device described in the master control set connection port transmission；The PLD passes through the first ethernet PHY transceiver group and second ethernet physical layer Transceiver group is defeated via the video input processing unit connector and the video by the data in a manner of point-to-point communication Go out processing unit connector and be sent to the video input processing unit and the video frequency output processing unit.
- 6. backplane communication method according to claim 5, it is characterised in that also include：The back board device receives the second interface circuit from the master control set via the master control set connector Switching command；Switching command is to the matrix switch module on the back board device described in the master control set connection port transmission；The matrix switch module on the back board device switches the video input processing unit according to the switching command Data exchange relation between the video frequency output processing unit.
- 7. backplane communication method according to claim 5, it is characterised in that also include：The back board device is set to pass through the expanding unit being connected with the expanding unit connector and another video processor shape Into cascade, to carry out data interaction with another described video processor.
- 8. backplane communication method according to claim 5, it is characterised in that the first ethernet PHY transceiver group Include 100 m ethernet physical layer transceiver with the second ethernet PHY transceiver group or gigabit Ethernet physical layer is received Send out device.
- A kind of 9. video processor, it is characterised in that including：Video input processing unit, video frequency output processing unit, master control dress Put, expanding unit, matrix switch module and PLD；The matrix switch module connects the video input processing Device, the video frequency output processing unit and the expanding unit；The PLD connects the expanding unit, simultaneously The video input processing unit is connected by the first ethernet PHY transceiver group and passes through the second ethernet physical layer Transceiver group connects the video frequency output processing unit；The master control set includes：Microcontroller, first interface circuit and second interface circuit；The first interface circuit connection The microcontroller and the communication interface including being adapted to host computer, the second interface circuit connect the microcontroller, The matrix switch module and the PLD.
- 10. video processor as claimed in claim 9, it is characterised in thatThe second interface circuit of the master control set is connected by universal serial bus with the matrix switch module, described to compile Journey logical device by FMC buses or FSMC buses connects the second interface circuit of the master control set and passes through the 3rd Ethernet PHY transceiver group is connected with the expanding unit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710866792.4A CN107645638B (en) | 2017-09-22 | 2017-09-22 | Video processor and backplane communication method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710866792.4A CN107645638B (en) | 2017-09-22 | 2017-09-22 | Video processor and backplane communication method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN107645638A true CN107645638A (en) | 2018-01-30 |
| CN107645638B CN107645638B (en) | 2019-10-11 |
Family
ID=61111336
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201710866792.4A Active CN107645638B (en) | 2017-09-22 | 2017-09-22 | Video processor and backplane communication method |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN107645638B (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2021035387A1 (en) * | 2019-08-23 | 2021-03-04 | 北京嗨动视觉科技有限公司 | Communication method and apparatus, video processor and backplane |
Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6959003B1 (en) * | 1998-09-22 | 2005-10-25 | Kabushiki Kaisha Toshiba | Serial transmission path switching system |
| CN201001167Y (en) * | 2006-12-30 | 2008-01-02 | 深圳洪迪实业有限公司 | Video matrix conversion device |
| CN102082919A (en) * | 2009-11-28 | 2011-06-01 | 天津七所信息技术有限公司 | Digital video matrix |
| CN102223490A (en) * | 2011-06-22 | 2011-10-19 | 上海博康智能网络科技有限公司 | Digital switching matrix supporting synchronic switching and synchronic switching method of digital image |
| CN102883110A (en) * | 2012-09-19 | 2013-01-16 | 旗瀚科技有限公司 | Video signal switching matrix system and system main board and service daughter board thereof |
| CN203645769U (en) * | 2013-10-17 | 2014-06-11 | 杭州中威电子股份有限公司 | High definition digital video monitoring device based on optical fiber network |
| CN105100681A (en) * | 2014-04-28 | 2015-11-25 | 浙江大华技术股份有限公司 | Video matrix cascade control method, device and system |
-
2017
- 2017-09-22 CN CN201710866792.4A patent/CN107645638B/en active Active
Patent Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6959003B1 (en) * | 1998-09-22 | 2005-10-25 | Kabushiki Kaisha Toshiba | Serial transmission path switching system |
| CN201001167Y (en) * | 2006-12-30 | 2008-01-02 | 深圳洪迪实业有限公司 | Video matrix conversion device |
| CN102082919A (en) * | 2009-11-28 | 2011-06-01 | 天津七所信息技术有限公司 | Digital video matrix |
| CN102223490A (en) * | 2011-06-22 | 2011-10-19 | 上海博康智能网络科技有限公司 | Digital switching matrix supporting synchronic switching and synchronic switching method of digital image |
| CN102223490B (en) * | 2011-06-22 | 2013-04-10 | 博康智能网络科技股份有限公司 | Digital switching matrix supporting synchronic switching and synchronic switching method of digital image |
| CN102883110A (en) * | 2012-09-19 | 2013-01-16 | 旗瀚科技有限公司 | Video signal switching matrix system and system main board and service daughter board thereof |
| CN203645769U (en) * | 2013-10-17 | 2014-06-11 | 杭州中威电子股份有限公司 | High definition digital video monitoring device based on optical fiber network |
| CN105100681A (en) * | 2014-04-28 | 2015-11-25 | 浙江大华技术股份有限公司 | Video matrix cascade control method, device and system |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2021035387A1 (en) * | 2019-08-23 | 2021-03-04 | 北京嗨动视觉科技有限公司 | Communication method and apparatus, video processor and backplane |
Also Published As
| Publication number | Publication date |
|---|---|
| CN107645638B (en) | 2019-10-11 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN103546299B (en) | Use the 50Gb/s Ethernet of serializer/de-serializers passage | |
| CN204650513U (en) | Distributed structure/architecture equipment and serial port circuit thereof | |
| CN110321313A (en) | Configurable interface card | |
| EP3029884A1 (en) | Commissioning method, master control board, and service board | |
| CN203658996U (en) | Chip interface multiplex circuit and mobile terminal | |
| CN106326168B (en) | Connecting circuit and computer system with same | |
| CN106250333A (en) | A kind of signal processing card system based on FPGA | |
| CN207234816U (en) | A kind of VPX power boards of SRIO and Ethernet | |
| CN204925719U (en) | Signal conversion equipment and system | |
| CN106302071A (en) | A kind of adapter, the network equipment and the method for port configuration | |
| CN106598888B (en) | A kind of more board communication systems and method using RS485 agreement | |
| CN109586956B (en) | FCoE switch capable of flexibly configuring ports and method | |
| CN111581152A (en) | Reconfigurable hardware acceleration SOC chip system | |
| US10990307B2 (en) | System and method for providing a configurable storage media interface | |
| CN109240960B (en) | Exchange board circuit based on VPX architecture and implementation method thereof | |
| CN107645638B (en) | Video processor and backplane communication method | |
| CN107181702B (en) | Device for realizing RapidIO and Ethernet fusion exchange | |
| CN103488598A (en) | Multi-mode terminal and method for realizing USB (universal serial bus) sharing | |
| CN103116560B (en) | Programmable blade server structure | |
| CN205788168U (en) | Master-slave mode serial equipment hub | |
| CN201887957U (en) | Wireless router supporting 3G system | |
| CN205283577U (en) | Device through high speed bus extension multichannel RS422485 interface | |
| CN105264510A (en) | Field programmable gate array and communication method | |
| CN204480237U (en) | A kind of connector, universal serial bus device and intelligent terminal | |
| CN107102961A (en) | Accelerate the method and system of arm processor concurrent working |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |