KR101920073B1 - Method and apparatus for converting signal for bandwidth variable data transmission/reception - Google Patents

Abstract

A signal conversion apparatus for transmitting and receiving bandwidth variable data is provided. Wherein the signal conversion apparatus is located between a physical layer module and a deserializer, and the signal conversion apparatus comprises: a transmission buffer for storing data to be transmitted transmitted from the physical layer module; A first receiving buffer and a second receiving buffer for storing received data transmitted from the serial-to-parallel converter; A transmission data converter for converting the data stored in the transmission buffer according to the bandwidth information provided from the physical layer module and outputting the data to the serial-to-parallel converter; And a receive data converter for converting the data stored in the first receiving buffer and / or the second receiving buffer according to an applied control signal and outputting the converted data to the physical layer module.

Description

TECHNICAL FIELD [0001] The present invention relates to a signal conversion apparatus for transmitting and receiving variable bandwidth data,

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a signal conversion apparatus, and more particularly, to a signal conversion apparatus for variable bandwidth data transmission and reception.

In a communication modem requiring low power and low cost such as ultra high-speed proximity communication in a wireless data communication, a high-speed SerDes (Serializer / Deserializer) is provided between a physical layer (PHY) . In particular, SerDes achieves high data rate through an optimized analog circuit design for low power / low cost. The performance of data transmission over a wireless channel changes according to the transmission bandwidth, and the transmission bandwidth varies depending on the presence or absence of the channel bonding. In order to change the transmission speed of the data to be transmitted to the RF module according to the transmission bandwidth, the transmission speed of the SerDes must be changed. To do so, the operating speed of the SerDes must be changed according to the required transmission bandwidth.

However, due to the characteristics of SerDes based on analog circuits, this structure can lead to a large design time, circuit size, and power consumption for each bandwidth support.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a signal conversion apparatus for transmitting and receiving bandwidth variable data of a low-cost low-power structure used in a communication modem.

Another object of the present invention is to provide a signal conversion apparatus capable of varying bandwidth without changing the structure of SerDes in data transmission / reception according to channel bandwidth using an On-Off Keying (OOK) modem.

According to one embodiment of the present invention, a signal conversion apparatus used in a communication modem is provided. Wherein the signal conversion apparatus is located between a physical layer module and a deserializer, and the signal conversion apparatus comprises: a transmission buffer for storing data to be transmitted transmitted from the physical layer module; A first receiving buffer and a second receiving buffer for storing received data transmitted from the serial-to-parallel converter; A transmission data converter for converting the data stored in the transmission buffer according to the bandwidth information provided from the physical layer module and outputting the data to the serial-to-parallel converter; And a receive data converter for converting the data stored in the first receiving buffer and / or the second receiving buffer according to an applied control signal and outputting the converted data to the physical layer module.

According to the embodiment of the present invention, in the data transmission / reception according to the channel bandwidth using the OOK modem, the signal conversion device capable of changing the bandwidth of the existing structure is added without changing the structure of the SerDes, The bandwidth can be varied.

Thus, low power SerDes optimized for a single clock can be reused, low cost low power structure can be realized, and design cost can be minimized. In particular, the transmission bandwidth can be easily varied at low cost.

1 is a diagram illustrating a physical layer and a SerDes (Serializer / Deserializer) connection structure in an On-Off Keying (OOK) modem according to an embodiment of the present invention.
Figs. 2 and 3 show examples of data reception processing by SerDes.
4 is a diagram illustrating a structure of a signal conversion apparatus according to an embodiment of the present invention.
5 is a diagram illustrating connection states for first and second transmissions of the signal conversion apparatus according to the embodiment of the present invention.
FIG. 6 is a timing diagram for a first transmission according to an embodiment of the present invention, and FIG. 7 illustrates signal conversion processing for a first transmission according to an embodiment of the present invention.
FIG. 8 is a timing diagram for a second transmission according to an embodiment of the present invention, and FIG. 9 is a diagram illustrating signal processing for a second transmission according to an embodiment of the present invention.
FIG. 10 is a timing chart for a first reception according to an embodiment of the present invention, and FIG. 11 is a diagram illustrating signal conversion processing for a first reception according to an embodiment of the present invention.
12 is a diagram illustrating a process in a received data converter according to an embodiment of the present invention.
13 is a timing diagram for a second reception in accordance with an embodiment of the present invention.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art can easily carry out the present invention. The present invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein.

In order to clearly illustrate the present invention, parts not related to the description are omitted, and similar parts are denoted by like reference characters throughout the specification.

Throughout the specification and claims, when a section is referred to as including an element, it is understood that it may include other elements as well, without departing from the other elements unless specifically stated otherwise.

The expressions described in the singular may be interpreted as singular or plural unless an explicit expression such as "a" or "a" is used.

Hereinafter, a signal conversion apparatus for transmitting and receiving bandwidth variable data according to an embodiment of the present invention will be described.

1 is a diagram illustrating a physical layer and a SerDes (Serializer / Deserializer) connection structure in an On-Off Keying (OOK) modem according to an embodiment of the present invention.

Specifically, FIG. 1 shows a physical layer (PHY) and a SerDes connection structure in an OOK modem that performs 3.52 Gbps transmission through two-channel bonding.

The serial-to-parallel converter, SerDes, performs a transmission and reception function of serializing and transmitting parallel bits at the time of transmission and restoring the bit strings back to the original parallel bits at the time of reception. Such SerDes is located between the physical layer (PHY) and the RF module and changes the transmission speed of the data, as in Fig. In particular, SerDes is optimized for data transmission over 3.52Gbps 2-channel bonding in the IEEE802.15.3c transmission standard, and supports 3.52Gbps and 1.76Gbps transmission in OOK (On-Off Keying) modem for transmitting and receiving data.

In order to support this transmission, if the SerDes transmission rate is redesigned to support 3.52Gbps and 1.76Gbps at the same time, or if SerDes can not be changed easily, transmission of 1.76Gbps data can be performed by time domain spreading It is processed in a reduced transmission manner. In the case of reception, since the preamble is inputted differently according to the bandwidth, it is necessary to change the synchronizer to recognize the preamble according to each band.

However, this method causes a lot of design cost and power consumption due to the characteristics of the SerDes and the synchronizing device which occupy most of the power consumption in the modem.

In the embodiment of the present invention, a signal conversion device is added between the physical layer (PHY) and the SerDes, which can change the data according to the channel bandwidth, without changing the SerDes or the synchronization device.

Figs. 2 and 3 show examples of data reception processing by SerDes.

Specifically, FIG. 2 shows 32-bit data to be received by the PHY when data is received without change of SerDes when 1.76 Gbps data transmission is performed, and FIG. 3 shows a case where 3.5Dbps data transmission is performed without changing SerDes Indicates the 32-bit data to be received by the PHY when the data is received.

When SerDes is used as it is, when 1.76 Gbps data transmission is performed, 16-bit data is received according to 1.76-Gbps data transmission, 16-bit received data is converted to 32-bit through SerDes, do. At this time, 16 inputs input at 1.76 Gbps are repeated once, converted to 32 bits, and output to the PHY.

3, 32-bit data is received according to 3.52-Gbps data transmission, 32-bit received data is directly converted to 32-bit through SerDes, and the PHY Lt; / RTI >

In the case of supporting 3.52 Gbps and 1.76 Gbps transmission as described above, when SerDes is used as it is, different 32-bit outputs appear at 3.52 Gbps and 1.76 Gbps for the same input, I can not get motivated.

In the embodiment of the present invention, a signal conversion device capable of changing the bandwidth is added between the PHY and SerDes. This makes it possible to transmit and receive data without changing the synchronous circuit.

4 is a diagram illustrating a structure of a signal conversion apparatus according to an embodiment of the present invention.

4, the signal conversion apparatus 1 according to the embodiment of the present invention includes a buffer controller 10, an interface unit 20, a bandwidth controller 30, A buffer 40, a Tx data converter 50, a Rx data converter 60, a first receiving buffer 70 and a second receiving buffer 80. [ Including a bandwidth controller 30, a transmit buffer 40, a transmit data converter 50, a receive data converter 60, a first receive buffer 70 and a second receive buffer 80, Processing section ".

The buffer controller 10 controls the transmission buffer 40 and the first and second reception buffers 70 and 80 of the signal conversion apparatus 1 and specifically controls the transmission buffer 40 and the first and second reception (For example, to the physical layer or SerDes) and information on whether buffers 70 and 80 are empty or full, respectively, and buffer level information, (40), and manages control signals for allowing the received data to be read from the receiving buffers (70, 80).

The interface unit 20 interfaces with SerDes. Specifically, the interface unit 20 outputs data whose bandwidth has been changed by the bandwidth change processing unit to SerDes, and outputs a control signal for receiving data from SerDes. The corresponding component of the bandwidth change processing unit operates according to the control signal to perform the above process.

The bandwidth controller 30 generates and outputs a control signal for changing the data according to the bandwidth information of the channel to be transmitted and received. Specifically, the bandwidth controller 30 generates a control signal for reading data stored in the transmission buffer 40 according to the channel bandwidth information received from the modem at the time of transmission, and generates 32-bit And generates control signals for dividing the data into the first reception buffer 70 and the second reception buffer 80 and determines whether the first and second reception buffers 70 and 80 can be accessed according to the channel bandwidth And this control signal and control information can be provided to the buffer controller 10. [0050]

The transmission buffer 40 and the reception buffers 70 and 80 are asynchronous buffers and separate the clock domains of the SerDes and the PHY.

The transmission data converter 50 and the reception data converter 60 are responsible for reconstructing data under the control of the bandwidth controller 30. [

The signal conversion apparatus 1 having such a structure is located between the PHY and SerDes and operates as follows.

In carrying out 3.52 Gbps and 1.76 Gbps transmission, 1.76 Gbps transmission is referred to as a first transmission and 3.52 Gbps transmission is referred to as a second transmission for convenience of explanation.

5 is a diagram illustrating connection states for first and second transmissions of the signal conversion apparatus according to the embodiment of the present invention.

For the bandwidth change, the signal conversion apparatus 1 is located between the PHY and SerDes, as shown in Fig. For 1.76 Gbps transmission or 3.52 Gbps transmission, the transmission data (PHY_Tx_Data) from the PHY is transmitted to the SerDes through the signal conversion apparatus according to the embodiment of the present invention.

First, the 1.76 Gbps transmission process will be described.

FIG. 6 is a timing diagram for a first transmission according to an embodiment of the present invention, and FIG. 7 illustrates signal conversion processing for a first transmission according to an embodiment of the present invention.

For 1.76 Gbps transmission, transmission data (PHY_Tx_Data in Fig. 5) from the PHY is stored in the transmission buffer of the signal conversion apparatus. The data stored in the transmission buffer (indicated by Tx Buffer Data in FIG. 6) is repeated twice for each bit, divided into 32 bits and transmitted to SerDes, as shown in FIG. In FIG. 7, Tx_SD [31: 0] represents the data processed by the signal conversion apparatus and transmitted to SerDes. The data transmitted to the SerDes is transmitted to the RF module (not shown) at 3.52 Gbps, but the actual data has a bandwidth of 1.76 Gbps by repeating the same bit twice.

Next, the 3.52Gbps transmission process will be described.

FIG. 8 is a timing diagram for a second transmission according to an embodiment of the present invention, and FIG. 9 is a diagram illustrating signal processing for a second transmission according to an embodiment of the present invention.

For 3.52 Gbps transmission, the transmission data (PHY_Tx_Data in FIG. 5) from the PHY is stored in the transmission buffer of the signal conversion apparatus. Since the data stored in the transmission buffer (Tx Buffer Data in FIG. 8) is 32 bits, it is transferred to SerDes without conversion as shown in FIG. In Fig. 8, Tx_SD [31: 0] represents data that is processed by the signal converting apparatus and is transmitted to SerDes. The data delivered to the SerDes has a bandwidth of 3.52 Gbps.

Next, the reception process will be described.

9 is a diagram illustrating a connection state for first and second reception of the signal conversion apparatus according to the embodiment of the present invention.

For the bandwidth change, the signal conversion apparatus 1 is located between the PHY and the SerDes, as shown in Fig. For 1.76 Gbps reception or 3.52 Gbps reception, the received data (Rx_SD_D) from SerDes is transferred to the PHY via the signal conversion apparatus according to the embodiment of the present invention. For convenience of explanation, 1.76 Gbps reception is referred to as a first reception, and 3.52 Gbps reception is referred to as a second reception.

First, the 1.76Gbps reception process will be described.

FIG. 10 is a timing chart for a first reception according to an embodiment of the present invention, and FIG. 11 is a diagram illustrating signal conversion processing for a first reception according to an embodiment of the present invention.

In order to receive 1.76 Gbps data, the received data (Rx_SD_D) from the SerDes via the signal converting apparatus is sequentially stored in the first receiving buffer and the second receiving buffer of the signal converting apparatus, as shown in Fig. 10, Rx Buffer 0 represents data stored in the first reception buffer, and Rx Buffer 1 represents data stored in the second reception buffer.

Specifically, received data from SerDes is stored in a first receiving buffer (Rx Buffer 0) and a second receiving buffer (Rx Buffer 1) by a write control signal (Write Enable) generated by a bandwidth controller of the signal converting apparatus, The stored data level information of the buffer is transmitted to the PHY via the buffer controller through the buffer controller. The PHY generates a reception control signal (PHY Rx Enable) according to the buffer state. The bandwidth controller uses a reception control signal (PHY Rx Enable) to generate a first reception buffer Rx Buffer 0 and a second reception buffer Rx Buffer 1 ) To be output. According to the control signal from the bandwidth controller, the received data converter reads the data stored in the first receiving buffer (Rx Buffer 0) and the second receiving buffer (Rx Buffer 1), and the received receiving data can be processed by the synchronous circuit of the PHY And outputs the converted data to the PHY.

12 is a diagram illustrating a process in a received data converter according to an embodiment of the present invention.

The receive data converter includes a data selector, as in Fig.

The data stored in the first reception buffer Rx Buffer 0 and the second reception buffer Rx Buffer 1 are output according to a control signal from the bandwidth controller, and the data selector selects the first reception buffer Rx Buffer 0, Converts the data output from the buffer (Rx Buffer 1) into data that can be processed by the synchronous circuit of the PHY, and outputs the data to the PHY. At this time, the data selector selects and outputs a signal having a large number when two or more signals are input, and selects and outputs a signal having the same number.

Packets received at 1.76Gbps in the RF module pass through SerDes with 3.52Gbps performance, and through the processing of this signal converter, each bit of the packet is repeated twice. As a result, the packet data output through the SerDes is converted through the signal conversion apparatus as shown in FIG. 11 and transferred to the PHY. Thus, data of different bandwidths can be processed without changing the synchronization circuit.

A description will be given of the 3.52 Gbps reception process.

13 is a timing diagram for a second reception in accordance with an embodiment of the present invention.

For reception of 3.52 Gbps data, the received data (Rx_SD_D) from the SerDes via the signal converting apparatus is stored in the first receiving buffer of the signal converting apparatus, as in Fig. When data of 3.52 Gbps bandwidth is received, data output from SerDes is stored only in the first reception buffer (Rx Buffer 0).

The stored data level information of the buffer is transmitted to the PHY via the buffer controller through the bandwidth controller, and the PHY generates the reception control signal (PHY Rx Enable). According to the reception control signal (PHY Rx Enable), data stored in the first reception buffer (Rx Buffer 0) is output to the PHY without conversion as shown in FIG.

In the signal conversion apparatus as described above, by changing the number of buffers (the number of transmission buffers, the number of reception buffers) and the controller (buffer controller, bandwidth controller, etc.) Speed SerDes, so that it is possible to easily change the bandwidth according to 1-channel, 2-channel, and 3-channel bonding. Specifically, the number of reception buffers for receiving data output from SerDes varies depending on the number of channels used for channel bonding, and the data selector selects and outputs a bit that is equal to or more than the set number of bits input from the plurality of reception buffers . For example, in a system using three-channel bonding, a first receiving buffer, a second receiving buffer, and a third receiving buffer may be used as the receiving buffers, and the data selector may select the data from the first receiving buffer to the third receiving buffer Bits are grouped into 3 bits in order to receive 32 sets. That is, the data selector receives three inputs (B0_0, B0_1, and B0_2) from the buffer to output Out_0, and selects and outputs two or more bits. In the case of Out_1, the output is determined from the inputs of B0_3, B0_4 and B0_5 through the same process as the previous one.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is to be understood that the invention is not limited to the disclosed exemplary embodiments. It belongs to the scope of right.

Claims (10)

A signal conversion device used in a communication modem,
Wherein the signal conversion device is located between a physical layer module and a deserializer,
The signal conversion apparatus includes:
A transmission buffer for storing data to be transmitted transmitted from the physical layer module;
A first receiving buffer and a second receiving buffer for storing received data transmitted from the serial-to-parallel converter;
A transmission data converter for converting the data stored in the transmission buffer according to the bandwidth information provided from the physical layer module and outputting the data to the serial-to-parallel converter; And
A receiving data converter for converting data stored in the first receiving buffer and / or the second receiving buffer according to an applied control signal and outputting the converted data to the physical layer module;
And a signal conversion unit. The method of claim 1, wherein
Wherein the bandwidth information comprises a first bandwidth and a second bandwidth, and wherein the second bandwidth is twice the bandwidth of the first bandwidth. The method according to claim 2, wherein
Wherein the transmission data converter repeatedly outputs the data stored in the transmission buffer twice for each bit when transmitting according to the first bandwidth, and provides the output to the serial-to-parallel converter. The method according to claim 2, wherein
Wherein the transmission data converter outputs the data stored in the transmission buffer without conversion and provides the data to the serial-to-parallel converter when transmitting according to the second bandwidth. The method according to claim 2, wherein
Wherein upon receiving according to the first bandwidth, the receive data converter outputs data stored in the first receive buffer and the second receive buffer, provided from the deserializer, to the physical layer. The method of claim 5, wherein
And a data selector located between the first receiving buffer and the second receiving buffer for selecting one of a bit of data input from the first receiving buffer and a bit of data input from the second receiving buffer,
Further comprising: The method of claim 6, wherein
The number of receiving buffers for receiving data output from the deserializer varies according to the number of channels used for channel bonding,
Wherein the data selector selects and outputs a bit that is present in a number equal to or greater than a set number of bits input from each of the plurality of reception buffers. The method according to claim 2, wherein
Wherein upon reception according to the second bandwidth, the receive data converter outputs 2-bit data stored in the first receive buffer, provided from the deserializer, without conversion, and provides the 2-bit data to the physical layer. The method of claim 1, wherein
A control signal generating unit for generating a control signal for reading data stored in the transmission buffer according to channel bandwidth information when data is transmitted, dividing data input from the deserializer in accordance with channel bandwidth information upon receiving data, A bandwidth controller for generating a control signal for storage in a buffer; And
Controls the writing and reading operations of data to and from the transmission buffer, the first reception buffer, and the second reception buffer according to a control signal provided from the bandwidth controller, and controls information and buffer level information on the state of each buffer Buffer controller
Further comprising: The method of claim 1, wherein
Wherein the communication modem is an On-Off Keying (OOK) modem.

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