CN218240899U

CN218240899U - Multi-FPGA data processing board card

Info

Publication number: CN218240899U
Application number: CN202220909140.0U
Authority: CN
Inventors: 刘海栋
Original assignee: Shanghai Minrong Technology Co ltd
Current assignee: Shanghai Minrong Technology Co ltd
Priority date: 2022-04-19
Filing date: 2022-04-19
Publication date: 2023-01-06
Anticipated expiration: 2032-04-19

Abstract

The utility model discloses a many FPGA data processing integrated circuit boards, include: clock chip, AD chip, first FPGA chip, second FPGA chip, wherein, first FPGA chip includes: the first AD interface unit, the second AD interface unit and the AURORA sending unit are used for sending the serial data output by the first AD interface unit and the second AD interface unit to the second FPGA, the AD data selection unit, the DDC algorithm unit, the data packing unit and the data transmission unit according to an AURORA protocol; the second FPGA chip includes: the system comprises an AURORA protocol receiving unit, an AD data selecting unit, a DDC algorithm unit, a data packing unit and a data transmission unit.

Description

Multi-FPGA data processing board card

Technical Field

The utility model relates to a data transmission field, more specifically say, relate to a many FPGA data processing integrated circuit boards.

Background

When processing the collected external data signals, the field programmable gate array FPGA in the board card is needed to be used, the resource of each FPGA is limited, when a user involves multi-channel data processing exceeding 256 bits, multiple FPGAs are needed to be used, at present, a driving chip is added to each path of data to fan out the data, the method not only increases the complexity of the circuit, but also increases the time delay, and the method also uses the transmission of a server, namely, when data is called among multiple FPGAs, the data is transmitted through the server. Data is read from the DDR of the first FPGA, is transmitted to the server, and is then called in the kernel which is transmitted from the server to the second FPGA, if the exchanged data only brings higher delay and lower throughput through the server, no benefit can be brought, and poor user experience is caused. It is apparent that a more efficient solution is needed to reduce the cost of software and hardware exchanging data.

SUMMERY OF THE UTILITY MODEL

The utility model aims at providing a many FPGA data processing integrated circuit boards have simplified circuit structure, have improved the speed that data read.

The utility model discloses a many FPGA data processing integrated circuit board, include: the clock chip is used for providing a reference clock for the circuit; the AD chip is used for sampling and performing analog-to-digital conversion on data according to a clock signal, and an output interface of the AD chip is connected with the first FPGA chip; the first FPGA chip is used for carrying out down-conversion on the AD-converted digital signals with specific paths and simultaneously transmitting the digital signals to the second FPGA chip according to a certain protocol, and one output interface of the first FPGA chip is connected with the second FPGA chip; wherein the content of the first and second substances,

the first FPGA chip includes:

the first AD interface unit and the second AD interface unit are used for receiving digital signals and converting the digital signals from parallel to serial, and output interfaces of the first AD interface unit and the second AD interface unit are respectively connected with the AURORA sending unit, the AD data selecting unit and the DDC algorithm unit;

the AURORA sending unit is used for sending the serial data output by the first AD interface unit and the second AD interface unit to a second FPGA according to an AURORA protocol, and an output interface of the AURORA sending unit is connected with the second FPGA;

the AD data selection unit is used for selecting data with specific digit and outputting the data to the data packaging unit, and an output interface of the AD data selection unit is connected with the data packaging unit;

the DDC algorithm unit is used for realizing data down-conversion, and an output interface of the DDC algorithm unit is connected with the data packing unit;

the data packing unit is used for packing and outputting the data with the specific digit and the data after down-conversion, and an output interface of the data packing unit is connected with the data transmission unit;

the data transmission unit is used for converting the packed data into parallel data for output;

the second FPGA chip includes:

an AURORA protocol receiving unit for receiving the serial data output by the first FPGA according to AURORA protocol and processing the input serial data, an output interface is connected with the AD data selection unit and the DDC algorithm unit,

the data packing unit is used for packing and outputting the data with the specific digit and the data after the down conversion, and an output interface of the data packing unit is connected with the data transmission unit;

and the data transmission unit is used for converting the packed data into parallel data for output.

Optionally, the data transmission unit is configured to convert the frequency-converted digital signal into a PCIE interface format for output.

Optionally, the system further comprises a DDR chipset for caching data information of the FPGA data down conversion.

Optionally, the second FPGA chip is connected to the upper computer through a PCIE bus.

The beneficial effects of the utility model reside in that:

the utility model discloses a set up AURORA sending unit in first FPGA, realize the serial transmission to second FPGA of data, second FPGA includes AURORA receiving element for receive the data of first FPGA transmission, and utilize other units to carry out corresponding processing, thereby realized FPGA's extension, made the resource obtain make full use of like this, simplified circuit structure.

Drawings

The above and other objects, features and advantages of the present invention will become more apparent by describing in more detail exemplary embodiments of the present invention with reference to the attached drawings, in which like reference numerals generally represent like parts.

Fig. 1 shows a schematic diagram of a multi-FPGA data processing board according to an embodiment of the present invention.

Detailed Description

The invention will be described in more detail below with reference to the accompanying drawings. While the preferred embodiments of the present invention have been illustrated in the accompanying drawings, it is to be understood that the invention may be embodied in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art.

Example 1

As shown in fig. 1, the multi-FPGA data processing board includes: a clock chip 110, configured to provide a reference clock for the circuit, generate a clock signal, and send the sampling clock signal to the AD chip 120; the AD chip samples and performs analog-to-digital conversion on data according to a clock signal, an output interface of the AD chip is connected with the first FPGA chip, and in this embodiment, the AD chip includes two AD chips, and the output interface of the AD chip is connected with the first FPGA chip and respectively processes data signals from different sources, for example, the first AD chip processes data sent by a satellite, the second AD chip processes data sent by a user, performs digital conversion on an analog signal, and outputs the converted digital signal to the first FPGA chip.

The first FPGA chip 130 includes: a first AD interface unit 1301, a second AD interface unit 1302, an AURORA sending unit 1303, and an AD data selecting unit 1304. The first AD interface unit 1301 and the second AD interface unit 1302 are respectively configured to receive digital signals output by the first AD chip and the second AD chip, and convert the digital signals from parallel to serial, where output interfaces of the first AD interface unit 1301 and the second AD interface unit are respectively connected to the AURORA sending unit, the AD data selecting unit, and the DDC algorithm unit.

In this embodiment, 256 paths of data output serially enter the AD data selecting unit 1304, an output interface thereof is connected to the data packing unit for selecting a specific number of paths of data to output to the data packing unit 1305, and at the same time, the 256 paths of data enter the DDC algorithm unit 1306 for down-conversion, and an output interface thereof is connected to the data packing unit and then output to the data packing unit 1307; data packing unit 1307, whose output interface is connected to the data transmission unit, packs the data that AD selection unit 1304 selects to pass and the data after down-conversion, and sends the data to data transmission unit 1308, where the data transmission unit is configured to output the data.

In this embodiment, the other 256 channels of the serial data output by the first AD receiving unit and the second AD receiving unit are sent to the AURORA sending unit 1303, where the other 256 channels are used for sending the serial data to the second FPGA140 according to the AURORA protocol, and in other embodiments, a plurality of parallel second FPGAs may be provided, where the second FPGAs are used for receiving more channels of serial data, so as to implement resource expansion;

the second FPGA chip includes: AURORA receiving unit 1401, AD data selecting unit 1402.

In this embodiment, 256 channels of data output serially enter the AD data selecting unit 1402, an output interface thereof is connected to the data packing unit for selecting a specific channel number of data to output to the data packing unit 1403, and at the same time, the 256 channels of data enter the DDC algorithm unit 1404 for down-conversion and then output to the data packing unit 1403, and an output interface thereof is connected to the data packing unit 1403; and a data packing unit 1403, an output interface of which is connected to the data transmission unit, and which packs the data that the AD selection unit 1402 selects to pass and the down-converted data and sends the packed data to a data transmission unit 1405, where the data transmission unit 1405 is configured to convert the data into a PCIE interface format and perform serial-to-parallel conversion, and then output the converted data.

In this embodiment, the data processing system further includes a DDR chipset for buffering data information of the FPGA data down conversion.

Optionally, the storage unit is a ROM memory.

While various embodiments of the present invention have been described above, the above description is intended to be illustrative, not exhaustive, and not limited to the disclosed embodiments. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments.

Claims

1. The utility model provides a many FPGA data processing integrated circuit boards which characterized in that includes: the clock chip is used for providing a reference clock for the circuit; the AD chip is used for sampling and carrying out analog-to-digital conversion on data according to a clock signal, and an output interface of the AD chip is connected with the first FPGA chip; the first FPGA chip is used for carrying out down-conversion on the digital signal after AD conversion and simultaneously transmitting the digital signal to the second FPGA chip according to a certain protocol, and one output interface of the first FPGA chip is connected with the second FPGA chip; wherein the content of the first and second substances,

the first FPGA chip includes:

the first AD interface unit and the second AD interface unit are used for receiving digital signals and converting the digital signals from parallel to serial, and output interfaces of the first AD interface unit and the second AD interface unit are respectively connected with the AURORA sending unit, the AD data selection unit and the DDC algorithm unit;

the AURORA sending unit is used for sending the serial data output by the first AD interface unit and the second AD interface unit to the second FPGA according to an AURORA protocol, and the output interface of the AURORA sending unit is connected with the second FPGA;

the AD data selection unit is used for selecting data of partial digit and outputting the data to the data packing unit, and an output interface of the AD data selection unit is connected with the data packing unit;

the data packing unit is used for packing and outputting the data of the digit selected by the AD data selection unit and the data after down-conversion, and an output interface of the data packing unit is connected with the data transmission unit;

the second FPGA chip includes:

the AD data selection unit is used for selecting data of partial digit and outputting the data to the data packaging unit, and an output interface of the AD data selection unit is connected with the data packaging unit;

2. The multi-FPGA data processing board card of claim 1, wherein the data transmission unit is configured to convert the frequency-converted digital signal into a PCIE interface format for output.

3. The multi-FPGA data processing board of claim 1, comprising a DDR chipset for buffering data information of the FPGA data down-conversion.

4. The multi-FPGA data processing board of claim 1, wherein the second FPGA chip is connected to an external upper computer via a PCIE bus.