CN111614355B - Data transmission device, analog-digital converter and radar system - Google Patents
Data transmission device, analog-digital converter and radar system Download PDFInfo
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- CN111614355B CN111614355B CN202010218147.3A CN202010218147A CN111614355B CN 111614355 B CN111614355 B CN 111614355B CN 202010218147 A CN202010218147 A CN 202010218147A CN 111614355 B CN111614355 B CN 111614355B
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- H—ELECTRICITY
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- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
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Abstract
The embodiment of the application discloses a data transmission device, an analog-to-digital converter and a radar system, which comprise: the N paths of LVDS interfaces are respectively connected with the first signal converter; the first signal converter is used for splitting one path of initial serial data into N sub-serial data; the N paths of LVDS interfaces are used for receiving N paths of sub-serial data in a one-to-one correspondence mode, converting each received sub-serial data into LVDS signals and outputting the LVDS signals, wherein the data transmission rate of the initial serial data is larger than the maximum working frequency of each path of low-voltage differential signal LVDS interface, and the data transmission rate of the sub-serial data is smaller than or equal to the maximum working frequency of each path of low-voltage differential signal LVDS interface. In the scheme, the data transmission device is used as an output device of LVDS data signals, and after splitting initial serial data into at least two sub-serial data, the data signal conversion and transmission are respectively carried out by utilizing N paths of LVDS interfaces, so that the data transmission rate can be effectively improved, and the data transmission accuracy can be effectively ensured.
Description
Technical Field
The embodiment of the application relates to the technical field of data transmission, in particular to a data transmission device, an analog-to-digital converter and a radar system.
Background
The Low-Voltage differential signal (Low-Voltage DIFFERENTIAL SIGNALING, LVDS)) is a level standard, and can be used as a high-speed signal transmission mode. The low-voltage differential signal technology is characterized in that extremely low voltage swing high-speed differential data is adopted, point-to-point or point-to-multipoint connection can be realized, low power consumption, low error rate, low crosstalk, low radiation and the like are realized.
LVDS technology can be used to output single bit (bit) data or sample single bit data input, but LVDS technology has a limitation of a highest operating frequency as a circuit for signal transmission. Because only one LVDS interface is provided in the conventional LVDS data transmission device, when the data frequency of the transmission exceeds the highest operating frequency of the LVDS interface, the LVDS data transmission device cannot ensure the accuracy of the transmitted data.
Disclosure of Invention
The application provides a data transmission device, an analog-to-digital converter and a radar system, which aim at the situation that the data transmission rate is larger than the maximum working frequency of a single LVDS interface in the data transmission device, and the accuracy of data transmitted by the data transmission device is effectively ensured by expanding the LVDS interface.
The application provides a data transmission device, which can comprise a first signal converter and N LVDS interfaces, wherein the N LVDS interfaces are respectively connected with the first signal converter; n is a positive integer (e.g., 2,3, 4,5, etc.), and N.gtoreq.2;
the first signal converter is used for splitting one path of initial serial data into N sub-serial data;
the N paths of LVDS interfaces are used for receiving the N sub-serial data in a one-to-one correspondence manner, and converting each received sub-serial data into LVDS signals for output;
The data transmission rate of the initial serial data is greater than the maximum working frequency of each path of low-voltage differential signal LVDS interface, and the data transmission rate of the sub serial data is less than or equal to the maximum working frequency of each path of LVDS interface.
In the embodiment of the application, the data transmission device is used as an output device of the LVDS data signals, after splitting the initial serial data with the data transmission rate larger than the maximum working frequency of each path of low-voltage differential signal LVDS interface into at least two paths of sub-serial data, the data signal conversion and transmission are respectively carried out by utilizing N paths of LVDS interfaces in one-to-one correspondence, so that the data transmission rate can be effectively improved, the data transmission speed of each path of sub-serial data can be ensured not to be larger than the maximum working frequency of each path of LVDS interface, and the data transmission accuracy can be further effectively ensured.
In an optional embodiment, the N-way LVDS interface is further configured to receive N-way LVDS serial data in a one-to-one correspondence, and convert each received LVDS serial data into the N-way serial data; and the first signal converter is further configured to combine the N-way serial data into one way of the initial serial data.
In the above embodiment, the data transmission device may further be used as an input device for LVDS data signals, and the N-way LVDS interfaces in one-to-one correspondence are used to perform data signal conversion and transmission respectively, and the first signal converter is used to combine the sub-serial data received by each LVDS interface into the initial serial data, so as to effectively increase the data transmission rate, and meanwhile, ensure that the data transmission rate of each sub-serial data is not greater than the maximum working frequency of each way LVDS interface, and further effectively ensure the accuracy of data transmission.
In an alternative embodiment, the data signal types of the initial serial data and the sub serial data are the same.
In an alternative embodiment, the serial data and the sub-serial data are non-LVDS signals, such as CMOS signals, etc.
In an alternative embodiment, the data transmission rate of each path of the sub-serial data is the same, and the maximum operating frequency of each path of the LVDS interface is the same. In other alternative embodiments, the data transmission rates of the sub-serial data in each path may be different or partially the same, and the maximum operating frequencies of the LVDS interfaces in each path may be different or partially the same, which may be determined according to practical requirements, so long as the overall transmission rate of the LVDS data can be improved, and meanwhile, each path of the LVDS interfaces also operates at or below the maximum operating frequency.
In an alternative embodiment, the data transmission rate of the initial serial data is N times the data transmission rate of each path of the sub serial data.
In an alternative embodiment, the data transmission device may further include a clock signal interface connected to the first signal converter; the first signal converter is further configured to obtain a clock signal of the initial serial data, and the clock signal interface is configured to receive and output the clock signal;
The clock signal is used for reading the initial serial data from the LVDS signals output by the N-path LVDS interfaces, and storing, processing or analyzing the initial serial data according to the clock signal.
In an alternative embodiment, the data transmission device may further include a second signal converter, where the second signal converter is connected to each path of the LVDS interface through the first signal converter;
The second signal converter is used for receiving initial parallel data, converting the initial parallel data into one path of initial serial data and sending the initial serial data to the first signal converter.
In an alternative embodiment, the data transmission device may further include an indication signal interface connected to the first signal converter;
The second signal converter is further configured to obtain a data mode indication signal of the initial parallel data, and output the data mode indication signal sequentially through the first signal converter and the indication signal interface; and
The data mode indication signal is used for converting the initial serial data read out from the LVDS signal into the initial parallel data, and carrying out operations such as storage, processing or analysis on the initial parallel data by combining the clock signal.
In an optional embodiment, when the first signal converter is further configured to combine the N-sub serial data into one path of the initial serial data, the data transmission apparatus further includes a third signal converter, where the third signal converter is connected to the first signal converter through each path of the LVDS interface, respectively;
The third signal converter is configured to convert one path of serial LVDS data into the N path of sub-serial data, and transmit the N path of serial LVDS data to the first signal converter through the N path of LVDS interface in a one-to-one correspondence.
The application also provides an analog-to-digital converter which can comprise the data transmission device according to any embodiment of the application.
The application also provides a radar system which can comprise the analog-to-digital converter according to any embodiment of the application and is used for outputting or receiving LVDS signals. The radar system may be a radar chip, such as a millimeter wave radar chip (e.g., an FMCW millimeter wave radar chip).
Drawings
Fig. 1 is a schematic structural diagram of a data transmission device provided by the present application;
Fig. 2 is a schematic structural diagram of a data transmission device according to the present application;
fig. 3 is a schematic structural diagram of a data transmission device according to the present application;
fig. 4 is a schematic structural diagram of a data transmission device according to the present application;
FIG. 5 is a schematic diagram of parallel data supported LVDS output signals provided by an embodiment of the application; ;
Fig. 6 is a schematic diagram of an embodiment of the present application for providing parallel data supported LVDS output signals at high frequencies.
Detailed Description
The application is described in further detail below with reference to the drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the application and are not limiting thereof. It should be noted that, for convenience of description, only some, but not all of the structures related to the present application are shown in the drawings, and furthermore, embodiments of the present application and features in the embodiments may be combined with each other without conflict.
Example 1
Fig. 1 is a schematic structural diagram of a data transmission device according to the present application, where the frequency of data transmission is greater than the highest operating frequency of a single LVDS interface in the data transmission device, so as to improve the accuracy of data transmitted by the data transmission device.
LVDS is a high-speed signal transmission mode, and is a level standard. The core of the LVDS technology is that extremely low voltage swing high-speed differential transmission data is adopted, point-to-point or point-to-multipoint connection can be realized, the characteristics of low power consumption, low error rate, low crosstalk, low radiation and the like are realized, and the LVDS technology is widely applied to different fields of broadband detection, electronic countermeasure and the like.
As shown in fig. 1, the data transmission device provided by the present application may include: a first signal converter 11, an N-way LVDS interface 12.
The N-path LVDS interfaces 12 are respectively connected with the first signal converter 11; n is a positive integer, and N is more than or equal to 2;
The first signal converter 11 is configured to split one path of initial serial data into N sub-serial data;
The N-way LVDS interface 12 is configured to receive N sub-serial data in a one-to-one correspondence, and convert each received sub-serial data into an LVDS signal for output; the data transmission rate of the initial serial data is greater than the maximum working frequency of each path of LVDS interface, and the data transmission rate of the sub serial data is less than or equal to the maximum working frequency of each path of low-voltage differential signal LVDS interface.
In this embodiment, the signal converter is a device for converting a signal. Further, the first signal converter 11 may be a device for splitting one path of serial data into N paths of serial data for outputting, or the first signal converter may be a device for combining N paths of serial data into one path of serial data for splitting and outputting. In the present embodiment, the type and model of the first signal converter are not limited, and only the signal converter will be described.
Further, the data signal types of the initial serial data and the sub serial data are the same.
Specifically, the serial data and the sub-serial data are non-LVDS signals.
Specifically, the non-LVDS signal is a CMOS signal.
Further, the N LVDS interfaces may be used to output LVDS signals, and may also be used to receive LVDS signals.
It should be noted that the N-way LVDS interface may be understood as having N LVDS interfaces, where N is a positive integer, and the number of LVDS interfaces may be determined according to the frequency of transmitting data and the maximum operating frequency of the single-way LVDS. The higher the frequency of data transmission, the lower the maximum operating frequency of the single-path LVDS, and the greater the number of interfaces needed for LVDS. The lower the frequency of data transmission, the higher the operating frequency of the single-pass LVDS, and the fewer the number of interfaces needed for LVDS.
In the case of 2 LVDS interfaces, for example, one path of serial data has M bits, the first signal converter splits the M-bit serial data into two paths of serial data, one path is the M/2 bit of the high bit, and the other path is the M/2 bit of the low bit, for example, the original path of serial data is 20 bits, (0110_0001_00_10_0001_1111), the high 10 bits (0110_0001_00) are split into one path, the low 10 bits (10_0001_1111) are split into one path, and the split path of serial data is respectively sent to the first path of LVDS interface and the second path of LVDS interface, and the first path of LVDS interface and the second path of LVDS interface respectively convert the received serial data into one-to-one corresponding LVDS signals for output.
Further, the N-way LVDS interface 12 is further configured to receive N-way LVDS serial data in a one-to-one correspondence manner, and convert each received LVDS serial data into N-way serial data; and
The first signal converter 11 is further configured to combine the N sub-serial data into one path of initial serial data.
For example, the 2 LVDS interfaces respectively receive two LVDS signals, and convert the two LVDS signals into 2-sub serial data, i.e., upper 10 bits (0110_0001_00) and lower 10 bits (10_0001_1111). The first signal converter 11 receives the upper 10 bits (0110_0001_00) transmitted by the first LVDS interface, and then receives the lower 10 bits (10_0001_1111) transmitted by the second LVDS interface, and combines them to obtain the original 20-bit serial data (0110_0001_00_10_0001_1111).
Further, the apparatus further includes a pad 13, where the pad 13 may be used to communicatively connect with an external device, so that the external device may read serial data, convert to parallel data, and perform various processing operations such as storing and analyzing the LVDS signal based on the clock signal and/or the indication signal.
The data transmission device provided by the embodiment of the application comprises: the N paths of LVDS interfaces are respectively connected with the first signal converter; the first signal converter is used for splitting one path of initial serial data into N sub-serial data; the N paths of LVDS interfaces are used for receiving N paths of sub-serial data in a one-to-one correspondence mode, converting each received sub-serial data into LVDS signals and outputting the LVDS signals, wherein the data transmission rate of the initial serial data is larger than the maximum working frequency of each path of low-voltage differential signal LVDS interface, and the data transmission rate of the sub-serial data is smaller than or equal to the maximum working frequency of each path of low-voltage differential signal LVDS interface.
In the scheme, the data transmission device is used as an output device of LVDS data signals, and after splitting initial serial data into at least two sub-serial data, the data signal conversion and transmission are respectively carried out by utilizing N paths of LVDS interfaces, so that the data transmission rate can be effectively improved, and the data transmission accuracy can be effectively ensured.
The data transmission device can also be used as an input device of LVDS data signals, utilizes N paths of LVDS interfaces in one-to-one correspondence to respectively convert and transmit the data signals, utilizes the first signal converter to combine sub-serial data received by each LVDS interface into initial serial data, effectively improves the data transmission rate, and can ensure that the data transmission speed of each sub-serial data is not larger than the maximum working frequency of each path of LVDS interface, thereby effectively ensuring the data transmission accuracy.
Example two
On the basis of the foregoing embodiment, the embodiment of the present application further provides a data conversion device, and fig. 2 is a schematic structural diagram of a data transmission device provided by the present application, as shown in fig. 2, where the data conversion device further includes: and a clock signal interface connected with the first signal converter.
The first signal converter is further configured to obtain a clock signal of the initial serial data, and the clock signal interface is configured to receive and output the clock signal; the clock signal is used for reading out the initial serial data from the LVDS signals output by the N-path LVDS interfaces.
The clock signal output end of the first signal converter is connected with the clock signal interface. The clock signal output end of the first signal converter outputs the clock signal of the acquired serial data to the clock signal interface, and the clock signal interface outputs the received clock signal.
As shown in fig. 2, the data conversion device further includes: an indication signal interface connected with the first signal converter; the second signal converter is further configured to obtain a data mode indication signal of the initial parallel data, and output the data mode indication signal sequentially through the first signal converter and the indication signal interface; and the data mode indication signal is used for converting the initial serial data read out from the LVDS signal into the initial parallel data.
The indication signal output end of the first signal converter is connected with the indication signal interface. The indication signal output end of the first signal converter outputs the obtained data mode indication signal of the serial data to the indication signal interface, and the indication signal interface outputs the received clock signal.
Example III
On the basis of the foregoing embodiment, the embodiment of the present application further provides a data conversion device, and fig. 3 is a schematic structural diagram of a data transmission device provided by the present application, as shown in fig. 3, where the data conversion device further includes: a second signal converter 14, where the second signal converter 14 is connected to each path of the LVDS interface through the first signal converter 11; the second signal converter 14 is configured to receive initial parallel data, convert the initial parallel data into one path of initial serial data, and send the one path of initial serial data to the first signal converter.
Further, the data conversion device further includes: the data source module 15 is configured to directly output the serial data as one-path serial data to the second signal converter if the serial data is received; if parallel data is received, the parallel data is converted into serial data and then output to the second signal converter 14 as one path of serial data.
In this embodiment, the data source module 15 may be understood as a module or a device that receives data. In the present embodiment, the data source module 15 performs different processing according to the received data format. If serial data is received, the serial data is directly output to the second signal converter. If parallel data is received, the parallel data is converted into serial data according to the data pattern indication frame signal and then output to the second signal converter 14.
In this embodiment, only the data source module is described, but not limited thereto, and an appropriate data source module may be selected or designed according to actual situations, which is not limited thereto.
Example IV
On the basis of the foregoing embodiment, the embodiment of the present application further provides a data conversion device, and fig. 4 is a schematic structural diagram of a data transmission device provided by the present application, as shown in fig. 4, where the data conversion device further includes: a third signal converter 16.
Wherein, when the first signal converter 11 is further used for merging the N-sub serial data into one path of initial serial data, the data transmission device further comprises a third signal converter 16, and the third signal converter 16 is connected to the first signal converter through each path of LVDS interfaces respectively; the third signal converter is used for converting one path of serial LVDS data into N paths of sub-serial data and transmitting the N paths of serial LVDS data to the first signal converter through N paths of LVDS interfaces in a one-to-one correspondence.
In this embodiment, first, description is given of a parallel data supported LVDS output signal mode, and fig. 5 is a schematic diagram of a parallel data supported LVDS output signal provided in an embodiment of the present application; as shown in fig. 5, the clock signal clock is a working clock signal indicating the synchronous sampling of the lower LVDS, and the data is a single bit data signal outputted by the LVDS interface, and since the LVDS is a differential signal, each output of the LVDS has positive and negative data. It should be noted that if the data received by the LVDS is parallel data, a mode indication signal frame is required. The mode indication signal frame is used to indicate how to restore the combined data to valid parallel data in a continuous serial output data stream.
Specifically, LVDS is only a data interface, if LVDS is used as an output port, generally, the CMOS level is converted into the LVDS level and then output, if the transmitted data is serial, the data is directly output, and a frame signal is not needed; if the data is parallel, the parallel data needs to be converted into serial data before being output, in which case a frame signal is required. Because if parallel data is input to LVDS, useful information can be obtained only by restoring serial data to parallel data.
FIG. 6 is a schematic diagram of an embodiment of the present application providing parallel data supported LVDS output signals at high frequency; the data pattern after LVDS output is shown in fig. 6 when the data frequency of the LVDS output becomes twice the data frequency in fig. 5. The clock signal clock is an operating clock signal for synchronous sampling of the lower LVDS, and the frequency is kept consistent with the clock signal of 5 in the figure. After the data frequency is doubled, the data frequency exceeds the highest frequency limit of LVDS at this time, the data in fig. 5 is split into two paths of output, the first path data1 and the second path data 2, and the frame still is a data mode indication signal, and the data mode indication signal frequency is doubled along with the doubling of the data frequency.
For example, if one serial data has N bits, it is split into two serial data, one is the high N/2 bit, and one is the low N/2 bit, for example, the original serial data is 20 bits, (0110_0001_00_10_0001_1111), the high 10 bits (0110_0001_00) are split into one, and the low 10 bits (10_0001_1111) are split into one, and after splitting, they are respectively sent to the first LVDS interface and the second LVDS interface for transmission.
The second signal converter 13 receives the upper 10 bits (0110_0001_00) transmitted by the first LVDS interface according to the data mode indication signal, and then receives the lower 10 bits (10_0001_1111) transmitted by the second LVDS interface, and combines the upper 10 bits and the lower 10 bits to obtain the original 20-bit serial data (0110_0001_00_10_0001_1111).
It should be noted that, if the serial data is N-way, the N-way LVDS interface requires at least n+2-way interfaces. One path of interface is used for transmitting data mode indication signals, one path of interface is used for transmitting clock signals, and the N path of interface is used for transmitting N paths of serial data.
Specifically, before the scheme of this embodiment is adopted, the LVDS interface is at least 3 paths, which are a serial data interface, a clock signal interface and a data mode indication signal interface respectively. In this embodiment, two paths of output are adopted, so that one path of interface needs to be added, and at least 4 paths of LVDS interfaces are respectively a first serial data interface, a second serial data interface, a clock signal interface and a data mode indication signal interface.
Further, if the data source module interfaces to parallel data, the last transmitted data is converted into parallel data. Parallel data reduction is determined from the data pattern indication signal frame. I.e. converting serial data into parallel data.
For example, if the data decoded from the data mode indication signal frame signal is a 20bit input, 0110_0001_00 is from one LVDS channel and 10_0001_1111 is from another LVDS channel, then the final data 0110_0001_00_10_0001_1111 is converted to 10 bits, i.e. 0*2^19+1*2^18+1*2^17+0*2^16+0*2^15+0*2^14+0*2^13+1*2^12+0*2^11+0*2^10+1*2^9+0*2^8+0*2^7+0*2^6+0*2^5+1*2^4+1*2^3+1*2^2+1*2^1+1*2^0.
The data reduction operation can be performed after the next stage of LVDS sampling. The LVDS of the receiving end is generally an LVDS interface on a PCB board or a testing instrument, has high speed, can meet the requirements, and is generally designed in a range which can be supported by the instrument or other chips.
On the basis of the above embodiments, an embodiment of the present application provides an analog-to-digital converter, which includes the data transmission device according to any one of the above embodiments.
The analog-to-digital converter provided by the embodiment of the application comprises the data transmission device provided by any embodiment of the application, and has corresponding functional modules and beneficial effects.
On the basis of the above embodiments, the embodiments of the present application provide a radar system, which includes an analog-to-digital converter as in the above embodiments, for outputting or receiving LVDS signals.
The radar system provided by the embodiment of the application comprises the data transmission device provided by any embodiment of the application, and has corresponding functional modules and beneficial effects.
LVDS-based data transmission has the advantages of high-speed data transmission, low power consumption, accurate time sequence positioning, strong noise resistance, electromagnetic interference resistance and the like, and is widely applied to various chip structures (such as communication chips, radar chips and the like) with analog-to-digital conversion requirements. However, in some special application scenarios, the chip needs to provide high-speed data sampling, so that the LVDS interface needs to transmit data exceeding the maximum operating frequency, that is, the transmitted data frequency is greater than the maximum operating frequency of the LVDS interface, at this time, the data accuracy of the LVDS transmission output cannot be effectively ensured, and meanwhile, the receiver of the LVDS cannot sample the correct data, which further affects the whole analog-digital conversion device, and even the normal operation of the whole chip.
The following will describe in detail a millimeter wave radar chip provided with an LVDS interface as an example:
As an alternative embodiment, the millimeter wave radar chip may be a radar chip based on FMCW waves.
It should be noted that, on the premise of not generating conflict, the technical content in the application embodiment can also be applied to various chip structures or other integrated circuit devices, as long as the LVDS interface is provided therein and the frequency of the transmitted data is greater than the LVDS maximum operating frequency, for example, the application can be a sensor chip such as a laser radar chip, various millimeter chips, and a communication chip (such as a millimeter wave communication chip). The data transmission method provided by the embodiment of the application is pointed by the data transmission device provided by any embodiment of the application, and has the functions and beneficial effects of corresponding modules.
Note that the above is only a preferred embodiment of the present application and the technical principle applied. It will be understood by those skilled in the art that the present application is not limited to the particular embodiments described herein, but is capable of various obvious changes, rearrangements and substitutions as will now become apparent to those skilled in the art without departing from the scope of the application. Therefore, while the application has been described in connection with the above embodiments, the application is not limited to the embodiments, but may be embodied in many other equivalent forms without departing from the spirit or scope of the application, which is set forth in the following claims.
Claims (11)
1. A data transmission apparatus, comprising: the device comprises a first signal converter and N paths of low-voltage differential signal LVDS interfaces, wherein the N paths of LVDS interfaces are respectively connected with the first signal converter; n is a positive integer, and N is more than or equal to 2;
the first signal converter is used for splitting one path of initial serial data into N sub-serial data;
the N paths of LVDS interfaces are used for receiving the N sub-serial data in a one-to-one correspondence manner, and converting each received sub-serial data into LVDS signals for output;
The data transmission rate of the initial serial data is greater than the maximum working frequency of each path of LVDS interface, and the data transmission rate of the sub serial data is less than or equal to the maximum working frequency of each path of LVDS interface;
The number N of the LVDS interfaces is determined according to the frequency of the initial serial data and the maximum working frequency of the single-path LVDS interfaces;
The data transmission device also outputs a data mode indication signal, wherein the data mode indication signal is used for representing the data serial-parallel correspondence between the initial serial data and N sub-serial data;
wherein the apparatus further comprises: the second signal converter is connected with each path of LVDS interfaces through the first signal converter respectively;
The second signal converter is used for receiving initial parallel data, converting the initial parallel data into one path of initial serial data and sending the initial serial data to the first signal converter;
Wherein the apparatus further comprises: an indication signal interface connected with the first signal converter;
The second signal converter is further configured to obtain a data mode indication signal of the initial parallel data, and output the data mode indication signal sequentially through the first signal converter and the indication signal interface; and
The data mode indication signal is used for converting the initial serial data read out from the LVDS signal into the initial parallel data.
2. The data transmission device of claim 1, wherein,
The N-path LVDS interfaces are also used for receiving N-path LVDS serial data in a one-to-one correspondence manner and converting each path of received LVDS serial data into the N-path sub-serial data; and
The first signal converter is further configured to combine the N-way serial data into one-way serial data.
3. A data transmission apparatus according to claim 1 or 2, wherein the data signal types of the initial serial data and the sub serial data are the same.
4. A data transmission device according to claim 3, wherein the serial data and the sub-serial data are non-LVDS signals.
5. The data transmission device of claim 4, wherein the non-LVDS signal is a CMOS signal.
6. The data transmission device according to claim 1 or 2, wherein the data transmission rate of each of the sub-serial data is the same, and the maximum operating frequency of each of the LVDS interfaces is the same.
7. The data transmission apparatus according to claim 6, wherein the data transmission rate of the initial serial data is N times the data transmission rate of each of the sub-serial data.
8. The data transmission apparatus according to claim 1 or 2, characterized by further comprising: a clock signal interface connected to the first signal converter; the first signal converter is further configured to obtain a clock signal of the initial serial data, and the clock signal interface is configured to receive and output the clock signal;
the clock signal is used for reading out the initial serial data from the LVDS signals output by the N-path LVDS interfaces.
9. The data transmission apparatus according to claim 8, wherein when the first signal converter is further configured to combine the N-sub serial data into one path of the initial serial data, the data transmission apparatus further comprises third signal converters connected to the first signal converter through the respective paths of the LVDS interfaces;
The third signal converter is configured to convert one path of serial LVDS data into the N path of sub-serial data, and transmit the N path of serial LVDS data to the first signal converter through the N path of LVDS interface in a one-to-one correspondence.
10. An analog-to-digital converter comprising a data transmission apparatus as claimed in any one of claims 1 to 9.
11. A radar system comprising an analog to digital converter according to claim 10 for outputting or receiving LVDS signals.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010218147.3A CN111614355B (en) | 2020-03-25 | 2020-03-25 | Data transmission device, analog-digital converter and radar system |
Applications Claiming Priority (1)
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