CN117420879A - FMC+ based high-speed acquisition daughter card - Google Patents
FMC+ based high-speed acquisition daughter card Download PDFInfo
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- CN117420879A CN117420879A CN202311329563.0A CN202311329563A CN117420879A CN 117420879 A CN117420879 A CN 117420879A CN 202311329563 A CN202311329563 A CN 202311329563A CN 117420879 A CN117420879 A CN 117420879A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
- G06F1/12—Synchronisation of different clock signals provided by a plurality of clock generators
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
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Abstract
The embodiment of the invention discloses a high-speed acquisition daughter card based on FMC+; the device comprises an analog input module, a digital input module and a digital output module, wherein the analog input module is used for inputting analog signals; the signal conditioning circuit is used for conditioning an input analog signal into a standard signal which accords with the input of the ADC; the ADC acquisition module is used for converting the standard signals into digital signals and transmitting the digital signals to the carrier plate; and (3) a clock module: the sampling clock is used for providing sampling clocks for the ADC acquisition modules respectively, and the carrier plate provides a link clock. The invention adopts a low-jitter clock generation circuit, is matched with a signal conditioning circuit and a low-noise power supply technology to realize higher SNR and SFDR performances and synchronization performances, and the board card adopts an FMC+ architecture design, thereby having wide applicability.
Description
Technical Field
The present invention relates to the field of communications and electronic measurements. And more particularly to a fmc+ based high speed acquisition daughter card.
Background
Currently, an electronic measurement test system generally comprises three parts, namely data acquisition, data processing and display control. The data acquisition is a basic means for acquiring information, and it acquires external analog signals and converts them into digital signals which can be identified by a computer, then sends them into a signal processing system, and makes corresponding calculation and processing according to the need so as to obtain the required result. With the development of modern electronic information technology, the measurement of high-speed transient signals is becoming more and more important, for example, in the fields of image processing, satellite remote sensing, radar measurement and the like, which all relate to high-frequency signals, and high-speed or ultra-high-speed data acquisition must be adopted to accurately record data so as to analyze the data.
In the VPX system, the mezzanine card is an effective and widely used method for adding specific functions to the embedded system, and has the advantage of flexible configuration. The FMC+ accords with the VITA57.4 standard, and on the basis of the original FMC standard function, the function of the existing FMC standard is expanded by greatly enhancing the function of the gigabit serial interface, and the FMC+ daughter card is gradually and widely applied in the aspects of diversity, flexibility, high performance and the like. According to different application environments, corresponding data acquisition functions and index requirements are different, and the traditional acquisition board has single function, large volume, poor flexibility and some inconvenience in use.
Disclosure of Invention
The invention aims to provide a high-speed acquisition daughter card based on FMC+ so as to solve at least one of the problems existing in the prior art.
In order to achieve the above purpose, the invention adopts the following technical scheme:
the invention provides a high-speed acquisition sub-card based on FMC+, which is used for being matched with a carrier plate, and comprises the following components:
the analog input module is used for inputting analog signals;
the signal conditioning circuit is used for conditioning an input analog signal into a standard signal which accords with the input of the ADC;
the ADC acquisition module is used for converting the standard signals into digital signals and transmitting the digital signals to the carrier plate;
and the clock module is used for providing sampling clocks for the ADC acquisition modules respectively and providing link clocks for the carrier plate.
Optionally, the device further comprises an FMC+ connector for transmitting data interacted between the high-speed acquisition sub-card and the carrier plate.
Optionally, the high-speed acquisition daughter card receives the reference clock signal of the carrier board through the fmc+ connector and transmits the reference clock signal to the clock module.
Optionally, the clock module is configured to provide 2 paths of CORECLK and SYSREF clock pairs for the carrier board; and is also configured to provide 1 set of adc_clk and SYSREF clock pairs, respectively, to the ADC acquisition module.
Optionally, the signal conditioning circuit comprises
A first resistor, a second resistor, a third resistor, a fourth resistor, a fifth resistor, a transformer, a sixth resistor, a seventh resistor, a ninth resistor, a tenth resistor, a first capacitor, a second capacitor, an eighth capacitor, a ninth capacitor, and a seventeenth capacitor;
the first end of the fifth resistor is input with an analog signal, and the second end of the fifth resistor is connected with a sixth pin of the transformer;
the fourth pin of the transformer is grounded, and the second pin and the first end of the ninth capacitor are connected with the second end of the ninth capacitor;
the first end of the third resistor is connected with the first pin of the transformer, the second end of the third resistor is connected with the first end of the sixth resistor, and the first end of the eighth capacitor is connected with the first end of the eighth capacitor;
the first end of the second resistor is connected with the third pin of the transformer, the second end of the second resistor is connected with the second end of the first resistor, and the first end of the seventeenth capacitor is connected;
the second end of the sixth resistor is connected with the first end of the first resistor and the first end of the sixteenth capacitor; the second end of the sixteenth capacitor is grounded;
the first end of the fourth resistor is connected with the second end of the eighth capacitor, the first end of the first capacitor and the first end of the second capacitor, and the second end of the fourth resistor is connected with the input end of the ADC;
a seventh resistor, the first end of which is connected with the second end of the seventeenth capacitor, the first end of the sixth capacitor and the second end of the second capacitor, and the second end of which is connected with the input end of the ADC;
the second end of the first capacitor and the second end of the sixth capacitor are grounded.
Optionally, the ADC acquisition module communicates with the carrier plate via JESD204B protocol.
Optionally, the high-speed acquisition daughter card performs signal interaction with the carrier board through an FMC+ standard protocol.
Optionally, the carrier configures the ADC acquisition module and the clock module through an SPI protocol.
Optionally, the clock module employs a low jitter clock canceller chip HMC7044, while cooperating with an external VCXO, to achieve an output clock jitter of a minimum of 44 fs.
Optionally, the clock signal length error between the HMC7044 chip and each high-speed ADC acquisition circuit is less than 5mil, and when the clock signal is input to the receiving end of the ADC acquisition circuit, the clock signal needs to be ac-coupled and then enters the ADC acquisition circuit, so as to ensure clock synchronization and signal output quality.
The beneficial effects of the invention are as follows:
the invention adopts a low-jitter clock generation circuit, is matched with a signal conditioning circuit and a low-noise power supply technology to realize higher SNR and SFDR performances and synchronization performances, and the board card adopts an FMC+ architecture design, thereby having wide applicability.
Drawings
The following describes the embodiments of the present invention in further detail with reference to the drawings.
FIG. 1 illustrates an exemplary block diagram of a structure in which an embodiment of the present invention may be applied.
Fig. 2 shows a circuit diagram of the signal conditioning module of the present invention.
Fig. 3 shows a functional block diagram of a clock module of the present invention.
Fig. 4 shows a graph of SNR versus clock jitter for the present invention.
Fig. 5 shows a functional block diagram of a level shifter circuit embodying the present invention.
Detailed Description
In order to more clearly illustrate the present invention, the present invention will be further described with reference to examples and drawings. Like parts in the drawings are denoted by the same reference numerals. It is to be understood by persons skilled in the art that the following detailed description is illustrative and not restrictive, and that this invention is not limited to the details given herein.
The invention provides a high-speed acquisition sub-card based on FMC+, which is used for being matched with a carrier plate, and comprises the following components:
the analog input module is used for inputting analog signals;
the signal conditioning circuit is used for conditioning an input analog signal into a standard signal which accords with the input of the ADC;
the ADC acquisition module is used for converting the standard signals into digital signals and transmitting the digital signals to the carrier plate;
and the clock module is used for providing sampling clocks for the ADC acquisition modules respectively and providing link clocks for the carrier plate.
Optionally, the device further comprises an FMC+ connector for transmitting data interacted between the high-speed acquisition sub-card and the carrier plate.
Optionally, the high-speed acquisition daughter card receives the reference clock signal of the carrier board through the fmc+ connector and transmits the reference clock signal to the clock module.
Optionally, the clock module is configured to provide 2 paths of CORECLK and SYSREF clock pairs for the carrier board; and is also configured to provide 1 set of adc_clk and SYSREF clock pairs, respectively, to the ADC acquisition module.
Optionally, the signal conditioning circuit comprises
A first resistor, a second resistor, a third resistor, a fourth resistor, a fifth resistor, a transformer, a sixth resistor, a seventh resistor, a ninth resistor, a tenth resistor, a first capacitor, a second capacitor, an eighth capacitor, a ninth capacitor, and a seventeenth capacitor;
the first end of the fifth resistor is input with an analog signal, and the second end of the fifth resistor is connected with a sixth pin of the transformer;
the fourth pin of the transformer is grounded, and the second pin and the first end of the ninth capacitor are connected with the second end of the ninth capacitor;
the first end of the third resistor is connected with the first pin of the transformer, the second end of the third resistor is connected with the first end of the sixth resistor, and the first end of the eighth capacitor is connected with the first end of the eighth capacitor;
the first end of the second resistor is connected with the third pin of the transformer, the second end of the second resistor is connected with the second end of the first resistor, and the first end of the seventeenth capacitor is connected;
the second end of the sixth resistor is connected with the first end of the first resistor and the first end of the sixteenth capacitor; the second end of the sixteenth capacitor is grounded;
a fourth resistor having a first end connected to the second end of the eighth capacitor, the first end of the first capacitor, the first end of the second capacitor, and a second end output connected to the input end of the ADC
A seventh resistor having a first end connected to the second end of the seventeenth capacitor, the first end of the sixth capacitor, and the second end of the second capacitor, and a second end output connected to the input end of the ADC
The second end of the first capacitor and the second end of the sixth capacitor are grounded.
Optionally, the ADC acquisition module communicates with the carrier plate via JESD204B protocol.
Optionally, the high-speed acquisition daughter card performs signal interaction with the carrier board through an FMC+ standard protocol.
Optionally, the carrier configures the ADC acquisition module and the clock module through an SPI protocol.
Optionally, the clock module employs a low jitter clock canceller chip HMC7044, while cooperating with an external VCXO, to achieve an output clock jitter of a minimum of 44 fs.
Optionally, the clock signal length error between the HMC7044 chip and each high-speed ADC acquisition circuit is less than 5mil, and when the clock signal is input to the receiving end of the ADC acquisition circuit, the clock signal needs to be ac-coupled and then enters the ADC acquisition circuit, so as to ensure clock synchronization and signal output quality.
According to the invention, the signal conditioning circuit is used for converting the broadband signals input through simulation into the differential level meeting the requirements of the ADC chips, the two ADC chips respectively realize conversion from 2 paths of broadband analog signals to digital signals, and the ADC chips are used for transmitting the converted high-speed data to the processor on the carrier board through the JESD204B interface through the FMC+ connector, so that the transmission rate as high as 12Gsps can be realized. The root mean square jitter of the clock chip is smaller than 100fs, which is very beneficial to improving the signal to noise ratio of the ADC and meeting the synchronism of the ADC. Aiming at multichannel high-speed signal acquisition under a VPX architecture, the invention provides a novel architecture and an implementation method, and has the advantages of high bandwidth, high speed, high integration level, strong flexibility and the like.
Example 1
In this embodiment, the analog input module: the invention adopts the mode of SSMP interface to realize the input of analog signals. The SSMP interface is a coaxial radio frequency connector, and a 4-path SSMP interface is designed according to the actual channel number of the ADC acquisition module.
The main functions of the signal conditioning circuit include balun, front-end filtering, ac coupling, and impedance matching, as shown in fig. 2. The analog signals are converted into standard signals through the signal conditioning circuit and then transmitted to the ADC acquisition module.
The ADC acquisition module is realized by adopting an AD9689, the AD9689 is a double-channel, 14-bit and 2GSPS/2.6GSPS analog-to-digital converter (ADC), an on-chip buffer and a sample hold circuit are arranged in the ADC, the bandwidth of the analog input-3 dB is 9GHz, and the direct sampling of the broadband analog signal up to 5GHz can be realized. The JESD204B interface is supported, has 8 high-speed serial output channels, and can be flexibly configured, and depends on the DDC configuration of a receiving device and the receiving channel rate. The invention adopts 2.4GSPS sampling rate to realize direct sampling of the analog broadband signal with 1.8G input center frequency and 1G bandwidth. Logic devices on the carrier board realize the configuration of the AD9689 through an SPI interface.
The invention adopts FMC+ standard protocol to complete signal and data transmission between the card carrier and the sub-card. The FMC+ standard is backwards compatible with the current FMC standard, the maximum single-ended signal rate is improved from 10Gbps to 28Gbps, the total number of Gigabit Transceivers (GT) in the FMC+ standard is expanded from 10 to 32, and extra protocol overhead is not needed, so that delay is eliminated, data transmission is ensured, system design is simplified, and power consumption, engineering time and material cost can be reduced. The selected FMC+ connector model of the invention is ASP-184330-01.
Example 2
The signal-to-noise ratio (SNR) of a high-speed ADC is very sensitive to sample clock jitter and therefore, stringent requirements are placed on the quality of the ADC sample clock. To meet the signal-to-noise ratio of the ADC, a clock source with very good jitter performance needs to be selected. The relationship between the ideal SNR of the high-speed ADC and the input signal, sampling rate is shown in equation 1:
SNR JRMS ＝-20×log(2×π×f in ×t JRMS ) (1)
wherein f in Is the highest frequency of the input signal, t JRMS In this example, the frequency of the analog input signal is 2.3G at the highest, the sampling clock is 2.4G, the required SNR is not less than 50dB, the required clock jitter calculated according to the formula 1 cannot be greater than 214fs, HMC7044 is adopted as a low-jitter clock generating chip, and HMC7044 can provide the output clock jitter of the lowest 44fs, thereby completely meeting the requirements of the daughter card.
In this embodiment, as shown in fig. 3, the clock module uses HMC7044 as a clock chip, where HMC7044 can provide 14 low-noise configurable outputs, which can generate 7 sets of DCLK and SYSREF clock pairs meeting the JESD204B interface requirements, and both DCLK and SYSREF clock outputs can be configured to support different signal standards such as CML, LVDS, LVPECL and LVCMOS, and different bias conditions can adjust the variable board insertion loss. The invention requires the generation of 4 sets of DCLK and SYSREF clock pairs through HMC7044, two sets for distribution to the ADC chips for use as clock inputs for two pieces of AD9689, and two sets for transmission to the carrier board through fmc+ connectors.
The method comprises the steps of firstly receiving a reference clock provided by a carrier board through an FMC+ connector, then sending the reference clock to a reference input end of a first-stage PLL of an HMC7044, after noise reduction through the first-stage PLL, outputting an analog quantity to control an external VCXO, adjusting the output precision of the VCXO, then outputting a 100M clock to an input end OSC_IN_P/N of a second-stage PLL through the second-stage PLL, multiplying a 2.4G clock, then outputting the clock to an ADC as a sampling clock after frequency division, analog delay and other functional modules, simultaneously calculating a nuclear clock required by a receiving device on the carrier board according to the JESD204B link rate of the ADC, obtaining a correct nuclear clock frequency through configuring a corresponding channel frequency divider coefficient, and transmitting the nuclear clock to the receiving device on the carrier board through the FMC+ connector. In addition, a path of SYSREF clock is provided for the ADC and the receiving device respectively for JESD204B link synchronization, and the frequencies of the SYSREF clock and the JESD204B link synchronization are the same, and the SYSREF clock is obtained by configuring the frequency divider coefficient of the SDCLKOUT channel of the HMC 7044. The sampling clock and SYSREF clock of the ADC adopt LVPECL level standard, the sampling clock and SYSREF clock are sent to the ADC chip after AC coupling, and the logic device core clock and SYSREF clock on the carrier board generally adopt LVDS level standard. In addition, the HMC7044 provides a reference clock for the high-speed serial transceiver to the logic devices on the carrier board through the fmc+ connector, and the clock frequency is flexibly configured according to the requirements.
Example 3
In this embodiment, the fmc+ connector receives the SPI signal provided by the carrier board, and is used to perform read-write configuration on two pieces of AD9689, and the level standard is LVCMOS1.8V. In addition, the fmc+ connector receives another path of SPI signal provided by the carrier board, and is used for performing read-write configuration on the clock chip HMC7044, the level standard of the SPI interface of HMC7044 is LVCMOS 3.3V, in order to maintain the consistency of the external interface, the level of the SPI signal of HMC7044 is converted into LVCMOS1.8V by a level conversion chip ADG3308, and the functional block diagram of the level conversion circuit is shown in fig. 5. ADG3308 is a bidirectional level shifter with 8 bidirectional channels built in, which can be used for multi-voltage digital systems, such as data transmission between low-voltage DSP controller and high-voltage devices, and the internal structure of the devices allows bidirectional level shifting to be performed without the need to set the shifting direction by means of additional signals.
In the description of the present invention, it should be noted that the azimuth or positional relationship indicated by the terms "upper", "lower", etc. are based on the azimuth or positional relationship shown in the drawings, and are merely for convenience of describing the present invention and simplifying the description, and are not indicative or implying that the apparatus or element in question must have a specific azimuth, be constructed and operated in a specific azimuth, and thus should not be construed as limiting the present invention. Unless specifically stated or limited otherwise, the terms "mounted," "connected," and "coupled" are to be construed broadly, and may be, for example, fixedly connected, detachably connected, or integrally connected; can be mechanically or electrically connected; can be directly connected or indirectly connected through an intermediate medium, and can be communication between two elements. The specific meaning of the above terms in the present invention can be understood by those of ordinary skill in the art according to the specific circumstances.
It is further noted that in the description of the present invention, relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.
It should be understood that the foregoing examples of the present invention are provided merely for clearly illustrating the present invention and are not intended to limit the embodiments of the present invention, and that various other changes and modifications may be made therein by one skilled in the art without departing from the spirit and scope of the present invention as defined by the appended claims.
Claims (10)
1. The utility model provides a high-speed collection daughter card based on FMC+, its characterized in that, high-speed collection daughter card includes:
the analog input module is used for inputting analog signals;
the signal conditioning circuit is used for conditioning an input analog signal into a standard signal which accords with the input of the ADC;
the ADC acquisition module is used for converting the standard signals into digital signals and transmitting the digital signals to the carrier plate;
and the clock module is used for providing sampling clocks for the ADC acquisition modules respectively and providing link clocks for the carrier plate.
2. The high-speed acquisition daughter card of claim 1 further comprising an fmc+ connector for transmitting data interacted between the high-speed acquisition daughter card and the carrier.
3. The high-speed acquisition daughter card of claim 2 wherein the high-speed acquisition daughter card receives the reference clock signal of the carrier board via the fmc+ connector and transmits the reference clock signal to the clock module.
4. A high-speed acquisition daughter card as claimed in claim 3 wherein said clock module is adapted to provide 2 pairs of CORECLK and SYSREF clocks to the carrier; and is also configured to provide 1 set of adc_clk and SYSREF clock pairs, respectively, to the ADC acquisition module.
5. The high-speed acquisition daughter card of claim 1 wherein said signal conditioning circuit comprises
A first resistor, a second resistor, a third resistor, a fourth resistor, a fifth resistor, a transformer, a sixth resistor, a seventh resistor, a ninth resistor, a tenth resistor, a first capacitor, a second capacitor, an eighth capacitor, a ninth capacitor, and a seventeenth capacitor;
the first end of the fifth resistor is input with an analog signal, and the second end of the fifth resistor is connected with a sixth pin of the transformer;
the fourth pin of the transformer is grounded, and the second pin and the first end of the ninth capacitor are connected with the second end of the ninth capacitor;
the first end of the third resistor is connected with the first pin of the transformer, the second end of the third resistor is connected with the first end of the sixth resistor, and the first end of the eighth capacitor is connected with the first end of the eighth capacitor;
the first end of the second resistor is connected with the third pin of the transformer, the second end of the second resistor is connected with the second end of the first resistor, and the first end of the seventeenth capacitor is connected;
the second end of the sixth resistor is connected with the first end of the first resistor and the first end of the sixteenth capacitor; the second end of the sixteenth capacitor is grounded;
the first end of the fourth resistor is connected with the second end of the eighth capacitor, the first end of the first capacitor and the first end of the second capacitor, and the second end of the fourth resistor is connected with the input end of the ADC;
a seventh resistor, the first end of which is connected with the second end of the seventeenth capacitor, the first end of the sixth capacitor and the second end of the second capacitor, and the second end of which is connected with the input end of the ADC;
the second end of the first capacitor and the second end of the sixth capacitor are grounded.
6. The high-speed acquisition daughter card of claim 1 wherein the ADC acquisition module communicates with the carrier plate via JESD204B protocol.
7. The high-speed acquisition daughter card of claim 1, wherein the high-speed acquisition daughter card interacts with the carrier board via fmc+ standard protocol.
8. The high-speed acquisition daughter card of claim 1 wherein the carrier configures the ADC acquisition module and the clock module via an SPI protocol.
9. The high-speed acquisition daughter card of claim 1 wherein the clock module employs a low jitter clock canceller chip HMC7044, in conjunction with an external VCXO, to achieve an output clock jitter of a minimum of 44 fs.
10. The high-speed acquisition daughter card of claim 9 wherein the clock signal length error between the low jitter clock canceller chip HMC7044 and each high-speed ADC acquisition circuit is less than 5 mils and the clock signal is input to the ADC acquisition circuit receiving end before being ac coupled to the ADC acquisition circuit to ensure clock synchronization and signal output quality.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202311329563.0A CN117420879A (en) | 2023-10-13 | 2023-10-13 | FMC+ based high-speed acquisition daughter card |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202311329563.0A CN117420879A (en) | 2023-10-13 | 2023-10-13 | FMC+ based high-speed acquisition daughter card |
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| CN117420879A true CN117420879A (en) | 2024-01-19 |
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| CN202311329563.0A Pending CN117420879A (en) | 2023-10-13 | 2023-10-13 | FMC+ based high-speed acquisition daughter card |
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