CN109600560A - Cmos image sensor exports high speed serialization LVDS signal calibration method and device - Google Patents
Cmos image sensor exports high speed serialization LVDS signal calibration method and device Download PDFInfo
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- H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
- H04N25/70—SSIS architectures; Circuits associated therewith
- H04N25/76—Addressed sensors, e.g. MOS or CMOS sensors
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- H04N23/00—Cameras or camera modules comprising electronic image sensors; Control thereof
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Abstract
The present invention relates to a kind of improved cmos image sensor output high speed serialization LVDS signal calibration method and devices, cmos image sensor exports the serial LVDS of multi-channel high-speed " calibrating sequence ", receiving end carries out difference to the multi-channel serial LVDS signal received and turns single-ended, delay adjustment, 1:8 serioparallel exchange, complete the phase alignment of image pixel clock and data, image pixel clock samples in the middle position of image data eye figure, and receiving end is made correctly to restore " calibrating sequence "；Whether the eye figure width for calculating current image date in real time meets LVDS signal eye diagram width minimum requirement, channel signal calibration is carried out if meeting the requirements, it is on the contrary then continue current channel signal calibration, after guaranteeing that all channel serial LVDS signal calibrations are completed, when ambient temperature and signal voltage fluctuation cause serial LVDS signal eye diagram to change, receiving end can reliably restore digital image data.
Description
Technical field
The invention belongs to field of image processings, are related to a kind of improved cmos image sensor output high speed serialization LVDS letter
Number calibration method and device.
Background technique
Current digital image signal transmission form can be divided into parallel and serial transmission two ways.But with digitized map
As the raising of pixel clock frequency and message transmission rate, parallel transmission mode is caused vulnerable to transmission medium and external interference
In digital picture receiving end Data reception errors.
Low-voltage differential signal (LVDS) serial transfer techniques have high-speed, low-power consumption, low noise and low EMI
The advantages that, it is widely used in the transmission of high-speed figure picture signal.But high speed serialization LVDS picture signal is calibrated
Method causes receiving terminal circuit plate to complete being followed by for LVDS signal calibration vulnerable to ambient temperature and signal voltage influence of fluctuations
Receiving end still can not correctly restore digital image data.
To solve the above-mentioned problems, spy proposes a kind of improved cmos image sensor output high speed serialization LVDS signal school
Quasi- method, the parameter for using high speed serialization LVDS picture signal eye figure width data to calibrate as LVDS picture signal, improves
The environmental suitability of signal calibration method.
Summary of the invention
Technical problems to be solved
In order to avoid the shortcomings of the prior art, the present invention proposes a kind of improved cmos image sensor output high speed
Serial LVDS signal calibration method and device, can be improved serial LVDS signal calibration method environmental suitability.
Technical solution
A kind of improved cmos image sensor output high speed serialization LVDS signal calibration method, it is characterised in that step is such as
Under:
Step 1, difference turn single-ended: the multichannel LVDS differential signal for first exporting front end cmos image sensor is converted
For single-ended signal；The multichannel LVDS differential signal includes image synchronization, clock and data differential signals；
Step 2, delay adjustment: the retardation provided according to phase delay signal delay_number adjusts each channel
The phase delay magnitude of single-ended signal, so that the phase for exporting each channel single-ended signal is consistent；
The phase delay signal delay_number: single-ended signal and " calibrating sequence " of setting are compared, obtained
The phase delay magnitude that should be adjusted to single-ended signal；
Step 3, serioparallel exchange: by the serial single-ended signal after phase adjustment in the ratio of 1:8, basis signal bit_slip
Be converted to 8 parallel-by-bit single ended data of low speed；
The bit that the signal bit_slip controls 8 bit parallel datas puts in order, and the generation of signal bit_slip is: will
Single-ended signal and " calibrating sequence " of setting are compared, if not identical sending bit reversal signal, if identical, calculating is worked as
The eye figure width width of prepass data；
Step 4: by the eye figure width minimum width_min ratio of eye figure width width and the current channel data prestored
Compared with, work as width >=width_min, then current channel phase alignment complete；
As width < width_min, then current channel phase alignment fails, and repeats step 2~step 3；
Step 5: after the parallel single ended data phase alignment success of first passage, carrying out the parallel single ended data phase of second channel
Position alignment, repeats step 2~step 4.
A kind of device for realizing the improved cmos image sensor output high speed serialization LVDS signal calibration method,
It is characterized in that including that difference turns single-ended block, delay adjustment module, serioparallel exchange module, channel selecting module, phase alignment mould
Block and LVDS signal eye diagram width data module；It is input terminal that difference, which turns single-ended block, and front end cmos image sensor is exported
Multichannel LVDS differential signal be converted to single-ended signal；It, which is exported, is sequentially connected in series delay adjustment module, serioparallel exchange module, leads to
Road selecting module and phase alignment module；Delay adjustment module, the feedback signal delay_ according to rear end phase alignment module
Number adjusts the phase delay magnitude of each channel single-ended signal, output to serioparallel exchange module in real time；Serioparallel exchange module
Feedback letter by the high speed serialization single-ended signal of delay adjustment module output in the ratio of 1:8, according to rear end phase alignment module
Number bit_slip is converted to 8 parallel-by-bit single ended data of low speed and exports to channel selecting module；Channel selecting module controls phase pair
Each channel data is sequentially output phase alignment module by the selector channel of neat module, phase alignment module by single ended data with
After pre-set " calibrating sequence " compares, phase adjustment feedback signal delay_number is issued to delay adjustment module, to
Serioparallel exchange module issues bits switch feedback signal bit_slip, and calculates the LVDS signal eye diagram width data being adjusted in place
And it exports；LVDS signal eye diagram width data module provides each channel LVDS signal obtained by measurement in high and low temperature environment
The minimum value of lower eye figure width data.
Beneficial effect
A kind of improved cmos image sensor output high speed serialization LVDS signal calibration method and dress proposed by the present invention
It sets, cmos image sensor exports the serial LVDS of multi-channel high-speed " calibrating sequence ", and receiving end is to the multi-channel serial received
LVDS signal carries out difference and turns single-ended, delay adjustment, 1:8 serioparallel exchange, completes the phase alignment of image pixel clock and data,
Image pixel clock samples in the middle position of image data eye figure, and receiving end is made correctly to restore " calibrating sequence "；Meter in real time
Whether the eye figure width for calculating current image date meets LVDS signal eye diagram width minimum requirement, and one is carried out if meeting the requirements
Lower channel signal calibration, it is on the contrary then continue current channel signal calibration, guarantee that all channel serial LVDS signal calibrations complete it
Afterwards, when ambient temperature and signal voltage fluctuation cause serial LVDS signal eye diagram to change, receiving end can be reliable
Restore digital image data.
Advantages of the present invention: high speed serialization LVDS picture signal eye figure width data is used, to improve serial LVDS signal
Calibration method environmental suitability.This method occupancy FPGA resource is few, and real-time is good, is easy to FPGA realization.Environmental suitability is strong,
When ambient temperature changes, serial LVDS picture signal receiving end remains to reliably restore digital image data.
Detailed description of the invention
Fig. 1: being algorithm flow of the invention.
Specific embodiment
Now in conjunction with embodiment, attached drawing, the invention will be further described:
Realize the device of improved cmos image sensor output high speed serialization LVDS signal calibration method, it is characterised in that
Turn single-ended block, delay adjustment module, serioparallel exchange module, channel selecting module, phase alignment module and LVDS including difference
Signal eye diagram width data module；It is input terminal, the multichannel that front end cmos image sensor is exported that difference, which turns single-ended block,
LVDS differential signal is converted to single-ended signal；It, which is exported, is sequentially connected in series delay adjustment module, serioparallel exchange module, channel selecting mould
Block and phase alignment module；Delay adjustment module, according to the feedback signal delay_number of rear end phase alignment module, in real time
Adjust the phase delay magnitude of each channel single-ended signal, output to serioparallel exchange module；Serioparallel exchange module adjusts delay
Ratio of the high speed serialization single-ended signal of module output in 1:8, the feedback signal bit_slip of foundation rear end phase alignment module
8 parallel-by-bit single ended data of low speed is converted to export to channel selecting module；The choosing of channel selecting module control phase alignment module
Select channel, each channel data be sequentially output phase alignment module, phase alignment module by single ended data with it is pre-set
After " calibrating sequence " compares, phase adjustment feedback signal delay_number is issued to delay adjustment module, to serioparallel exchange mould
Block issues bits switch feedback signal bit_slip, and calculates the LVDS signal eye diagram width data being adjusted in place and export；
LVDS signal eye diagram width data module provides each channel LVDS signal obtained by measurement eye figure under high and low temperature environment
The minimum value of width data.
Realize that steps are as follows:
(a) difference turns single-ended: the multichannel LVDS differential signal that first exports front end cmos image sensor (including figure
As synchronous, clock and data differential signals) feeding difference turns single-ended block and is converted to single-ended signal, such as a pair of of differential clocks are
Clk_p and clk_n is converted to single-ended clock signal clk；
(b) delay adjustment: due to front end cmos image sensor output multichannel LVDS differential signaling path not
Together, the multi channel signals phase for causing fpga chip to receive is inconsistent, may cause data sampling mistake, it is therefore desirable to will be more
Channel single-ended signal is sent into delay adjustment module, according to the feedback signal delay_number of rear end phase alignment module, in real time
The phase delay magnitude (delay increases or reduces) for adjusting each channel single-ended signal, it is consistent single-ended to export each channel phases
Signal；
(c) serioparallel exchange: by the high speed serialization single-ended signal of delay adjustment module output in the ratio of 1:8, according to rear end
The feedback signal bit_slip of phase alignment module is converted to 8 parallel-by-bit single ended data of low speed, the feedback letter of phase alignment module
The effect of number bit_slip is to control the bit of 8 bit parallel datas to put in order, such as when feedback signal bit_slip is 0,8
Parallel data is 1010_1100, when feedback signal bit_slip is 1, starts the bit reversal function of serioparallel exchange module, 8
Parallel data bit sequence is 0101_1001 after resequencing；
(d) channel selecting: resource is consumed to save the FPGA of the LVDS picture signal calibration method, therefore first by the 1st
Channel parallel single ended data is sent into rear end phase alignment module, after completing phase alignment to the channel, rear end phase alignment mould
Block gives front passage selecting module one feedback signal DONE (high level is effective), and then channel selecting is by the 2nd channel parallel list
End data be sent into rear end phase alignment module, and so on complete multichannel single ended data phase alignment；
(e) phase alignment:
(1) to the 8 single ended data real-time samplings inputted from channel selecting module, and with pre-set " calibrating sequence "
(8 ' b1101_0000) is compared；
(2) if the two is not identical, forward end delay adjustment module provides feedback signal delay_number and increases in real time
Or reduce the phase-delay quantity of single-ended signal；
(3) forward end serioparallel exchange module provides feedback signal bit_slip simultaneously, changes the bit row of 8 bit parallel datas
Column sequence until 8 single ended datas inputted from channel selecting module are identical as " calibrating sequence " (8 ' b1101_0000), and is counted
Calculate the eye figure width width of current channel data；
(4) the eye figure width minimum of the current channel data prestored is then read from eye figure width data module
Width_min, if meeting width >=width_min, current channel phase alignment is completed, forward end channel selecting module hair
Send feedback signal DONE；
(5) if width < width_min, the failure of current channel phase alignment continues above-mentioned (1) (2) (3) and (4)
Step.
LVDS signal eye diagram width data module: the effect of the module is that each channel obtained by measurement is stored in advance
The minimum value of LVDS signal eye figure width data under high and low temperature environment.
Claims (2)
1. a kind of improved cmos image sensor exports high speed serialization LVDS signal calibration method, it is characterised in that step is such as
Under:
Step 1, difference turn single-ended: the multichannel LVDS differential signal that front end cmos image sensor exports being converted to list first
End signal；The multichannel LVDS differential signal includes image synchronization, clock and data differential signals；
Step 2, delay adjustment: it is single-ended to adjust each channel for the retardation provided according to phase delay signal delay_number
The phase delay magnitude of signal, so that the phase for exporting each channel single-ended signal is consistent；
The phase delay signal delay_number: single-ended signal and " calibrating sequence " of setting are compared, list is obtained
The phase delay magnitude that end signal should adjust；
Step 3, serioparallel exchange: by the serial single-ended signal after phase adjustment in the ratio of 1:8, basis signal bit_slip conversion
For 8 parallel-by-bit single ended data of low speed；
The bit that the signal bit_slip controls 8 bit parallel datas puts in order, and the generation of signal bit_slip is: will be single-ended
Signal and " calibrating sequence " of setting are compared, if not identical sending bit reversal signal, if identical, are calculated current logical
The eye figure width width of track data；
Step 4: by eye figure width width compared with the eye figure width minimum width_min of the current channel data prestored, when
Width >=width_min, then current channel phase alignment is completed；
As width < width_min, then current channel phase alignment fails, and repeats step 2~step 3；
Step 5: after the parallel single ended data phase alignment success of first passage, carrying out the parallel single ended data phase pair of second channel
Together, step 2~step 4 is repeated.
2. a kind of realize improved cmos image sensor output high speed serialization LVDS signal calibration method described in claim 1
Device, it is characterised in that turn single-ended block, delay adjustment module, serioparallel exchange module, channel selecting module, phase including difference
Alignment module and LVDS signal eye diagram width data module；It is input terminal that difference, which turns single-ended block, and front end cmos image is sensed
The multichannel LVDS differential signal of device output is converted to single-ended signal；It, which is exported, is sequentially connected in series delay adjustment module, serioparallel exchange
Module, channel selecting module and phase alignment module；Delay adjustment module, the feedback signal according to rear end phase alignment module
Delay_number adjusts the phase delay magnitude of each channel single-ended signal, output to serioparallel exchange module in real time；It goes here and there and turns
Ratio of the block by the high speed serialization single-ended signal of delay adjustment module output in 1:8 is changed the mold, according to rear end phase alignment module
Feedback signal bit_slip is converted to 8 parallel-by-bit single ended data of low speed and exports to channel selecting module；Channel selecting module control
Each channel data is sequentially output phase alignment module by the selector channel of phase alignment module, and phase alignment module will be single-ended
After data are compared with pre-set " calibrating sequence ", phase adjustment feedback signal delay_ is issued to delay adjustment module
Number issues bits switch feedback signal bit_slip to serioparallel exchange module, and calculates the LVDS signal eye being adjusted in place
Figure width data simultaneously exports；LVDS signal eye diagram width data module is provided to exist by each channel LVDS signal that measurement obtains
The minimum value of eye figure width data under high and low temperature environment.
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| CN110188477A (en) * | 2019-05-31 | 2019-08-30 | 中国电子科技集团公司第五十八研究所 | A kind of bit synchronization method of high-speed ADC data transmission |
| CN110418060A (en) * | 2019-08-05 | 2019-11-05 | 苏州中科全象智能科技有限公司 | A kind of method for correcting image and system of high speed camera |
| CN111193891A (en) * | 2019-12-16 | 2020-05-22 | 中国航空工业集团公司洛阳电光设备研究所 | FPGA-based Camera Link data receiving system and transmission method |
| CN111614355A (en) * | 2020-03-25 | 2020-09-01 | 加特兰微电子科技(上海)有限公司 | Data transmission device, analog-to-digital converter and radar system |
| CN113315935A (en) * | 2021-05-20 | 2021-08-27 | 中国科学院光电技术研究所 | CMOS image sensor data acquisition device and method based on FPGA |
| CN113727148A (en) * | 2021-07-22 | 2021-11-30 | 北京控制工程研究所 | Large-scale image high-speed transmission circuit |
| CN114003530A (en) * | 2021-10-29 | 2022-02-01 | 上海大学 | FPGA-based serial differential communication data acquisition system and method |
| CN115882869A (en) * | 2022-12-09 | 2023-03-31 | 中国科学院长春光学精密机械与物理研究所 | Camera-Link decoding method based on signal time characteristics |
| WO2024098932A1 (en) * | 2022-11-11 | 2024-05-16 | 深圳市紫光同创电子有限公司 | Sampling clock delay phase determination method, apparatus and system, and storage medium |
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| CN114003530A (en) * | 2021-10-29 | 2022-02-01 | 上海大学 | FPGA-based serial differential communication data acquisition system and method |
| WO2024098932A1 (en) * | 2022-11-11 | 2024-05-16 | 深圳市紫光同创电子有限公司 | Sampling clock delay phase determination method, apparatus and system, and storage medium |
| CN115882869A (en) * | 2022-12-09 | 2023-03-31 | 中国科学院长春光学精密机械与物理研究所 | Camera-Link decoding method based on signal time characteristics |
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Application publication date: 20190409 |