CN113727148A - Large-scale image high-speed transmission circuit - Google Patents
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Abstract
The invention discloses a large-scale image high-speed transmission circuit, comprising: the device comprises a detector module, a control module, a power supply module and a transmission module; the detector module is responsible for converting optical signals into digital signals and serially transmitting original image data to the control module; the control module is used as a main control core and is responsible for providing exposure control, serial image acquisition, phase drift correction and single-particle locking protection of the detector; the power supply module is responsible for providing working power supply for the other three modules; the transmission module is responsible for converting 32-bit parallel image data, a clock and a control signal into 40-bit serial data through 8b/10b coding conversion and then transmitting the 40-bit serial data to a line at a high speed. The invention improves the data interface transmission rate of the star sensor, simplifies the cable connection relation between the probe and the line, and realizes large-scale high-speed image transmission with the image data volume of 5 hundred million pixels per second.
Description
Technical Field
The invention belongs to the technical field of space extremely-high-precision pointing measurement, and particularly relates to a large-scale image high-speed transmission circuit.
Background
The star sensor is an important attitude determination device of a satellite GNC system, and the measurement precision of the star sensor can directly influence the positioning precision of the whole star. With the continuous improvement of surveying and mapping resolution of remote sensing satellites in China, the GNC system requires that the directional precision of the star sensor is improved to extremely high precision in milli-second order. Therefore, the milli-angle-second star sensor selects an APS image detector CMV50000 with an ultra-large area array, and the resolution of a single-frame image is 4.8 million pixels. In order to meet the application requirement that the attitude updating rate is not lower than 10Hz, the problem of large-scale image data high-speed transmission of 5 hundred million pixels/second becomes a technical bottleneck in designing the milli-second star sensor.
The traditional split star sensor generally uses LVDS parallel signals as image data technology, and the highest communication speed of a single-path signal is 1 million pixels/second. If a mode of parallel transmission of multiple LVDS signals is adopted, 50 paths of LVDS signals are required to be used by the milli-second star sensor, and the connector, the cable and the internal interface circuit of the equipment are remarkably increased. The multi-head very high precision star sensor produced by Beijing 502 uses an LVDS serializer to replace an LVDS parallel signal for image data transmission, and the transmission rate is 7.8 million pixels/second. However, the technology needs to strictly ensure the phase relationship between 3 paths of image data signals and 1 path of clock signals in the transmission process of the signals, and needs to put more constraints on the material, processing and layout of the transmission cable.
In addition, when the milli-second star sensor works in orbit, the transmission circuit needs to withstand the temperature change of minus 40 ℃ to plus 60 ℃. Fluctuations in ambient temperature can cause the phase between the 22 serial data output sub-LVDS channels of the detector to drift. If the phase drift of a certain channel is large, the acquired image data is abnormal. Meanwhile, under the influence of the spatial single-particle effect, single-particle locking may occur when the transmission circuit is in the on-track state, and devices such as a detector with weak anti-irradiation performance need to be protected, so that the situation that the detector is in a single-particle locking state for a long time to cause function disorder and even burnout is prevented.
Disclosure of Invention
The technical problem solved by the invention is as follows: the defects of the prior art are overcome, a large-scale image high-speed transmission circuit is provided, an implementation method of the high-speed transmission circuit is provided, and the image data transmission rate of the split star sensor is greatly improved.
The purpose of the invention is realized by the following technical scheme: a large-scale image high-speed transmission circuit comprising: the device comprises a detector module, a control module, a power supply module and a transmission module; the detector module converts the starlight signal into a digital image signal through analog-to-digital conversion, obtains multiple paths of serial image data from the digital image signal through multiple paths of serial data output channels and sends the multiple paths of serial image data to the control module; the control module provides an exposure control time sequence of the detector module, receives multi-channel serial image data output by the detector module, converts the serial image data into parallel image data, and finally packs the parallel image data, a preset clock and a preset control signal according to a transmission protocol and sends the parallel image data, the preset clock and the preset control signal to the transmission module; meanwhile, the control module detects the current values of all paths of power supplies required by the working of the detector module, and when the current value of a certain path exceeds a preset threshold value, all the power supplies required by the working of the detector module are restarted or closed according to a preset power-on and power-off time sequence; the power supply module provides power for the detector module, the control module and the transmission module, and feeds current values of all paths of power supplies back to the control module when the detector module works; and the transmission module receives the packed data sent by the control module, encodes the packed data and then transmits the encoded packed data at a high speed.
In the large-scale image high-speed transmission circuit, the serial data output channel is 22 channels.
In the large-scale image high-speed transmission circuit, the control module continues to acquire training words of 22 serial data output channels after the detector module finishes outputting image data; if the training word collected by a certain channel is inconsistent with the preset value, the detector module is subjected to image acquisition training again to correct the phase difference relation among the 22 paths of serial data output channels.
In the large-scale image high-speed transmission circuit, the control module detects the current values of all paths of power supplies required by the work of the detector module when the power supply module runs; if the current value of a certain power supply is increased and exceeds a preset threshold value, all power supplies required by the work of the detector module are powered off according to a preset power-off time sequence, and then power is supplied according to a preset power-on time sequence after time delay, so that the restart is completed; and if the current value of a certain power supply still exceeds a preset threshold value after the detector module is restarted for 3 times, all power supplies required by the work of the detector module are shut down.
In the large-scale image high-speed transmission circuit, the delay time is 100 ms.
In the large-scale image high-speed transmission circuit, the packed data includes parallel image data, a preset clock and a preset control signal.
In the large-scale image high-speed transmission circuit, the transmission module receives the packed data sent by the control module, and the 32-bit parallel image data is converted into a 40-bit serial signal for high-speed transmission through 8b/10b coding.
In the large-scale image high-speed transmission circuit, the transmission module is a BLK3118 interface chip.
In the large-scale image high-speed transmission circuit, the detector module is a CMV50000 detector.
In the large-scale image high-speed transmission circuit, a serial data output channel of the detector module is a sub-LVDS interface.
Compared with the prior art, the invention has the following beneficial effects:
(1) the invention combines a large area array detector with a BLK3118 serializer, provides a realization method of a high-speed transmission circuit, and improves the image data transmission rate of a split star sensor to 5 hundred million pixels/second;
(2) the invention can continue to collect the data of each serial data output channel after the detector finishes the image data output of each frame, if the collection value of a certain channel is inconsistent with the preset value, the detector is subjected to image collection training again, the phase difference among the channels is corrected, and the influence of overlarge phase drift on image collection is avoided;
(3) the invention can detect the current value of each power supply when the detector works, and close all the power supplies of the detector according to the preset power-off time sequence when the current of a certain path is abnormally increased, thereby providing reliable single locking protection measures for the detector on the premise of meeting the safe power-off time sequence of the detector;
(4) the invention can simplify the connection between the star sensor probe and the circuit, improve the data transmission rate, improve the reliability of the on-orbit operation of the product, and can be widely applied to the development of the split type star sensor.
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Various other advantages and benefits will become apparent to those of ordinary skill in the art upon reading the following detailed description of the preferred embodiments. The drawings are only for purposes of illustrating the preferred embodiments and are not to be construed as limiting the invention. Also, like reference numerals are used to refer to like parts throughout the drawings. In the drawings:
FIG. 1 is a schematic block diagram of a large-scale image high-speed transmission circuit;
FIG. 2 is a flow chart of the control core module of the present invention controlling the detector module;
fig. 3 is a flow chart of the control core module of the present invention controlling the power module.
Detailed Description
Exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be embodied in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art. It should be noted that the embodiments and features of the embodiments may be combined with each other without conflict. The present invention will be described in detail below with reference to the embodiments with reference to the attached drawings.
In order to facilitate the whole star layout and the thermal control implementation, the milli-second star sensor adopts a split type design and is divided into a probe and a circuit. The pixels of a scientific-grade large-area array detector selected by the probe are as high as 5 million, and in order to meet the requirement that the attitude updating rate of the star sensor is not less than 10Hz, the image transmission speed of the probe needs to reach 5 hundred million pixels/second. The traditional split star sensor usually uses an LVDS interface for parallel transmission. On the premise of selecting an aerospace-grade anti-radiation chip, if the LVDS interface chip B54LVDS031 is adopted for design, 13 chips are needed to meet the requirement. If the LVDS serial interface chip B54LVDS217 is selected for design, 7 chips are needed to meet the requirement. If the serializer BLK3118 chip is adopted for design, the maximum derated transmission rate is 10Gbps, and only 1 chip is needed to meet the requirement. Considering the design requirements of miniaturization and light weight of the star sensor, a BLK3118 interface chip is selected for designing a high-speed transmission circuit.
FIG. 1 is a schematic block diagram of a large-scale high-speed image transmission circuit according to the present invention. As shown in fig. 1, the large-scale image high-speed transmission circuit includes: the device comprises a detector module, a control module, a power supply module and a transmission module; wherein,
the detector module is an APS device and is responsible for converting optical signals into digital signals and sending image data to the control module through 22 paths of serial data output channels.
The control module is an FPGA device and is used as a main control core and is responsible for providing an exposure control time sequence of the detector module, receiving 22 paths of serial image data output by the detector module, converting the serial image into parallel image data, and finally packaging the image data, the clock and the control signal according to a transmission protocol and sending the image data, the clock and the control signal to the transmission module; and meanwhile, the control module detects the current values of all paths of power supplies required by the work of the detector module, and when the current value of a certain path exceeds a preset threshold value, all the power supplies required by the work of the detector module are restarted or closed according to a preset power-on and power-off time sequence.
The power module provides all paths of power supplies required by the operation of the other three modules, and simultaneously outputs the current values of all paths of power supplies when the detector module operates.
The transmission module is a serializer, can receive packed data sent by the control module, and converts 32-bit parallel image data into 40-bit serial signals for high-speed transmission through 8b/10b coding.
The control module will continue to collect training words of 22 serial data output channels after the detector module finishes outputting image data. If the training word collected by a certain channel is inconsistent with the preset value, the detector module is subjected to image collection training again to correct the phase difference relation among the 22-path serial data output channels.
And the control module detects the current values of all paths of power supplies required by the work of the detector module when the power supply module runs. And if the current value of a certain power supply is increased and exceeds a preset threshold value, all power supplies required by the work of the detector module are powered off according to a preset power-off time sequence, and then power is supplied according to a preset power-on time sequence after time delay, so that the restart is completed. And if the current value of a certain power supply exceeds a preset threshold value after the detector module is restarted for 3 times, all power supplies required by the work of the detector module are shut down.
The control module is used as a main control and is responsible for providing exposure time sequence control, serial image acquisition, phase drift correction and single particle locking protection of the detector module. Firstly, carrying out power-on time sequence control, working parameter setting and exposure time control on a detector module, then acquiring 22 paths of serial images output by the detector, converting the serial images into parallel image data, and finally packaging and sending the parallel image data, clock signals and control signals to a transmission module according to a transmission protocol; and meanwhile, the current value of the power module during operation is detected, and the detector module is powered off and restarted or turned off when the current value is abnormally increased.
The power module provides all paths of power supplies required by the operation of the other three modules, and the current values of all paths of power supplies when the detector module operates can be fed back to the control module.
The transmission module can receive 32bit parallel image data, clock signals and control signals sent by the control module, the parallel single-ended signals are converted into 40bit serial differential signals through 8b/10b coding in the BLK3118 chip, and the signals are transmitted to a line for data processing through a main or slave XAUI channel at a high speed.
Fig. 2 is a flowchart of the operation of the control module in the large-scale image high-speed transmission circuit to perform phase drift correction on the detector module.
And after receiving a power-on instruction of the line detector, the control module starts the detector module to perform power-on time sequence control, working parameter setting and exposure time control. Firstly, N paths of power supplies required by the work of the detector are powered up according to a preset power-up time sequence so as to ensure the power supply safety when the detector is started. And then reading a state register of the detector and judging the state of the PLL, and writing in a parameter register of the detector after the PLL in the detector is stable so as to ensure the reliability of parameter setting of the detector. And finally, controlling the exposure time sequence of the detector according to the external exposure signal, so that the exposure time of the detector can be adjusted according to an external instruction. After exposure is finished, image data of 22 paths of sub-LVDS channels of the detector are collected firstly, then are converted into parallel image data in a serial-parallel mode, and the parallel image data are placed into an internal buffer area. And finally, 32-bit parallel image data, a clock and a control signal are sent to a transmission module, 8b/10b coding is carried out through BLK3118, the data are converted into 40-bit serial data, and the 40-bit serial data are transmitted to a circuit at a high speed.
The control module can continue to collect the data output by each sub-LVDS channel after the detector module finishes outputting the image data of each frame. If the acquired value of a certain channel is inconsistent with the preset value, the channel is considered to be influenced by temperature fluctuation, so that the phase difference relation between the channel and other channels is greatly drifted. At this time, if the acquisition training parameters during system power-on are still used for image acquisition, the image data of the channel may be misaligned, resulting in abnormal image data. Therefore, the control module performs image acquisition training on the detector module again, corrects the phase difference relationship among the 22 paths of sub-LVDS channels of the detector, and eliminates the adverse effect of overlarge phase drift among the channels so as to ensure that the image data of the next frame can be correctly acquired.
FIG. 3 is a flowchart illustrating the operation of the control module in the large-scale high-speed image transmission circuit for performing single-event locking protection on the detector module.
The control module can detect the current values of the detector power supplies 1 to N required by the operation of the detector module after the power supply module operates. And if the current value of a certain path of the N paths of power supplies is increased and exceeds a preset threshold value, the detector module is considered to have a single event locking fault, and the power supplies N to 1 of the detector are sequentially closed according to a preset power-off time sequence so as to ensure the safety of the detector when the power is off. Delaying 100ms after the detector power supply 1 is powered off, then sequentially turning on the detector power supplies 1 to N according to a preset power-on time sequence, and restarting the detector module to work. If the current value of a certain path still exceeds the preset threshold value in the detector power supplies 1 to N after the reset is carried out for 3 times, the detector power supplies 1 to N are closed, and the detector module is prevented from being in the single-event locked overcurrent state for a long time. In the embodiment, the power-on or power-off time sequence of the detector can be adjusted according to the power-on or power-off time sequence requirements of different detectors, and the delay waiting time and the current threshold of the locking protection can be set through an external instruction so as to adapt to the change of the state of star sensor internal software or the external working environment.
Further, the transmission module uses a BLK3118 interface chip.
Further, the detector module uses a CMV50000 detector.
Furthermore, a serial data output channel of the detector module is a sub-LVDS interface.
In the embodiment, the control module is used for carrying out exposure driving on the detector, controlling the working parameters and the exposure time of the detector, then collecting 22 paths of serial image data output by the detector, and converting serial data into parallel data. And finally, transmitting the 32-bit parallel image data, the clock and the control signal to a transmission module, and converting the data into 40-bit serial data through 8b/10b coding and transmitting the data to a line at a high speed. The control module can continue to collect the data output by each channel after the detector finishes outputting the image data. And when the acquired data of a certain channel is inconsistent with the preset value, the chart acquisition training is carried out again to correct the phase drift among the channels of the detector. The control module can control the power-on and power-off time sequence of the detector so as to protect the safety of the detector power supply; meanwhile, whether the current value of each power supply of the detector exceeds a preset threshold value or not can be detected, if the current of a certain power supply exceeds the limit, all power supplies of the detector are powered off and restarted or shut down, and the detector is prevented from being in a single event locking state for a long time.
Although the present invention has been described with reference to the preferred embodiments, it is not intended to limit the present invention, and those skilled in the art can make variations and modifications of the present invention without departing from the spirit and scope of the present invention by using the methods and technical contents disclosed above.
Claims (10)
1. A large-scale image high-speed transmission circuit characterized by comprising: the device comprises a detector module, a control module, a power supply module and a transmission module; wherein,
the detector module converts the starlight signal into a digital image signal through analog-to-digital conversion, and obtains multi-channel serial image data from the digital image signal through a plurality of serial data output channels and sends the multi-channel serial image data to the control module;
the control module provides an exposure control time sequence of the detector module, receives multi-channel serial image data output by the detector module, converts the serial image data into parallel image data, and finally packs the parallel image data, a preset clock and a preset control signal according to a transmission protocol and sends the parallel image data, the preset clock and the preset control signal to the transmission module; meanwhile, the control module detects the current values of all paths of power supplies required by the working of the detector module, and when the current value of a certain path exceeds a preset threshold value, all the power supplies required by the working of the detector module are restarted or closed according to a preset power-on and power-off time sequence;
the power supply module provides power for the detector module, the control module and the transmission module, and feeds current values of all paths of power supplies back to the control module when the detector module works;
and the transmission module receives the packed data sent by the control module, encodes the packed data and then transmits the encoded packed data at a high speed.
2. The large-scale image high-speed transmission circuit according to claim 1, wherein: the serial data output channel is 22-way.
3. The large-scale image high-speed transmission circuit according to claim 2, wherein: the control module continues to acquire training words of 22 paths of serial data output channels after the detector module finishes outputting image data; if the training word collected by a certain channel is inconsistent with the preset value, the detector module is subjected to image acquisition training again to correct the phase difference relation among the 22 paths of serial data output channels.
4. The large-scale image high-speed transmission circuit according to claim 1, wherein: the control module detects the current values of all paths of power supplies required by the work of the detector module when the power supply module runs; if the current value of a certain power supply is increased and exceeds a preset threshold value, all power supplies required by the work of the detector module are powered off according to a preset power-off time sequence, and then power is supplied according to a preset power-on time sequence after time delay, so that the restart is completed; and if the current value of a certain power supply still exceeds a preset threshold value after the detector module is restarted for 3 times, all power supplies required by the work of the detector module are shut down.
5. The large-scale image high-speed transmission circuit according to claim 4, wherein: the time of the delay is 100 ms.
6. The large-scale image high-speed transmission circuit according to claim 1, wherein: the packed data includes parallel image data, a preset clock, and a preset control signal.
7. The large-scale image high-speed transmission circuit according to claim 1, wherein: and the transmission module receives the packed data sent by the control module, and converts 32-bit parallel image data into 40-bit serial signals for high-speed transmission through 8b/10b coding.
8. The large-scale image high-speed transmission circuit according to claim 1, wherein: the transmission module is a BLK3118 interface chip.
9. The large-scale image high-speed transmission circuit according to claim 1, wherein: the detector module is a CMV50000 detector.
10. The large-scale image high-speed transmission circuit according to claim 1, wherein: and a serial data output channel of the detector module is a sub-LVDS interface.
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| CN115597657A (en) * | 2022-09-06 | 2023-01-13 | 北京控制工程研究所（Cn） | Replaceable space imaging test system |
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