CN113727148A - Large-scale image high-speed transmission circuit - Google Patents

Abstract

The invention discloses a large-scale image high-speed transmission circuit, comprising: a detector module, a control module, a power supply module and a transmission module; wherein, the detector module is responsible for converting optical signals into digital signals, and serially sending original image data To the control module; as the main control core, the control module is responsible for providing exposure control, serial image acquisition, phase drift correction and single-event locking protection of the detector; the power module is responsible for providing working power for the other three modules; the transmission module is responsible for The parallel image data, clock and control signal are converted into 40bit serial data through 8b/10b encoding and then transmitted to the line at high speed. The invention improves the data interface transmission rate of the star sensor, simplifies the cable connection relationship between the probe and the line, and realizes large-scale image high-speed transmission with an image data volume of 500 million pixels/second.

Description

A large-scale image high-speed transmission circuit

technical field

The invention belongs to the technical field of spatial extremely high-precision pointing measurement, and in particular relates to a large-scale image high-speed transmission circuit.

Background technique

The star sensor is an important attitude determination device of the satellite GNC system, and its measurement accuracy will directly affect the positioning accuracy of the entire satellite. With the continuous improvement of the mapping resolution of my country's remote sensing satellites, the GNC system requires that the orientation accuracy of the star sensor be improved to an extremely high precision of the order of milliarcseconds. To this end, the milliarcsecond star sensor uses the APS image detector CMV50000 with a large area array, and its single-frame image resolution is 48 million pixels. In order to meet the application requirements of the attitude update rate not lower than 10Hz, the problem of high-speed transmission of large-scale image data of 500 million pixels per second has become a technical bottleneck in the design of the milliarcsecond star sensor.

The traditional split star sensor usually uses LVDS parallel signal as the image data technology, and the maximum communication rate of its single signal is 10 million pixels/second. If the multi-channel LVDS signal is transmitted in parallel, the milliarcsecond star sensor needs to use 50 channels of LVDS signals, which will lead to a significant increase in the connectors, cables and internal interface circuits of the device. The multi-head very high-precision Xingmin produced by Beijing 502 uses LVDS serializers to replace LVDS parallel signals for image data transmission, with a transmission rate of 78 million pixels/second. However, this technology needs to strictly ensure the phase relationship between the three-way image data signal and one-way clock signal during the signal transmission process, and requires more constraints on the material, processing and layout of the transmission cable.

In addition, when the milliarcsecond star sensor works in orbit, the transmission circuit needs to withstand temperature changes of -40°C to +60°C. Fluctuations in ambient temperature can cause phase shifts between the detector's 22 serial data output sub-LVDS channels. If the phase drift of a channel is large, the acquired image data will be abnormal. At the same time, due to the influence of the space single-event effect, single-event locking may occur when the transmission circuit is on the rail. It is necessary to protect devices with weak anti-irradiation performance, such as detectors, to prevent the detectors from being in the single-event locked state for a long time, resulting in functional confusion or even burnout.

SUMMARY OF THE INVENTION

The technical problem solved by the invention is: to overcome the deficiencies of the prior art, to provide a large-scale image high-speed transmission circuit, and to provide a realization method of the high-speed transmission circuit, which greatly improves the image data transmission rate of the split star sensor.

The object of the present invention is achieved through the following technical solutions: a large-scale image high-speed transmission circuit, comprising: a detector module, a control module, a power supply module and a transmission module; wherein, the detector module converts the starlight signal into analog-to-digital conversion into digital image signal, and the digital image signal obtains multiple serial image data through multiple serial data output channels and sends the multiple serial image data to a control module; the control module provides exposure control of the detector module and receive the multi-channel serial image data output by the detector module, then convert the serial image data into parallel image data, and finally package and send the parallel image data, preset clock and preset control signal according to the transmission protocol to the transmission module; at the same time, the control module detects the current value of each power supply required for the operation of the detector module, and when the current value of a certain channel exceeds the preset threshold, All power supplies are restarted or turned off according to the preset power-on and power-off sequence; the power module provides power for the detector module, the control module and the transmission module, and the power module converts the current value of each power supply when the detector module is working feedback to the control module; the transmission module receives the packaged data sent by the control module, and encodes the packaged data for high-speed transmission.

In the above-mentioned large-scale image high-speed transmission circuit, there are 22 serial data output channels.

In the above-mentioned large-scale image high-speed transmission circuit, the control module continues to collect the training words of 22 serial data output channels after the detector module completes the output of the image data; if the training words collected by a certain channel are inconsistent with the preset value , the detector module is re-trained for image acquisition to correct the phase difference relationship between the 22 serial data output channels.

In the above-mentioned large-scale image high-speed transmission circuit, the control module detects the current value of each power supply required for the operation of the detector module when the power supply module is running; if the current value of a certain power supply increases and exceeds the preset value, When the threshold is set, all the power supplies required for the operation of the detector module are powered off according to the preset power-off sequence, and then powered on according to the preset power-on sequence after a delay to complete the restart; if restarted 3 times, If the current value of a certain power supply still exceeds the preset threshold, all power supplies required for the operation of the detector module are turned off.

In the above large-scale image high-speed transmission circuit, the delay time is 100ms.

In the above large-scale image high-speed transmission circuit, the packaged data includes parallel image data, a preset clock and a preset control signal.

In the above large-scale image high-speed transmission circuit, the transmission module receives the packetized data sent by the control module, and after 8b/10b encoding, converts 32-bit parallel image data into 40-bit serial signals for high-speed transmission.

In the above large-scale image high-speed transmission circuit, the transmission module is a BLK3118 interface chip.

In the above large-scale image high-speed transmission circuit, the detector module is a CMV50000 detector.

In the above large-scale image high-speed transmission circuit, the serial data output channel of the detector module is a sub-LVDS interface.

Compared with the prior art, the present invention has the following beneficial effects:

(1) The present invention combines a large area array detector with a BLK3118 serializer, and provides an implementation method for a high-speed transmission circuit, which increases the image data transmission rate of the split star sensor to 500 million pixels/second;

(2) The present invention can continue to collect the data of each serial data output channel after the detector completes the output of each frame of image data. If the collected value of a certain channel is inconsistent with the preset value, the detector will be collected again. Image training, correcting the phase difference between each channel to avoid excessive phase drift affecting image acquisition;

(3) The present invention can detect the current value of each power supply when the detector is working, and shut down all the power supplies of the detector according to the preset power-off sequence when the current of a certain path increases abnormally, and when the safe power-off sequence of the detector is satisfied On the premise, provide it with reliable monad locking protection measures;

(4) The invention can simplify the connection between the star sensor probe and the line, improve the data transmission rate, and improve the reliability of the product on-orbit operation, and can be widely used in the development of the split star sensor.

Description of drawings

Various other advantages and benefits will become apparent to those of ordinary skill in the art upon reading the following detailed description of the preferred embodiments. The drawings are for the purpose of illustrating preferred embodiments only and are not to be considered limiting of the invention. Also, the same components are denoted by the same reference numerals throughout the drawings. In the attached image:

Figure 1 is a block diagram of the principle composition of a large-scale image high-speed transmission circuit;

Fig. 2 is the flow chart that the control core module of the present invention controls the detector module;

FIG. 3 is a flow chart of the control core module of the present invention controlling the power supply module.

Detailed ways

Exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be embodied in various forms and should not be limited by the embodiments set forth herein. Rather, these embodiments are provided so that the present disclosure will be more thoroughly understood, and will fully convey the scope of the present disclosure to those skilled in the art. It should be noted that the embodiments of the present invention and the features of the embodiments may be combined with each other under the condition of no conflict. The present invention will be described in detail below with reference to the accompanying drawings and in conjunction with the embodiments.

In order to facilitate the whole satellite layout and thermal control implementation, the milliarcsecond star sensor adopts a split design, which is divided into probes and lines. The scientific-grade large area array detector selected for the probe has as many as 50 million pixels. In order to meet the requirement that the attitude update rate of the star sensor is not less than 10Hz, the image transmission speed of the probe needs to reach 500 million pixels/second. Traditional split star sensors often use the LVDS interface for parallel transmission. Under the premise of choosing aerospace-grade radiation-resistant chips, if the LVDS interface chip B54LVDS031 is used for design, 13 chips are required to meet the requirements. If the LVDS serial interface chip B54LVDS217 is selected for design, 7 chips are required to meet the requirements. If the serializer BLK3118 chip is used for design, the maximum transmission rate after derating is 10Gbps, and only one chip can meet the demand. Considering the miniaturization and lightweight design requirements of the star sensor, the BLK3118 interface chip is selected for the high-speed transmission circuit design.

FIG. 1 is a block diagram of the principle composition of a large-scale image high-speed transmission circuit of the present invention. As shown in Figure 1, the large-scale image high-speed transmission circuit includes: a detector module, a control module, a power supply module and a transmission module; wherein,

The detector module is an APS device, responsible for converting optical signals into digital signals, and sending image data to the control module through 22 serial data output channels.

The control module is an FPGA device. As the main control core, it is responsible for providing the exposure control timing of the detector module, and receives the 22-channel serial image data output by the detector module, then converts the serial image into parallel image data, and finally converts the image data. , the clock and the control signal are packaged and sent to the transmission module according to the transmission protocol; at the same time, the control module detects the current value of each power supply required for the operation of the detector module, and when the current value of a certain channel exceeds the preset threshold, the detector module All power supplies required for work are restarted or turned off according to the preset power-on and power-off sequence.

The power supply module provides the other three modules with various power supplies required for their work, and outputs the current value of each power supply when the detector module is working.

The transmission module is a serializer, which can receive the packaged data sent by the control module, and convert the 32-bit parallel image data into 40-bit serial signals after 8b/10b encoding for high-speed transmission.

The control module will continue to collect the training words of the 22 serial data output channels after the detector module completes the image data output. If the training word collected by a channel is inconsistent with the preset value, the detector module is re-trained to collect images to correct the phase difference relationship between the 22 serial data output channels.

The control module will detect the current value of each power supply required for the operation of the detector module when the power supply module is running. If the current value of a certain power supply increases and exceeds the preset threshold, all power supplies required for the operation of the detector module will be powered off according to the preset power-off sequence, and then powered on according to the preset power-on sequence after a delay. to complete the restart. If the current value of a certain power supply exceeds the preset threshold after restarting 3 times, turn off all the power supplies required for the detector module to work.

The control module, as the main controller, is responsible for providing exposure timing control, serial image acquisition, phase drift correction and single-particle locking protection of the detector module. First, the power-on sequence control, working parameter setting and exposure time control of the detector module are carried out, then the 22-channel serial images output by the detector are collected and converted into parallel image data, and finally the parallel image data, clock signal and control signal are transmitted according to the The protocol is packaged and sent to the transmission module; at the same time, the current value of the power supply module is detected when the current value is abnormally increased, and the detector module is powered off, restarted or closed when the current value increases abnormally.

The power supply module provides the other three modules with various power supplies required for their work, and can feed back the current values of the various power supplies when the detector module is working to the control module.

The transmission module can receive the 32bit parallel image data, clock signal and control signal sent by the control module. After the 8b/10b encoding inside the BLK3118 chip, the parallel single-ended signal is converted into a 40bit serial differential signal. transmitted to the line for data processing.

FIG. 2 is a working flow chart of the control module performing phase drift correction on the detector module in the large-scale image high-speed transmission circuit.

After receiving the power-on command of the line detector, the control module starts the detector module to perform power-on sequence control, working parameter setting and exposure time control. First, power on the N power supplies required for the detector to work according to the preset power-on sequence, so as to ensure the safety of the power supply when the detector is started. Then read the status register of the detector and judge the PLL status. After the internal PLL of the detector is stable, write the parameter register of the detector to ensure the reliability of the detector parameter setting. Finally, the exposure timing of the detector is controlled according to the external exposure signal, so that the exposure time of the detector can be adjusted according to the external command. After exposure, the image data of 22 sub-LVDS channels of the detector are first collected, and then converted into parallel image data through serial-parallel conversion and put into the internal buffer. Finally, the 32bit parallel image data, clock and control signal are sent to the transmission module, and the 8b/10b encoding is converted into 40bit serial data through BLK3118 and transmitted to the line at high speed.

The control module can continue to collect the data output by each sub-LVDS channel after the detector module completes the output of each frame of image data. If the collected value of a channel is inconsistent with the preset value, it is considered that the channel is affected by temperature fluctuations, resulting in a large drift in the phase difference relationship with other channels. At this time, if the image collection training parameters when the system is powered on are still used for image acquisition, the image data of this channel may be misaligned, resulting in abnormal image data. Therefore, the control module will perform image capture training on the detector module again, correct the phase difference relationship between the 22 sub-LVDS channels of the detector, and eliminate the adverse effect of excessive phase drift between channels, so as to ensure that the next frame can be correctly captured. image data.

FIG. 3 is a working flow chart of the control module in the large-scale image high-speed transmission circuit for single-particle locking protection for the detector module.

The control module can detect the current value of the detector power supply 1 to N required for the operation of the detector module after the power supply module operates. If the current value of one of the N-channel power sources increases and exceeds the preset threshold, it is considered that the detector module has a single event locking fault, and the detector power supply N to 1 will be turned off in sequence according to the preset power-off sequence to ensure that the detector is disconnected. Safety when powered. After the detector power supply 1 is powered off, the delay is 100ms, and then the detector power supply 1 to N are turned on in sequence according to the preset power-on sequence, and the detector module is restarted to work. If the current value of a certain channel in the detector power supply 1 to N exceeds the preset threshold after restarting 3 times, turn off the detector power supply 1 to N to prevent the detector module from being in the overcurrent state of single-event lock for a long time. In this embodiment, the power-on or power-off sequence of the detector can be adjusted according to the power-on or power-off sequence requirements of different detectors, and the delay waiting time and current threshold of the lock protection can be set by external commands to adapt to Changes in Xingmin's internal software status or external working environment.

Further, the transmission module uses the BLK3118 interface chip.

Further, the detector module uses the CMV50000 detector.

Further, the serial data output channel of the detector module is a sub-LVDS interface.

In this embodiment, through the control module, the detector is exposed and driven, the working parameters and exposure time of the detector are controlled, and then 22 channels of serial image data output by the detector are collected, and the serial data is converted into parallel data. Finally, the 32bit parallel image data, clock and control signals are sent to the transmission module, and after 8b/10b encoding, they are converted into 40bit serial data and transmitted to the line at high speed. The control module can continue to collect the data output by each channel after the detector completes the output of the image data. When the collected data of a certain channel is inconsistent with the preset value, the image collection training is performed again to correct the phase drift between each channel of the detector. The control module can control the power-on and power-off sequence of the detector to protect the safety of the power supply of the detector; at the same time, it can detect whether the current value of each power supply of the detector exceeds the preset threshold. If the limit is reached, power off and restart or turn off all power supplies of the detector to prevent it from being in the single-particle lock state for a long time.

Although the present invention has been disclosed above with preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art can use the methods and technical contents disclosed above to improve the present invention without departing from the spirit and scope of the present invention. The technical solutions are subject to possible changes and modifications. Therefore, any simple modifications, equivalent changes and modifications made to the above embodiments according to the technical essence of the present invention without departing from the content of the technical solutions of the present invention belong to the technical solutions of the present invention. protected range.

Claims (10)

1. a large-scale image high-speed transmission circuit is characterized in that comprising: a detector module, a control module, a power supply module and a transmission module; wherein, The detector module converts the starlight signal into a digital image signal through analog-to-digital conversion, obtains the multi-channel serial image data from the digital image signal through the multi-channel serial data output channel, and sends the multi-channel serial image data to the control module. ; The control module provides the exposure control timing of the detector module, and receives the multi-channel serial image data output by the detector module, then converts the serial image data into parallel image data, and finally converts the parallel image data, pre- The clock and the preset control signal are packaged and sent to the transmission module according to the transmission protocol; at the same time, the control module detects the current value of each power supply required for the operation of the detector module. When the threshold value is set, restart or shut down all the power supplies required for the operation of the detector module according to the preset power-on and power-off sequence; The power supply module provides power for the detector module, the control module and the transmission module, and the power supply module feeds back the current value of each power supply when the detector module is working to the control module; The transmission module receives the packaged data sent by the control module, and encodes the packaged data for high-speed transmission. 2. The large-scale image high-speed transmission circuit according to claim 1, wherein the number of serial data output channels is 22. 3. large-scale image high-speed transmission circuit according to claim 2, is characterized in that: described control module continues to collect the training word of 22 serial data output channels after described detector module completes image data output; If the training word collected by a channel is inconsistent with the preset value, the detector module is re-trained to collect images to correct the phase difference relationship between the 22 serial data output channels. 4. The large-scale image high-speed transmission circuit according to claim 1, wherein the control module detects the current value of each power supply required for the operation of the detector module when the power supply module operates; When the current value of a certain power supply increases and exceeds the preset threshold, all the power supplies required for the operation of the detector module are powered off according to the preset power-off sequence, and then after a delay, power-on is powered up according to the preset power-on sequence. If the current value of a certain power supply exceeds the preset threshold after restarting 3 times, all the power supplies required for the operation of the detector module will be turned off. 5. The large-scale image high-speed transmission circuit according to claim 4, wherein the delay time is 100ms. 6 . The large-scale image high-speed transmission circuit according to claim 1 , wherein the packed data includes parallel image data, a preset clock and a preset control signal. 7 . 7. The large-scale image high-speed transmission circuit according to claim 1, wherein the transmission module receives the packaged data sent by the control module, and converts the 32-bit parallel image data into 40-bit serial data through 8b/10b encoding. Signals are transmitted at high speed. 8. The large-scale image high-speed transmission circuit according to claim 1, wherein the transmission module is a BLK3118 interface chip. 9 . The large-scale image high-speed transmission circuit according to claim 1 , wherein the detector module is a CMV50000 detector. 10 . 10 . The large-scale image high-speed transmission circuit according to claim 1 , wherein the serial data output channel of the detector module is a sub-LVDS interface. 11 .

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