CN112652277B - Sampler, display driving chip and display device - Google Patents

Sampler, display driving chip and display device Download PDF

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Publication number
CN112652277B
CN112652277B CN202011527006.6A CN202011527006A CN112652277B CN 112652277 B CN112652277 B CN 112652277B CN 202011527006 A CN202011527006 A CN 202011527006A CN 112652277 B CN112652277 B CN 112652277B
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China
Prior art keywords
sampling
sampling control
nth
clock signal
control
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CN112652277A (en
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白东勋
李东明
南帐镇
花正贝
范昊
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Hefei Yisiwei Computing Technology Co ltd
Beijing Eswin Computing Technology Co Ltd
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Beijing Eswin Computing Technology Co Ltd
Hefei Eswin IC Technology Co Ltd
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Priority to CN202011527006.6A priority Critical patent/CN112652277B/en
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Priority to PCT/CN2021/094645 priority patent/WO2022134440A1/en
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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/02—Details of power systems and of start or stop of display operation
    • G09G2330/021—Power management, e.g. power saving
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/06—Handling electromagnetic interferences [EMI], covering emitted as well as received electromagnetic radiation
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Liquid Crystal Display Device Control (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)

Abstract

The invention provides a sampler, a display driving chip and a display device. The sampler comprises a first sampling control circuit, a second sampling control circuit and a sampling circuit, wherein the second sampling control circuit comprises N second sampling control units; the second sampling control unit comprises M second sampling control unit circuits; the first sampling control circuit is used for converting serial input data into N first serial data, wherein N and M are positive integers; n is greater than 1, and/or M is greater than 1; an mth second sampling control unit circuit in the nth second sampling control unit converts the nth first serial data into second serial data under the control of the sampling control signal; the sampling circuit is electrically connected with the second sampling control unit circuit and is used for converting the second serial data into corresponding parallel data under the control of a sampling control clock signal; n is a positive integer less than or equal to N. The invention reduces power consumption and reduces consumed peak current and average current.

Description

Sampler, display driving chip and display device
Technical Field
The invention relates to the technical field of signal sampling, in particular to a sampler, a display driving chip and a display device.
Background
In the display driver chip circuit, a clock signal generation circuit extracts a clock from high-speed serial data and generates a reference clock signal to operate display driver logic. In the process of converting serial data into parallel data, one-bit high-speed serial data is converted into multi-bit low-speed parallel data, so the load of the data buffer is generally larger, and the size of the data buffer is generally increased to ensure the normal operation of the data buffer. However, when the size is increased, the power consumption and the peak current are also increased, which also reduces the anti-electromagnetic interference performance.
Disclosure of Invention
The invention mainly aims to provide a sampler, a display driving chip and a display device, and solves the problems that the power consumption of the existing display driving chip is large, and the peak current and the average current of the sampler are large.
In order to achieve the above object, the present invention provides a sampler comprising a first sampling control circuit, a second sampling control circuit and a sampling circuit, wherein the second sampling control circuit comprises N second sampling control units; the second sampling control unit comprises M second sampling control unit circuits; the first sampling control circuit is used for converting serial input data into N first serial data, and N and M are positive integers; n is greater than 1, and/or M is greater than 1;
the mth second sampling control unit circuit in the nth second sampling control unit is used for converting the nth first serial data into corresponding second serial data under the control of the corresponding sampling control signal;
the sampling circuit is electrically connected with the second sampling control unit circuit and is used for converting the second serial data into corresponding parallel data under the control of a sampling control clock signal;
n is a positive integer less than or equal to N.
Optionally, the first sampling control circuit includes N first sampling control unit circuits, and the nth first sampling control unit circuit is configured to convert the serial input data into nth first serial data.
Optionally, the nth first sampling control unit circuit includes an nth first control inverter and an nth second control inverter;
the input end of the nth first control inverter is connected with the serial input data, and the output end of the nth first control inverter is electrically connected with the input end of the nth second control inverter;
and the output end of the nth second control inverter is used for outputting the nth first serial data.
Optionally, the nth first sampling control unit circuit includes an nth control nand gate and an nth control inverter;
the first input end of the nth control NAND gate is connected with the serial input data, the second input end of the nth control NAND gate is connected with the nth input control signal, and the output end of the nth control NAND gate is electrically connected with the input end of the nth control inverter;
and the output end of the nth control inverter is used for outputting the nth first serial data.
Optionally, the mth second sampling control unit circuit in the nth second sampling control unit includes a sampling nand gate and a sampling inverter;
the first input end of the sampling NAND gate is connected with the nth first serial data, the second input end of the sampling NAND gate is connected with the corresponding sampling control signal, the output end of the sampling NAND gate is electrically connected with the input end of the sampling inverter, the output end of the sampling inverter is electrically connected with the sampling circuit, and the sampling inverter is used for outputting the corresponding second serial data to the sampling circuit through the output end of the sampling inverter.
Optionally, the sampling circuit comprises a plurality of D flip-flops;
the input end of the D trigger is connected with the second serial data, the control end of the D trigger is connected with the corresponding sampling control clock signal, and the output end of the D trigger is used for outputting the corresponding parallel data.
The invention also provides a display driving chip which comprises the sampler.
Optionally, the display driving chip according to the embodiment of the present invention further includes a clock signal generator, a delay circuit, and a delay locked loop, wherein,
the clock signal generator is used for extracting clock edge information in original serial input data to generate a response input clock signal;
the delay circuit is used for controlling the original serial input data to delay for a preset time so as to obtain serial input data, and the serial input data is provided to the sampler;
the delay locked loop converts the input clock signal into a plurality of sampling control clock signals and provides the sampling control clock signals to the sampler.
The display device provided by the embodiment of the invention comprises the display driving chip.
The sampler, the display driving chip and the display device of the embodiment of the invention convert serial input data into N first serial data through the first sampling control circuit, the mth second sampling control unit circuit in the nth second control unit is used for converting the nth first serial data into corresponding second serial data under the control of corresponding sampling control signals, and the sampling circuit converts the second serial data into corresponding parallel data under the control of sampling control clock signals. In the embodiment of the invention, data conversion is performed under the control of the corresponding sampling control signal of each circuit of the sampling control unit, so that when the sampler works, the signal output by at least one second sampling control unit circuit is unchanged in each sampling time period included in the working time period of the sampler, thereby saving power consumption, reducing peak current and average current of the circuit and improving the anti-electromagnetic interference performance.
Drawings
FIG. 1 is a block diagram of a sampler according to an embodiment of the present invention;
FIG. 2 is a diagram of a display driver chip according to an embodiment of the invention;
FIG. 3 is a timing diagram of clock signals used in a display driver chip according to an embodiment of the invention;
FIG. 4 is a block diagram of a sampler according to another embodiment of the present invention;
FIG. 5 is a circuit diagram of a sampler according to yet another embodiment of the present invention;
FIG. 6 is a timing diagram illustrating the operation of the embodiment of the sampler shown in FIG. 5 according to the present invention;
FIG. 7 is a circuit diagram of a sampler according to another embodiment of the present invention;
FIG. 8 is a timing diagram illustrating the operation of the embodiment of the sampler shown in FIG. 7 according to the present invention;
FIG. 9 is a block diagram of a sampler according to another embodiment of the present invention;
FIG. 10 is a circuit diagram of a sampler according to yet another embodiment of the present invention;
FIG. 11 is a timing diagram illustrating the operation of the embodiment of the sampler shown in FIG. 10 according to the present invention;
FIG. 12 is a circuit diagram of a sampler according to another embodiment of the present invention;
FIG. 13 is a timing diagram illustrating the operation of the embodiment of the sampler shown in FIG. 12 according to the present invention;
FIG. 14 is a timing diagram of the data buffer drain current I1 in the prior art sampler, the data buffer drain current I2 in the embodiment of the sampler shown in FIG. 7, and the data buffer drain current I3 in the embodiment of the sampler shown in FIG. 12.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
As shown in fig. 1, the sampler according to the embodiment of the present invention includes a first sampling control circuit 11, a second sampling control circuit 12, and a sampling circuit 13, where the second sampling control circuit 12 includes N second sampling control units; the second sampling control unit comprises M second sampling control unit circuits; the first sampling control circuit 11 is configured to convert serial input data into N first serial data, where N and M are positive integers; n is greater than 1, and/or M is greater than 1;
the mth second sampling control unit circuit in the nth second sampling control unit is used for converting the nth first serial data into corresponding second serial data under the control of the corresponding sampling control signal;
the sampling circuit 13 is electrically connected to the second sampling control unit circuit, and is configured to convert the second serial data into corresponding parallel data under the control of a sampling control clock signal;
n is a positive integer less than or equal to N.
The sampler of the embodiment of the invention can convert serial input data into N first serial data through the first sampling control circuit, the mth second sampling control unit circuit in the nth second control unit is used for converting the nth first serial data into corresponding second serial data under the control of a corresponding sampling control signal, and the sampling circuit converts the second serial data into corresponding parallel data under the control of a sampling control clock signal. In the embodiment of the invention, data conversion is performed under the control of the corresponding sampling control signal of each circuit of the sampling control unit, so that when the sampler works, the signal output by at least one second sampling control unit circuit is unchanged in each sampling time period included in the working time period of the sampler, thereby saving power consumption, reducing peak current and average current of the circuit and improving the anti-electromagnetic interference performance.
In the embodiment of the present invention, the first sampling control circuit 11 and the second sampling circuit 12 constitute a data buffer.
The sampler according to the embodiment of the present invention is included in the display driver chip according to the embodiment of the present invention, as shown in fig. 2, the display driver chip according to the embodiment of the present invention may include a sampler 20, a clock signal generator 21, a delay circuit 23, and a delay locked loop 24, wherein,
the clock signal generator 21 is configured to extract clock edge information in the original serial input data DIN to generate a responsive input clock signal RCLK;
the delay circuit 23 is configured to control the original serial input data DIN to delay for a predetermined time to obtain serial input data RDAT, and provide the serial input data RDAT to the sampler 20;
the delay locked loop 24 converts the input clock signal RCLK into a plurality of sampling control clock signals and supplies the sampling control clock signals to the sampler 20.
In an embodiment of the present invention, the original serial input data DIN may be clock-embedded serial data, and the clock signal generator 21 extracts clock edge information in DIN to generate a responsive input clock signal RCLK; for example, when one of the original serial input data DIN has 24 rising edges, the input clock signal RCLK may also have 24 rising edges;
the delay locked loop 24 converts the input clock signal RCLK into a plurality of sampling control clock signals, wherein a rising edge of each of the sampling control clock signals corresponds to a rising edge of RCLK;
the delay circuit 23 is configured to control the original serial input data DIN to delay for a predetermined time to obtain serial input data RDAT; the predetermined time may be selected according to actual conditions, so that a middle segment of one data of the RDAT corresponds to a rising edge of one sampling control clock signal, so that the sampler can accurately convert the serial input data RDAT into corresponding parallel data.
As shown in fig. 3, assuming that one of the original serial input data DIN has 24 rising edges, the delay locked loop 24 outputs 24 sampling control clock signals;
in fig. 3, reference numeral CLK1 is a first sampling control clock signal, reference numeral CLK4 is a fourth sampling control clock signal, reference numeral CLK5 is a fifth sampling control clock signal, reference numeral CLK8 is an eighth sampling control clock signal, reference numeral CLK9 is a ninth sampling control clock signal, reference numeral CLK12 is a twelfth sampling control clock signal, reference numeral CLK13 is a thirteenth sampling control clock signal, reference numeral CLK16 is a sixteenth sampling control clock signal, reference numeral CLK17 is a seventeenth sampling control clock signal, reference numeral CLK20 is a twentieth sampling control clock signal, reference numeral CLK21 is a twenty-first sampling control clock signal, reference numeral CLK24 is a twenty-fourth sampling control clock signal;
the first data carried by the RDAT is labeled D1, the fourth data carried by the RDAT is labeled D4, the fifth data carried by the RDAT is labeled D5, the eighth data carried by the RDAT is labeled D8, the ninth data carried by the RDAT is labeled D9, the twelfth data carried by the RDAT is labeled D12, the thirteenth data carried by the RDAT is labeled D13, the sixteenth data carried by the RDAT is labeled D16, the seventh data carried by the RDAT is labeled D17, the twenty second data carried by the RDAT is labeled D20, the twenty first data carried by the RDAT is labeled D21, and the twenty fourth data carried by the RDAT is labeled D24.
As shown in fig. 3, the middle segment of D1 carried by RDAT corresponds to the rising edge of CLK1, the middle segment of D4 carried by RDAT corresponds to the rising edge of CLK4, the middle segment of D5 carried by RDAT corresponds to the rising edge of CLK5, the middle segment of D8 carried by RDAT corresponds to the rising edge of CLK8, the middle segment of D9 carried by RDAT corresponds to the rising edge of CLK9, the middle segment of D12 carried by RDAT corresponds to the rising edge of CLK12, the middle segment of D13 carried by RDAT corresponds to the rising edge of CLK13, the middle segment of D16 carried by RDAT corresponds to the rising edge of CLK16, the middle segment of D17 carried by RDAT corresponds to the rising edge of CLK17, the middle segment of D20 carried by RDAT corresponds to the rising edge of CLK20, the middle segment of D21 carried by RDAT corresponds to the rising edge of CLK21, and the middle segment of D24 carried by RDAT corresponds to the rising edge of CLK 24.
Optionally, the first sampling control circuit may include N first sampling control unit circuits, and the nth first sampling control unit circuit is configured to convert the serial input data into nth first serial data.
In a specific implementation, the first sampling control circuit may include N first sampling control unit circuits, and each first sampling control unit circuit outputs one of the first serial data.
According to a specific embodiment, the nth first sampling control unit circuit includes an nth first control inverter and an nth second control inverter;
the input end of the nth first control inverter is connected with the serial input data, and the output end of the nth first control inverter is electrically connected with the input end of the nth second control inverter;
and the output end of the nth second control inverter is used for outputting the nth first serial data.
In the embodiment of the present invention, the first sampling control unit circuit may include two control inverters, but is not limited thereto.
According to another specific implementation, the nth first sampling control unit circuit comprises an nth control nand gate and an nth control inverter;
the first input end of the nth control NAND gate is connected with the serial input data, the second input end of the nth control NAND gate is connected with the nth input control signal, and the output end of the nth control NAND gate is electrically connected with the input end of the nth control inverter;
and the output end of the nth control inverter is used for outputting the nth first serial data.
In a specific implementation, the nth first sampling control unit circuit may include an nth control nand gate and an nth control inverter, the nth control nand gate has a second input terminal connected to the nth input control signal, and when the potential of the nth control nand gate is a low voltage, the nth control nand gate outputs the high voltage no matter the serial input data is the high voltage or the low voltage, so as to save power consumption and reduce peak current and average current.
Optionally, the mth second sampling control unit circuit in the nth second sampling control unit may include a sampling nand gate and a sampling inverter;
the first input end of the sampling NAND gate is connected with the nth first serial data, the second input end of the sampling NAND gate is connected with the corresponding sampling control signal, the output end of the sampling NAND gate is electrically connected with the input end of the sampling inverter, the output end of the sampling inverter is electrically connected with the sampling circuit, and the sampling inverter is used for outputting the corresponding second serial data to the sampling circuit through the output end of the sampling inverter.
In specific implementation, the second input end of the sampling nand gate is connected with a corresponding sampling control signal, so that when the potential of the sampling control signal is low voltage, the output of the nand gate is high voltage, and the control phase inverter outputs low voltage, thereby saving power consumption.
In particular implementations, the sampling circuit may include a plurality of D flip-flops;
the input end of the D trigger is connected with the second serial data, the control end of the D trigger is connected with the corresponding sampling control clock signal, and the output end of the D trigger is used for outputting the corresponding parallel data.
As shown in FIG. 4, based on the embodiment of the sampler of the present invention as shown in FIG. 1, N is equal to 1 and M is equal to 3;
the first sampling control circuit 11 is configured to convert serial input data into first serial data;
the second sampling control circuit comprises a second sampling control unit;
the second sampling control unit includes a first second sampling control unit circuit 121, a second sampling control unit circuit 122, and a third second sampling control unit circuit 123;
the first second sampling control unit circuit 121 is configured to convert the first serial data into first second serial data under the control of the first sampling control signal;
the second sampling control unit circuit 122 is configured to convert the first serial data into second serial data under the control of a second sampling control signal;
the third second sampling control unit circuit 123 is configured to convert the first serial data into third second serial data under the control of a third sampling control signal;
the sampling circuit 13 is electrically connected to the first second sampling control unit circuit 121, the second sampling control unit circuit 122, and the third second sampling control unit circuit 123, respectively, and is configured to convert the first second serial data, the second serial data, and the third second serial data into corresponding parallel data under the control of a sampling control clock signal.
As shown in fig. 5, on the basis of the embodiment of the sampler shown in fig. 4,
the first sampling control circuit 11 includes a first inverter F1 and a second inverter F2;
the first second sampling control unit circuit 121 includes a first nand gate AF1 and a third inverter F3;
the second sampling control unit circuit 122 includes a second nand gate AF2 and a fourth inverter F4;
the third second sampling control unit circuit 123 includes a third nand gate AF3 and a fifth inverter F5;
the input end of the F1 is connected with serial input data RDAT, and the output end of the F1 is electrically connected with the input end of the F2;
a first input of AF1 is electrically connected to the output of F2; a second input end of the AF1 is connected with a first enabling clock signal EN1, an output end of the AF2 is electrically connected with an input end of the F3, and an output end of the F3 is used for outputting first second serial data RDAT 1;
a first input end of the AF2 is electrically connected with an output end of the F2, a second input end of the AF2 is connected to the second enable clock signal EN2, an output end of the AF2 is electrically connected with an input end of the F4, and an output end of the F4 is used for outputting a second serial data RDAT 2;
a first input end of the AF3 is electrically connected with an output end of the F2, a second input end of the AF3 is connected with a third enable clock signal EN3, an output end of the AF3 is electrically connected with an input end of the F5, and an output end of the F5 is used for third second serial data RDAT 3;
the sampling circuit 13 is electrically connected to the output terminal of F3, the output terminal of F4, and the output terminal of F5, respectively, and is configured to convert the first second serial data, the second serial data, and the third second serial data into corresponding parallel data under the control of a sampling control clock signal.
In the embodiment shown in fig. 5, EN1, EN2, and EN3 are sampling control signals.
In fig. 5 and 7, reference numeral C1 is a first load capacitor, reference numeral C2 is a second load capacitor, and reference numeral C3 is a third load capacitor.
As shown in fig. 6, when the sampler shown in fig. 5 of the present invention is in operation, the sampling period includes a first sampling period S1, a second sampling period S2, and a third sampling period S3, which are sequentially set;
in the first sampling period S1, EN1 is a high voltage, EN2 and EN3 are low voltages, the first second sampling control unit circuit 121 operates to output the first second serial data RDAT1 through the output terminal of F3;
in the second sampling period S2, EN2 is a high voltage, EN1 and EN3 are low voltages, the second sampling control unit circuit 122 operates to output the second serial data RDAT2 through the output terminal of F4;
in the third sampling period S3, EN3 is a high voltage, EN1 and EN2 are low voltages, and the third second sampling control unit circuit 123 operates to output the third second serial data RDAT3 through the output terminal of F5.
When the embodiment of the sampler shown in fig. 5 of the present invention is in operation, in the first sampling period S1, since EN2 and EN3 are low voltages, AF2 and AF3 continuously output high voltages, and F4 and F5 continuously output low voltages, power consumption can be saved, and peak current and average current can be reduced;
in the second sampling period S2, since EN1 and EN3 are low voltages, AF1 and AF3 continuously output high voltages and F3 and F5 continuously output low voltages, power consumption can be saved and peak current and average current can be reduced;
in the third sampling period S3, since EN1 and EN2 are low voltages, AF1 and AF2 continuously output high voltages and F3 and F4 continuously output low voltages, power consumption can be saved and peak current and average current can be reduced.
As shown in fig. 7, on the basis of the embodiment of the sampler shown in fig. 5, the sampling circuit comprises a first sampling unit 61, a second sampling unit 62 and a third sampling unit 63;
the first sampling unit 61 comprises a first D flip-flop, a second D flip-flop, a third D flip-flop, a fourth D flip-flop, a fifth D flip-flop, a sixth D flip-flop, a seventh D flip-flop and an eighth D flip-flop;
the input end of the first D trigger is connected to the RDAT1, and the output end of the first D trigger is electrically connected with the first parallel data output end; a control end of the first D trigger is accessed to a first sampling control clock signal;
the input end of the second D flip-flop is connected to the RDAT1, and the output end of the second D flip-flop is electrically connected with the second parallel data output end; the control end of the second D trigger is connected with a second sampling control clock signal;
the input end of the third D flip-flop is connected to the RDAT1, and the output end of the third D flip-flop is electrically connected with the third parallel data output end; a control end of the third D trigger is accessed to a third sampling control clock signal;
the input end of the fourth D flip-flop is connected to the RDAT1, and the output end of the fourth D flip-flop is electrically connected with the fourth parallel data output end; a control end of the fourth D trigger is connected with a fourth sampling control clock signal;
the input end of the fifth D flip-flop is connected to the RDAT1, and the output end of the fifth D flip-flop is electrically connected with the fifth parallel data output end; a control end of the fifth D trigger is accessed to a fifth sampling control clock signal;
the input end of the sixth D trigger is connected to the RDAT1, and the output end of the sixth D trigger is electrically connected with the sixth parallel data output end; a control end of the sixth D trigger is accessed to a sixth sampling control clock signal;
the input end of the seventh D flip-flop is connected to the RDAT1, and the output end of the seventh D flip-flop is electrically connected with the seventh parallel data output end; a control end of the seventh D trigger is connected with a seventh sampling control clock signal;
the input end of the eighth D flip-flop is connected to the RDAT1, and the output end of the eighth D flip-flop is electrically connected with the eighth parallel data output end; a control end of the eighth D trigger is accessed to an eighth sampling control clock signal;
the second sampling unit 62 includes a ninth D flip-flop, a tenth D flip-flop, an eleventh D flip-flop, a twelfth D flip-flop, a thirteenth D flip-flop, a fourteenth D flip-flop, a fifteenth D flip-flop, and a sixteenth D flip-flop;
the input end of the ninth D flip-flop is connected to the RDAT2, and the output end of the ninth D flip-flop is electrically connected with the ninth parallel data output end; a control end of the ninth D trigger is connected with a ninth sampling control clock signal;
the input end of the tenth D flip-flop is connected to the RDAT2, and the output end of the tenth D flip-flop is electrically connected with the tenth parallel data output end; a control end of the tenth D trigger is accessed to a tenth sampling control clock signal;
the input end of the eleventh D flip-flop is connected to the RDAT2, and the output end of the eleventh D flip-flop is electrically connected with the eleventh parallel data output end; a control end of the eleventh D trigger is connected with an eleventh sampling control clock signal;
the input end of the twelfth D trigger is connected to the RDAT2, and the output end of the twelfth D trigger is electrically connected with the twelfth parallel data output end; a control end of the twelfth D trigger is connected with a twelfth sampling control clock signal;
the input end of the thirteenth D flip-flop is connected with the RDAT2, and the output end of the thirteenth D flip-flop is electrically connected with the thirteenth parallel data output end; a control end of the thirteenth D trigger is connected with a thirteenth sampling control clock signal;
the input end of the fourteenth D flip-flop is connected to the RDAT2, and the output end of the fourteenth D flip-flop is electrically connected with the fourteenth parallel data output end; a control end of the fourteenth D trigger is connected to a fourteenth sampling control clock signal;
the input end of the fifteenth D flip-flop is connected to the RDAT2, and the output end of the fifteenth D flip-flop is electrically connected with the fifteenth parallel data output end; a control end of the fifteenth D trigger is connected with a fifteenth sampling control clock signal;
the input end of the sixteenth D trigger is connected to the RDAT2, and the output end of the sixteenth D trigger is electrically connected with the sixteenth parallel data output end; a control end of the sixteenth D trigger is connected with a sixteenth sampling control clock signal;
the third sampling unit 63 includes a seventeenth D flip-flop, an eighteenth D flip-flop, a nineteenth D flip-flop, a twentieth D flip-flop, a twenty-first D flip-flop, a twenty-second D flip-flop, a twenty-third D flip-flop, and a twenty-fourth D flip-flop;
the input end of the seventeenth D flip-flop is connected to the RDAT3, and the output end of the seventeenth D flip-flop is electrically connected with the seventeenth parallel data output end; a control end of the seventeenth D trigger is connected with a seventeenth sampling control clock signal;
the input end of the eighteenth D trigger is connected with the RDAT3, and the output end of the eighteenth D trigger is electrically connected with the eighteenth parallel data output end; a control end of the eighteenth D trigger is connected with an eighteenth sampling control clock signal;
the input end of the nineteenth D flip-flop is connected to the RDAT3, and the output end of the nineteenth D flip-flop is electrically connected with the nineteenth parallel data output end; a control end of the nineteenth D trigger is connected to a nineteenth sampling control clock signal;
the input end of the twentieth flip-flop is connected to the RDAT3, and the output end of the twentieth flip-flop is electrically connected with the twentieth parallel data output end; a control end of the twentieth trigger is connected to a twentieth sampling control clock signal;
the input end of the twenty-first D trigger is connected with the RDAT3, and the output end of the twenty-first D trigger is electrically connected with the twenty-first parallel data output end; a control end of the twenty-first D trigger is connected with a twenty-first sampling control clock signal;
the input end of the twenty-second D trigger is connected to the RDAT3, and the output end of the twenty-second D trigger is electrically connected with the twenty-second parallel data output end; a control end of the twenty-second D trigger is connected with a twenty-second sampling control clock signal;
the input end of the twenty-third D trigger is connected to the RDAT3, and the output end of the twenty-third D trigger is electrically connected with the twenty-third parallel data output end; a control end of the twenty-third trigger is connected with a twenty-third sampling control clock signal;
the input end of the twenty-fourth D trigger is connected to the RDAT3, and the output end of the twenty-fourth D trigger is electrically connected with the twenty-fourth parallel data output end; and the control end of the twenty-fourth D trigger is connected with a twenty-fourth sampling control clock signal.
In the embodiment of the present invention, when each D flip-flop operates, when a clock signal connected to the control terminal of the D flip-flop is at a rising edge, a signal at the input terminal of the D flip-flop is transmitted to the output terminal of the D flip-flop, but not limited thereto.
In fig. 7, reference numeral DOUT [1:8] is a first set of parallel data outputs comprising: a first parallel data output terminal, a second parallel data output terminal, a third parallel data output terminal, a fourth parallel data output terminal, a fifth parallel data output terminal, a sixth parallel data output terminal, a seventh parallel data output terminal, and an eighth parallel data output terminal;
labeled CLK [1:8] is a first set of clock signals comprising: a first sampling control clock signal, a second sampling control clock signal, a third sampling control clock signal, a fourth sampling control clock signal, a fifth sampling control clock signal, a sixth sampling control clock signal, a seventh sampling control clock signal, and an eighth sampling control clock signal;
labeled DOUT [9:16] is a second set of parallel data outputs comprising: a ninth parallel data output terminal, a tenth parallel data output terminal, an eleventh parallel data output terminal, a twelfth parallel data output terminal, a thirteenth parallel data output terminal, a fourteenth parallel data output terminal, a fifteenth parallel data output terminal, and a sixteenth parallel data output terminal;
labeled CLK [9:16] is a second set of clock signals comprising: a ninth sampling control clock signal, a tenth sampling control clock signal, an eleventh sampling control clock signal, a twelfth sampling control clock signal, a thirteenth sampling control clock signal, a fourteenth sampling control clock signal, a fifteenth sampling control clock signal, a sixteenth sampling control clock signal;
labeled DOUT [17:24] is a third set of parallel data outputs comprising: a seventeenth parallel data output terminal, an eighteenth parallel data output terminal, a nineteenth parallel data output terminal, a twentieth parallel data output terminal, a twenty-first parallel data output terminal, a twenty-second parallel data output terminal, a twenty-third parallel data output terminal, and a twenty-fourth parallel data output terminal;
labeled CLK [17:24] is a third set of clock signals comprising: a seventeenth sampling control clock signal, an eighteenth sampling control clock signal, a nineteenth sampling control clock signal, a twentieth sampling control clock signal, a twenty-first sampling control clock signal, a twenty-second sampling control clock signal, a twenty-third sampling control clock signal, and a twenty-fourth sampling control clock signal.
Fig. 8 is a timing diagram of the operation of the sampler shown in fig. 7.
As shown in fig. 8, reference numeral CLK1 is a first sampling control clock signal, reference numeral CLK4 is a fourth sampling control clock signal, reference numeral CLK5 is a fifth sampling control clock signal, reference numeral CLK8 is an eighth sampling control clock signal, reference numeral CLK9 is a ninth sampling control clock signal, reference numeral CLK12 is a twelfth sampling control clock signal, reference numeral CLK13 is a thirteenth sampling control clock signal, reference numeral CLK16 is a sixteenth sampling control clock signal, reference numeral CLK17 is a seventeenth sampling control clock signal, reference numeral CLK20 is a twentieth sampling control clock signal, reference numeral CLK21 is a twenty-first sampling control clock signal, reference numeral CLK24 is a twenty-fourth sampling control clock signal;
the first data carried by the RDAT is labeled D1, the fourth data carried by the RDAT is labeled D4, the fifth data carried by the RDAT is labeled D5, the eighth data carried by the RDAT is labeled D8, the ninth data carried by the RDAT is labeled D9, the twelfth data carried by the RDAT is labeled D12, the thirteenth data carried by the RDAT is labeled D13, the sixteenth data carried by the RDAT is labeled D16, the seventh data carried by the RDAT is labeled D17, the twenty-second data carried by the RDAT is labeled D20, the twenty-first data carried by the RDAT is labeled D21, and the twenty-fourth data carried by the RDAT is labeled D24;
and as shown in fig. 8, when EN1 is high voltage, CLK1, CLK4, CLK5 and CLK8 sequentially reach a rising edge; the first parallel data output end, the second parallel data output end, the third parallel data output end, the fourth parallel data output end, the fifth parallel data output end, the sixth parallel data output end, the seventh parallel data output end and the eighth parallel data output end sequentially output corresponding parallel data;
when the EN2 is a high voltage, CLK9, CLK12, CLK13 and CLK16 sequentially reach a rising edge, and a ninth sampling control clock signal, a tenth sampling control clock signal, an eleventh sampling control clock signal, a twelfth sampling control clock signal, a thirteenth sampling control clock signal, a fourteenth sampling control clock signal, a fifteenth sampling control clock signal and a sixteenth sampling control clock signal sequentially output corresponding parallel data;
when EN3 is at a high voltage, CLK17, CLK20, CLK21 and CLK24 sequentially reach a rising edge, and the seventeenth sampling control clock signal, the eighteenth sampling control clock signal, the nineteenth sampling control clock signal, the twentieth sampling control clock signal, the twenty-first sampling control clock signal, the twenty-second sampling control clock signal, the twenty-third sampling control clock signal and the twenty-fourth sampling control clock signal sequentially output corresponding parallel data.
In fig. 8, reference numeral S1 denotes a first sampling period, reference numeral S2 denotes a second sampling period, and reference numeral S3 denotes a third sampling period.
As shown in FIG. 9, based on the embodiment of the sampler of the present invention as shown in FIG. 1, N is equal to 3 and M is equal to 2;
the first sampling control circuit comprises a first sampling control unit circuit 81, a second first sampling control unit circuit 82 and a third first sampling control unit circuit 83;
the second sampling control circuit comprises a first second sampling control unit, a second sampling control unit and a third second sampling control unit;
the first second sampling control unit includes a first second sampling control unit circuit 121 and a second sampling control unit circuit 122;
the second sampling control unit includes a third second sampling control unit circuit 123 and a fourth second sampling control unit circuit 124;
the third second sampling control unit includes a fifth second sampling control unit circuit 125 and a sixth second sampling control unit circuit 126;
the first second sampling control unit circuit 121 is configured to convert the first serial data into the first second serial data under the control of the first sampling control signal;
the second sampling control unit circuit 122 is configured to convert the first serial data into second serial data under the control of a second sampling control signal;
the third second sampling control unit circuit 123 is configured to convert the second first serial data into third second serial data under the control of the third sampling control signal;
the fourth second sampling control unit circuit 124 is configured to convert the second first serial data into fourth second serial data under the control of a fourth sampling control signal;
the fifth second sampling control unit circuit 125 is configured to convert the third first serial data into fifth second serial data under the control of a fifth sampling control signal;
the sixth second sampling control unit circuit 126 is configured to convert the third first serial data into sixth second serial data under the control of a sixth sampling control signal;
the sampling circuit 13 is electrically connected to the first second sampling control unit circuit 121, the second sampling control unit circuit 122, the third second sampling control unit circuit 123, the fourth second sampling control unit circuit 124, the fifth second sampling control unit circuit 125, and the sixth second sampling control unit circuit 126, respectively, and is configured to convert the first second serial data, the second serial data, the third second serial data, the fourth second serial data, the fifth second serial data, and the sixth second serial data into corresponding parallel data under the control of a sampling control clock signal.
As shown in fig. 10, on the basis of the embodiment of the sampler shown in fig. 9,
the first sampling control unit circuit 81 includes a first nand gate AF1 and a first inverter F1;
the second first sampling control unit circuit 82 includes a second nand gate AF2 and a second inverter F2;
the third first sampling control unit circuit 83 includes a third nand gate AF3 and a third inverter F3;
the first second sampling control unit circuit 121 includes a fourth nand gate AF4 and a fourth inverter F4;
the second sampling control unit circuit 122 includes a fifth nand gate AF5 and a fifth inverter F4;
the third second sampling control unit circuit 123 includes a sixth nand gate AF6 and a sixth inverter F6;
the fourth second sampling control unit circuit 124 includes a seventh nand gate AF7 and a seventh inverter F7;
the fifth second sampling control unit circuit 125 includes an eighth nand gate AF8 and an eighth inverter F8;
the sixth second sampling control unit circuit 126 includes a ninth nand gate AF9 and a ninth inverter F9;
a first input end of the AF1 is connected with RDAT, a second input end of the AF1 is connected with a first enabling clock signal EN1, and an output end of the AF1 is electrically connected with an input end of the F1;
a first input end of the AF2 is connected with RDAT, a second input end of the AF2 is connected with a second enabling clock signal EN2, and an output end of the AF2 is electrically connected with an input end of the F2;
a first input end of the AF3 is connected with RDAT, a second input end of the AF3 is connected with a third enabling clock signal EN3, and an output end of the AF3 is electrically connected with an input end of the F3;
a first input end of the AF4 is electrically connected with an output end of the F4, a second input end of the AF4 is connected to the fourth enable clock signal EN1.1, an output end of the AF4 is electrically connected with an input end of the F4, and an output end of the F4 is used for outputting first second serial data RDAT 1;
a first input end of the AF5 is electrically connected with an output end of the F5, a second input end of the AF5 is connected to the fifth enable clock signal EN1.2, an output end of the AF5 is electrically connected with an input end of the F5, and an output end of the F5 is used for outputting a second serial data RDAT 2;
a first input end of the AF6 is electrically connected with an output end of the F6, a second input end of the AF4 is connected to a sixth enable clock signal EN2.1, an output end of the AF6 is electrically connected with an input end of the F6, and an output end of the F6 is used for outputting third second serial data RDAT 3;
a first input end of the AF7 is electrically connected with an output end of the F7, a second input end of the AF7 is connected to the seventh enable clock signal EN2.2, an output end of the AF7 is electrically connected with an input end of the F7, and an output end of the F7 is used for outputting fourth second serial data RDAT 4;
a first input end of the AF8 is electrically connected with an output end of the F8, a second input end of the AF8 is connected to the eighth enable clock signal EN3.1, an output end of the AF8 is electrically connected with an input end of the F8, and an output end of the F8 is used for outputting fifth second serial data RDAT 5;
a first input end of the AF9 is electrically connected with an output end of the F9, a second input end of the AF9 is connected to the ninth enable clock signal EN3.2, an output end of the AF9 is electrically connected with an input end of the F9, and an output end of the F9 is used for outputting a sixth second serial data RDAT 4.
In the embodiment shown in fig. 10, EN1, EN2, and EN3 are input control signals, and EN1.1, EN1.2, EN2.1, EN2.2, EN3.1, and EN3.2 sample control signals.
In fig. 10 and 12, reference numeral C1 denotes a first load capacitor, reference numeral C2 denotes a second load capacitor, reference numeral C3 denotes a third load capacitor, reference numeral C4 denotes a fourth load capacitor, reference numeral C5 denotes a fifth load capacitor, and reference numeral C6 denotes a sixth load capacitor.
As shown in fig. 11, when the sampler shown in fig. 10 of the present invention is in operation, the sampling period includes a first sampling period S1, a second sampling period S2, a third sampling period S3, a fourth sampling period S4, a fifth sampling period S5, and a sixth sampling period S6, which are sequentially set;
at the first sampling period S1, EN1 is a high voltage, EN2 and EN3 are low voltages, EN1.1 is a high voltage, EN1.2, EN2.1, EN2.2, EN3.1 and EN3.2 are all low voltages, the first sampling control unit circuit 81 and the first second sampling control unit circuit 121 operate to output the first second serial data RDAT1 through the output terminal of F4;
at the second sampling period S2, EN2 is a high voltage, EN1 and EN3 are low voltages, EN1.2 is a high voltage, EN1.1, EN2.1, EN2.2, EN3.1 and EN3.2 are all low voltages, the first sampling control unit circuit 81 and the second sampling control unit circuit 122 operate to output the second serial data RDAT2 through the output terminal of F5;
at the third sampling period S3, EN2 is a high voltage, EN1 and EN3 are low voltages, EN2.1 is a high voltage, EN1.1, EN1.2, EN2.2, EN3.1 and EN3.2 are all low voltages, the second first sampling control unit circuit 82 and the third second sampling control unit circuit 123 operate to output the third second serial data RDAT3 through the output terminal of F6;
at a fourth sampling period S4, EN2 is a high voltage, EN1 and EN3 are low voltages, EN2.2 is a high voltage, EN1.1, EN2.1, EN3.1 and EN3.2 are all low voltages, the second first sampling control unit circuit 81 and the fourth second sampling control unit circuit 124 operate to output a fourth second serial data RDAT4 through an output terminal of F7;
at a fifth sampling period S5, EN3 is a high voltage, EN1 and EN2 are low voltages, EN3.1 is a high voltage, EN1.1, EN1.2, EN2.1, EN2.2 and EN3.2 are all low voltages, the third first sampling control unit circuit 83 and the fifth second sampling control unit circuit 125 operate to output a fifth second serial data RDAT5 through an output terminal of F8;
in the sixth sampling period S6, EN3 is a high voltage, EN1 and EN2 are low voltages, EN3.2 is a high voltage, EN1.1, EN2.1, EN2.2 and EN3.1 are all low voltages, the third first sampling control unit circuit 83 and the sixth second sampling control unit circuit 126 operate to output the sixth second serial data RDAT6 through the output terminal of F9.
As shown in fig. 12, on the basis of the embodiment of the sampler shown in fig. 10, the sampling circuit includes a first sampling unit 61, a second sampling unit 62, a third sampling unit 63, a fourth sampling unit 64, a fifth sampling unit 65, and a sixth sampling unit 66;
the first sampling unit 61 comprises a first D flip-flop, a second D flip-flop \ a third D flip-flop and a fourth D flip-flop; the first sampling unit 62 includes a fifth D flip-flop, a sixth D flip-flop, a seventh D flip-flop, and an eighth D flip-flop;
the input end of the first D trigger is connected to the RDAT1, and the output end of the first D trigger is electrically connected with the first parallel data output end; a control end of the first D trigger is accessed to a first sampling control clock signal;
the input end of the second D flip-flop is connected to the RDAT1, and the output end of the second D flip-flop is electrically connected with the second parallel data output end; the control end of the second D trigger is connected with a second sampling control clock signal;
the input end of the third D flip-flop is connected to the RDAT1, and the output end of the third D flip-flop is electrically connected with the third parallel data output end; a control end of the third D trigger is accessed to a third sampling control clock signal;
the input end of the fourth D flip-flop is connected to the RDAT1, and the output end of the fourth D flip-flop is electrically connected with the fourth parallel data output end; a control end of the fourth D trigger is connected with a fourth sampling control clock signal;
the input end of the fifth D flip-flop is connected to the RDAT2, and the output end of the fifth D flip-flop is electrically connected with the fifth parallel data output end; a control end of the fifth D trigger is accessed to a fifth sampling control clock signal;
the input end of the sixth D trigger is connected to the RDAT2, and the output end of the sixth D trigger is electrically connected with the sixth parallel data output end; a control end of the sixth D trigger is accessed to a sixth sampling control clock signal;
the input end of the seventh D flip-flop is connected to the RDAT2, and the output end of the seventh D flip-flop is electrically connected with the seventh parallel data output end; a control end of the seventh D trigger is connected with a seventh sampling control clock signal;
the input end of the eighth D flip-flop is connected to the RDAT2, and the output end of the eighth D flip-flop is electrically connected with the eighth parallel data output end; a control end of the eighth D trigger is accessed to an eighth sampling control clock signal;
the third sampling unit 63 includes a ninth D flip-flop, a tenth D flip-flop, an eleventh D flip-flop, and a twelfth D flip-flop, and the fourth sampling unit 64 includes a thirteenth D flip-flop, a fourteenth D flip-flop, a fifteenth D flip-flop, and a sixteenth D flip-flop;
the input end of the ninth D flip-flop is connected to the RDAT3, and the output end of the ninth D flip-flop is electrically connected with the ninth parallel data output end; a control end of the ninth D trigger is connected with a ninth sampling control clock signal;
the input end of the tenth D flip-flop is connected to the RDAT3, and the output end of the tenth D flip-flop is electrically connected with the tenth parallel data output end; a control end of the tenth D trigger is accessed to a tenth sampling control clock signal;
the input end of the eleventh D flip-flop is connected to the RDAT3, and the output end of the eleventh D flip-flop is electrically connected with the eleventh parallel data output end; a control end of the eleventh D trigger is connected with an eleventh sampling control clock signal;
the input end of the twelfth D trigger is connected to the RDAT3, and the output end of the twelfth D trigger is electrically connected with the twelfth parallel data output end; a control end of the twelfth D trigger is connected with a twelfth sampling control clock signal;
the input end of the thirteenth D flip-flop is connected with the RDAT4, and the output end of the thirteenth D flip-flop is electrically connected with the thirteenth parallel data output end; a control end of the thirteenth D trigger is connected with a thirteenth sampling control clock signal;
the input end of the fourteenth D flip-flop is connected to the RDAT4, and the output end of the fourteenth D flip-flop is electrically connected with the fourteenth parallel data output end; a control end of the fourteenth D trigger is connected to a fourteenth sampling control clock signal;
the input end of the fifteenth D flip-flop is connected to the RDAT4, and the output end of the fifteenth D flip-flop is electrically connected with the fifteenth parallel data output end; a control end of the fifteenth D trigger is connected with a fifteenth sampling control clock signal;
the input end of the sixteenth D trigger is connected to the RDAT4, and the output end of the sixteenth D trigger is electrically connected with the sixteenth parallel data output end; a control end of the sixteenth D trigger is connected with a sixteenth sampling control clock signal;
the fifth sampling unit 65 includes a seventeenth D flip-flop, an eighteenth D flip-flop, a nineteenth D flip-flop, and a twentieth D flip-flop; the fifth sampling unit 66 includes a twenty-first D flip-flop, a twenty-second D flip-flop, a twenty-third D flip-flop, and a twenty-fourth D flip-flop;
the input end of the seventeenth D flip-flop is connected to the RDAT5, and the output end of the seventeenth D flip-flop is electrically connected with the seventeenth parallel data output end; a control end of the seventeenth D trigger is connected with a seventeenth sampling control clock signal;
the input end of the eighteenth D trigger is connected with the RDAT5, and the output end of the eighteenth D trigger is electrically connected with the eighteenth parallel data output end; a control end of the eighteenth D trigger is connected with an eighteenth sampling control clock signal;
the input end of the nineteenth D flip-flop is connected to the RDAT5, and the output end of the nineteenth D flip-flop is electrically connected with the nineteenth parallel data output end; a control end of the nineteenth D trigger is connected to a nineteenth sampling control clock signal;
the input end of the twentieth flip-flop is connected to the RDAT5, and the output end of the twentieth flip-flop is electrically connected with the twentieth parallel data output end; a control end of the twentieth trigger is connected to a twentieth sampling control clock signal;
the input end of the twenty-first D trigger is connected with the RDAT6, and the output end of the twenty-first D trigger is electrically connected with the twenty-first parallel data output end; a control end of the twenty-first D trigger is connected with a twenty-first sampling control clock signal;
the input end of the twenty-second D trigger is connected to the RDAT6, and the output end of the twenty-second D trigger is electrically connected with the twenty-second parallel data output end; a control end of the twenty-second D trigger is connected with a twenty-second sampling control clock signal;
the input end of the twenty-third D trigger is connected to the RDAT6, and the output end of the twenty-third D trigger is electrically connected with the twenty-third parallel data output end; a control end of the twenty-third trigger is connected with a twenty-third sampling control clock signal;
the input end of the twenty-fourth D trigger is connected to the RDAT6, and the output end of the twenty-fourth D trigger is electrically connected with the twenty-fourth parallel data output end; and the control end of the twenty-fourth D trigger is connected with a twenty-fourth sampling control clock signal.
In fig. 12, labeled DOUT [1:4], is a first set of parallel data outputs comprising: a first parallel data output, a second parallel data output, a third parallel data output, and a fourth parallel data output;
labeled DOUT [5:8], is a second set of parallel data outputs comprising: a fifth parallel data output terminal, a sixth parallel data output terminal, a seventh parallel data output terminal, and an eighth parallel data output terminal;
labeled CLK [1:4] is a first set of clock signals comprising: a first sampling control clock signal, a second sampling control clock signal, a third sampling control clock signal and a fourth sampling control clock signal;
labeled CLK [5:6] is a second set of clock signals comprising: a fifth sampling control clock signal, a sixth sampling control clock signal, a seventh sampling control clock signal, and an eighth sampling control clock signal;
labeled DOUT [9:12] is a third set of parallel data outputs comprising: a ninth parallel data output, a tenth parallel data output, an eleventh parallel data output, and a twelfth parallel data output;
labeled DOUT [13:16], is a fourth set of parallel data outputs comprising: a thirteenth parallel data output terminal, a fourteenth parallel data output terminal, a fifteenth parallel data output terminal, and a sixteenth parallel data output terminal;
labeled CLK [9:12] is a third set of clock signals comprising: a ninth sampling control clock signal, a tenth sampling control clock signal, an eleventh sampling control clock signal, and a twelfth sampling control clock signal;
labeled CLK [13:16] is a fourth set of clock signals comprising: a thirteenth sampling control clock signal, a fourteenth sampling control clock signal, a fifteenth sampling control clock signal, a sixteenth sampling control clock signal;
labeled DOUT [17:20] is a fifth set of parallel data outputs comprising: a seventeenth parallel data output terminal, an eighteenth parallel data output terminal, a nineteenth parallel data output terminal, and a twentieth parallel data output terminal;
labeled DOUT [17:20] is a sixth set of parallel data outputs comprising: a twenty-first parallel data output terminal, a twenty-second parallel data output terminal, a twenty-third parallel data output terminal, and a twenty-fourth parallel data output terminal;
labeled CLK [17:20] is a fifth set of clock signals comprising: a seventeenth sampling control clock signal, an eighteenth sampling control clock signal, a nineteenth sampling control clock signal, and a twentieth sampling control clock signal;
labeled CLK [21:24] is a sixth set of clock signals comprising: a twenty-first sampling control clock signal, a twenty-second sampling control clock signal, a twenty-third sampling control clock signal, and a twenty-fourth sampling control clock signal.
Fig. 13 is an operation timing chart of the sampler shown in fig. 12.
As shown in fig. 13, reference numeral CLK1 is a first sampling control clock signal, reference numeral CLK4 is a fourth sampling control clock signal, reference numeral CLK5 is a fifth sampling control clock signal, reference numeral CLK8 is an eighth sampling control clock signal, reference numeral CLK9 is a ninth sampling control clock signal, reference numeral CLK12 is a twelfth sampling control clock signal, reference numeral CLK13 is a thirteenth sampling control clock signal, reference numeral CLK16 is a sixteenth sampling control clock signal, reference numeral CLK17 is a seventeenth sampling control clock signal, reference numeral CLK20 is a twentieth sampling control clock signal, reference numeral CLK21 is a twenty-first sampling control clock signal, reference numeral CLK24 is a twenty-fourth sampling control clock signal;
the first data carried by the RDAT is labeled D1, the fourth data carried by the RDAT is labeled D4, the fifth data carried by the RDAT is labeled D5, the eighth data carried by the RDAT is labeled D8, the ninth data carried by the RDAT is labeled D9, the twelfth data carried by the RDAT is labeled D12, the thirteenth data carried by the RDAT is labeled D13, the sixteenth data carried by the RDAT is labeled D16, the seventh data carried by the RDAT is labeled D17, the twenty-second data carried by the RDAT is labeled D20, the twenty-first data carried by the RDAT is labeled D21, and the twenty-fourth data carried by the RDAT is labeled D24;
and as shown in fig. 13, when EN1 and EN1.1 are high voltage, CLK1 and CLK4 sequentially reach rising edges; CLK5 and CLK8 in turn reach a rising edge when EN1 and EN1.2 are high; the first parallel data output end, the second parallel data output end, the third parallel data output end, the fourth parallel data output end, the fifth parallel data output end, the sixth parallel data output end, the seventh parallel data output end and the eighth parallel data output end sequentially output corresponding parallel data;
CLK9 and CLK12 in turn reach a rising edge when EN2 and EN2.1 are high; when EN2 and EN2.2 are high voltage, CLK13 and CLK16 sequentially reach a rising edge, and the ninth sampling control clock signal, the tenth sampling control clock signal, the eleventh sampling control clock signal, the twelfth sampling control clock signal, the thirteenth sampling control clock signal, the fourteenth sampling control clock signal, the fifteenth sampling control clock signal, and the sixteenth sampling control clock signal sequentially output corresponding parallel data;
CLK17 and CLK20 in turn reach a rising edge when EN3 and EN3.1 are high; when EN3 and EN3.2 are high voltage, CLK21 and CLK24 sequentially reach a rising edge, and the seventeenth sampling control clock signal, the eighteenth sampling control clock signal, the nineteenth sampling control clock signal, the twentieth sampling control clock signal, the twenty-first sampling control clock signal, the twenty-second sampling control clock signal, the twenty-third sampling control clock signal, and the twenty-fourth sampling control clock signal sequentially output corresponding parallel data.
The display driving chip provided by the embodiment of the invention comprises the sampler.
In the embodiment of the present invention, the display driving chip may further include a clock signal generator, a delay circuit, and a delay locked loop, wherein,
the clock signal generator is used for extracting clock edge information in original serial input data to generate a response input clock signal;
the delay circuit is used for controlling the original serial input data to delay for a preset time so as to obtain serial input data, and the serial input data is provided to the sampler;
the delay locked loop converts the input clock signal into a plurality of sampling control clock signals and provides the sampling control clock signals to the sampler.
The display device provided by the embodiment of the invention comprises the display driving chip.
While the foregoing is directed to the preferred embodiment of the present invention, it will be understood by those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the invention as defined in the appended claims.

Claims (8)

1. A sampler is characterized by comprising a first sampling control circuit, a second sampling control circuit and a sampling circuit, wherein the second sampling control circuit comprises N second sampling control units; the second sampling control unit comprises M second sampling control unit circuits; the first sampling control circuit is used for converting serial input data into N first serial data, and N and M are positive integers; n is greater than 1, and/or M is greater than 1;
the mth second sampling control unit circuit in the nth second sampling control unit is used for converting the nth first serial data into corresponding second serial data under the control of the corresponding sampling control signal;
the sampling circuit is electrically connected with the second sampling control unit circuit and is used for converting the second serial data into corresponding parallel data under the control of a sampling control clock signal;
n is a positive integer less than or equal to N, and M is a positive integer less than or equal to M;
the first sampling control circuit comprises N first sampling control unit circuits, and the nth first sampling control unit circuit is used for converting the serial input data into nth first serial data.
2. The sampler of claim 1, wherein the nth first sampling control unit circuit comprises an nth first control inverter and an nth second control inverter;
the input end of the nth first control inverter is connected with the serial input data, and the output end of the nth first control inverter is electrically connected with the input end of the nth second control inverter;
and the output end of the nth second control inverter is used for outputting the nth first serial data.
3. The sampler of claim 1, wherein the nth first sampling control unit circuit comprises an nth control nand gate and an nth control inverter;
the first input end of the nth control NAND gate is connected with the serial input data, the second input end of the nth control NAND gate is connected with the nth input control signal, and the output end of the nth control NAND gate is electrically connected with the input end of the nth control inverter;
and the output end of the nth control inverter is used for outputting the nth first serial data.
4. The sampler of any one of claims 1 to 3, wherein the mth one of the nth second sampling control units comprises a sampling NAND gate and a sampling inverter;
the first input end of the sampling NAND gate is connected with the nth first serial data, the second input end of the sampling NAND gate is connected with the corresponding sampling control signal, the output end of the sampling NAND gate is electrically connected with the input end of the sampling inverter, the output end of the sampling inverter is electrically connected with the sampling circuit, and the sampling inverter is used for outputting the corresponding second serial data to the sampling circuit through the output end of the sampling inverter.
5. The sampler of any one of claims 1 to 3, wherein the sampling circuit comprises a plurality of D flip-flops;
the input end of the D trigger is connected with the second serial data, the control end of the D trigger is connected with the corresponding sampling control clock signal, and the output end of the D trigger is used for outputting the corresponding parallel data.
6. A display driver chip comprising a sampler as claimed in any one of claims 1 to 5.
7. The display driver chip of claim 6, further comprising a clock signal generator, a delay circuit, and a delay locked loop, wherein,
the clock signal generator is used for extracting clock edge information in original serial input data to generate a response input clock signal;
the delay circuit is used for controlling the time delay of the original serial input data for a preset time to obtain serial input data and providing the serial input data to the sampler;
the delay locked loop converts the input clock signal into a plurality of sampling control clock signals and provides the sampling control clock signals to the sampler.
8. A display device comprising the display driver chip according to claim 6 or 7.
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