CN113963651A

CN113963651A - Data receiving circuit, display driving chip and electronic equipment

Info

Publication number: CN113963651A
Application number: CN202111326438.5A
Authority: CN
Inventors: 吴嘉训; 苏嘉伟
Original assignee: Jichuang North Zhuhai Technology Co ltd
Current assignee: Jichuang North Zhuhai Technology Co ltd
Priority date: 2021-11-10
Filing date: 2021-11-10
Publication date: 2022-01-21

Abstract

The present disclosure relates to a data receiving circuit, a display driving chip and an electronic device, the circuit including: a clock generation module comprising: a multiphase clock generating unit and a buffer control unit; a buffer module, comprising: a first buffer unit, m second buffer units; and the sampling module comprises a plurality of sampling units. According to the data receiving circuit provided by the embodiment of the disclosure, n second clock signals are generated by the multiphase clock generating unit according to the first clock signal, m buffering control signals are generated by the buffering control unit according to the n second clock signals, so as to control the working states of the m second buffering units, and dynamic start and stop of each second buffering unit are realized, so that power supply bounce of the first buffering unit of the data receiving circuit is effectively reduced, thereby eliminating jitter of output display data of the data receiving circuit, improving accuracy of display of the data to be displayed by a display device, and improving user experience.

Description

Data receiving circuit, display driving chip and electronic equipment

Technical Field

The present disclosure relates to the field of display technologies, and in particular, to a data receiving circuit, a display driver chip, and an electronic device.

Background

Generally, when a display device normally operates, a receiving circuit in the related art buffers display data once by using one buffer and directly samples the once buffered display data by using a plurality of samplers when receiving the display data and a clock signal, and then combines and outputs the sampled data. However, the buffer with high data driving capability is prone to generate large peak current to cause Power bounce (Power bounce), which causes Jitter (Jitter) of output display data, and the display device cannot display accurately.

Disclosure of Invention

According to an aspect of the present disclosure, there is provided a data receiving circuit, applied to a display panel, for receiving data to be displayed and a first clock signal output from a timing controller, the circuit including:

a clock generation module comprising:

the multi-phase clock generating unit is used for generating n second clock signals according to the first clock signal, wherein each second clock signal has different phases, each second clock signal corresponds to each data bit of the data to be displayed one by one, and n is a positive integer;

the buffer control unit is connected with the multiphase clock generation unit and used for generating m buffer control signals according to n second clock signals, wherein m is less than or equal to n and is a positive integer;

a buffer module, comprising:

the first buffer unit is used for carrying out first-stage buffer processing on the data to be displayed and outputting first buffer data;

the m second buffer units are connected to the first buffer unit and the buffer control unit, each second buffer unit is used for buffering each data unit of the first buffer data, each data unit comprises at least one bit of data of the first buffer data, each second buffer unit corresponds to each buffer control signal one by one, and when the buffer control signals are in an effective state, the second buffer units are in a starting state and output second buffer data; otherwise, the second buffer unit is in a closed state;

and the sampling module is connected with the buffering module and comprises a plurality of sampling units, and each sampling unit is used for sampling the second buffering data output by each second buffering unit to obtain sampling data.

In one possible embodiment, each sampling unit includes at least one sampler, and each sampler corresponds to each bit data of the second buffered data and each second clock signal.

In one possible implementation, each data unit comprises n/m bit data and each sampling unit comprises n/m samplers.

In one possible embodiment, when the k buffered control signals are in an active state, the m-k control signals are in an inactive state, where k < m and k is a positive integer.

In one possible implementation, the clock generation module further includes:

and the output clock generating unit is connected with the multiphase clock generating unit and used for generating output clock signals according to the n second clock signals.

In a possible implementation manner, the sampling module is further configured to synthesize a plurality of sampling data, and obtain and output the data to be displayed.

In one possible implementation, the circuit further includes:

and the driving module is connected with the sampling module and the clock generating module and used for driving the display panel to display according to the output clock signal and the data to be displayed.

In one possible embodiment, the display panel includes at least one of a liquid crystal display panel, an organic light emitting diode display panel, a quantum dot light emitting diode display panel, a mini light emitting diode display panel, and a micro light emitting diode display panel.

According to an aspect of the present disclosure, a display driving chip is provided, which includes the data receiving circuit.

According to an aspect of the present disclosure, there is provided an electronic device including the display driving chip.

In one possible implementation, the electronic device comprises a display, a smartphone, or a portable device.

In each aspect of the embodiment of the disclosure, n second clock signals are generated by the multiphase clock generation unit according to the first clock signal, m buffer control signals are generated by the buffer control unit according to the n second clock signals, so as to control the operating states of the m second buffer units, and dynamic enabling and closing of each second buffer unit is realized, so as to effectively reduce power bounce of the first buffer unit of the data receiving circuit, thereby eliminating jitter of output display data of the data receiving circuit, improving accuracy of display of the data to be displayed by the display device, and improving user experience.

It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure. Other features and aspects of the present disclosure will become apparent from the following detailed description of exemplary embodiments, which proceeds with reference to the accompanying drawings.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present disclosure and, together with the description, serve to explain the principles of the disclosure.

Fig. 1 shows a block diagram of a data receiving circuit according to an embodiment of the present disclosure.

FIG. 2 shows a timing diagram according to an embodiment of the present disclosure.

Fig. 3 shows a block diagram of a data receiving circuit according to an embodiment of the present disclosure.

Detailed Description

Various exemplary embodiments, features and aspects of the present disclosure will be described in detail below with reference to the accompanying drawings. In the drawings, like reference numbers can indicate functionally identical or similar elements. While the various aspects of the embodiments are presented in drawings, the drawings are not necessarily drawn to scale unless specifically indicated.

In the description of the present disclosure, it is to be understood that the terms "length," "width," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," and the like, as used herein, refer to an orientation or positional relationship indicated in the drawings, which is solely for the purpose of facilitating the description and simplifying the description, and does not indicate or imply that the referenced device or element must have a particular orientation, be constructed and operated in a particular orientation, and, therefore, should not be taken as limiting the present disclosure.

Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the present disclosure, "a plurality" means two or more unless specifically limited otherwise.

In the present disclosure, unless otherwise expressly stated or limited, the terms "mounted," "connected," "secured," and the like are to be construed broadly and can, for example, be fixedly connected, detachably connected, or integral; can be mechanically or electrically connected; either directly or indirectly through intervening media, either internally or in any other relationship. The specific meaning of the above terms in the present disclosure can be understood by those of ordinary skill in the art as appropriate.

The word "exemplary" is used exclusively herein to mean "serving as an example, embodiment, or illustration. Any embodiment described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other embodiments.

The term "and/or" herein is merely an association describing an associated object, meaning that three relationships may exist, e.g., a and/or B, may mean: a exists alone, A and B exist simultaneously, and B exists alone. In addition, the term "at least one" herein means any one of a plurality or any combination of at least two of a plurality, for example, including at least one of A, B, C, and may mean including any one or more elements selected from the group consisting of A, B and C.

Furthermore, in the following detailed description, numerous specific details are set forth in order to provide a better understanding of the present disclosure. It will be understood by those skilled in the art that the present disclosure may be practiced without some of these specific details. In some instances, methods, means, elements and circuits that are well known to those skilled in the art have not been described in detail so as not to obscure the present disclosure.

In the related art, a display device mainly includes a display panel, a timing control chip (i.e., a TCON chip), and a display driving chip. When the display equipment works normally, the time sequence control chip transmits a frame of display Data [ n:1] and a clock signal CLK to the display driving chip through a high-speed interface (RX), so that the display driving chip drives the display panel to display images according to the clock signal CLK and the display Data. The display driving chip has a data receiving circuit, and generally, the data receiving circuit includes a main data buffer, a multi-phase frequency generator, a data sampling unit including a plurality of sub-samplers, and a frequency recovery unit.

After receiving the display Data [ n:1] and the clock signal CLK, the multiphase frequency generator generates a multiphase clock signal CLK [ n:1] to cause the plurality of sub-samplers to respectively Data-sample the display Data [ n:1] according to the multiphase clock signal CLK [ n:1] to sequentially output sub-display Data to be combined into output display Data _ out [ n:1 ]. And the frequency recovery unit generates an output clock signal CLK _ out according to the multi-phase clock signal CLK [ n:1 ].

However, as described in the background art, in order to enable each sub-sampler to smoothly sample the display Data [ n:1], the Data driving capability of the front main Data buffer must be sufficiently large, and as the number of display Data increases, the Data driving capability of the main Data buffer must be correspondingly improved. However, the main Data buffer with high Data driving capability is prone to generate large peak current to cause power bounce, resulting in Jitter (Jitter) defect in the output display Data _ out [ n:1 ].

The data receiving circuit provided by the embodiment of the disclosure is applied to a display panel, and receives data to be displayed and a first clock signal output by a timing controller, and the circuit includes: a clock generation module comprising: a multiphase clock generating unit and a buffer control unit; a buffer module, comprising: a first buffer unit, m second buffer units; and the sampling module comprises a plurality of sampling units. The multi-phase clock generating unit generates n second clock signals according to the first clock signals, the buffer control unit generates m buffer control signals according to the n second clock signals to control the working states of the m second buffer units, dynamic starting and closing of each second buffer unit are achieved, power supply rebounding of the first buffer unit of the data receiving circuit is effectively reduced, jitter of output display data of the data receiving circuit is eliminated, accuracy of display of the data to be displayed by display equipment is improved, and user experience is improved.

The data receiving circuit of the embodiment of the disclosure can be applied to a display driving chip.

The data receiving circuit and the display driving chip of the embodiment of the disclosure can be applied to electronic equipment.

The electronic device may also be, for example, a User Equipment (UE), a mobile device, a User terminal, a handheld device, a computing device, or a vehicle-mounted device, and some examples of the terminal are: a display, a Smart Phone or a portable device, a Mobile Phone (Mobile Phone), a tablet computer, a notebook computer, a palmtop computer, a Mobile Internet Device (MID), a wearable device, a Virtual Reality (VR) device, an Augmented Reality (AR) device, a wireless terminal in Industrial Control (Industrial Control), a wireless terminal in unmanned driving (self), a wireless terminal in Remote Surgery (Remote Surgery), a wireless terminal in Smart Grid, a wireless terminal in Transportation Safety (Transportation Safety), a wireless terminal in Smart City (Smart City), a wireless terminal in Smart Home (Smart Home), a wireless terminal in car networking, and the like. For example, the server may be a local server or a cloud server.

Referring to fig. 1, fig. 1 is a block diagram of a data receiving circuit according to an embodiment of the disclosure.

The circuit is applied to a display panel and receives data to be displayed and a first clock signal output by a timing controller, as shown in fig. 1, and the circuit comprises:

clock generation module 10, comprising:

a multiphase clock generating unit 110, configured to generate n second clock signals according to the first clock signal, where each second clock signal has a different phase, and each second clock signal corresponds to each data bit of the data to be displayed one by one, where n is a positive integer;

a buffer control unit 120, connected to the multiphase clock generating unit 110, for generating m buffer control signals according to n second clock signals, where m is greater than or equal to n and is a positive integer;

a buffer module 20 comprising:

the first buffer unit 210 is configured to perform first-level buffer processing on the data to be displayed and output first buffer data;

m second buffer units 220, each of which is connected to the first buffer unit 210 and the buffer control unit 120, each of the second buffer units 220 being configured to buffer each data unit of the first buffered data, each data unit including at least one bit of the first buffered data, wherein each of the second buffer units 220 corresponds to each of the buffer control signals one to one, and when the buffer control signal is in an active state, the second buffer unit 220 is in an active state and outputs second buffered data; otherwise, the second buffer unit 220 is in a closed state;

the sampling module 30 is connected to the buffering module 20, and includes a plurality of sampling units 310, and each sampling unit 310 is configured to sample the second buffered data output by each second buffering unit 220 to obtain sampled data.

The embodiment of the present disclosure does not limit the specific implementation manner of each module and unit in the data receiving circuit, and those skilled in the art may implement the implementation by using related technologies as long as the functions of each module and unit provided by the embodiment of the present disclosure can be implemented.

The following provides an exemplary description of embodiments of the disclosure. It should be understood that the embodiments given in this disclosure are preferred embodiments, and those skilled in the art can reasonably extend, modify and obtain more embodiments according to the spirit of the claims that are claimed herein, and such embodiments should fall within the scope of the disclosure.

In a possible implementation manner, the multiphase clock generating unit 110 may be implemented by a delay circuit, or implemented in combination with a frequency dividing circuit, for example, the received first clock signal may be directly delayed multiple times to obtain a multiphase clock signal; the clock signal with the required frequency can be obtained through the frequency dividing circuit, and the delay circuit is used for delaying the clock signal for one time or more times to obtain the multiphase clock signal. Of course, the multiphase clock generating unit 110 may also be implemented by using a signal generating circuit, and generate a plurality of second clock signals with different phases according to parameters (such as frequency, pulse width, etc.) of the received first clock signal, or generate one second clock signal and then perform multiple time delays to obtain a plurality of second clock signals. It should be understood that the specific implementation manner of the multi-phase clock generation unit 110 is not limited in the embodiments of the present disclosure, and those skilled in the art may implement or use a multi-phase clock generator (multi-phase CLK Gen) in the related art as needed, for example, the multi-phase clock generator (multi-phase CLK Gen) directly generates a plurality of second clock signals according to the first clock signal.

For example, the rising edge of the second clock signal of the embodiment of the present disclosure corresponds to each data bit, and each second clock signal may be configured to collect the corresponding data bit at a time when the second clock signal is active (changes from low level to high level) and inactive (low level) at other times before the time.

In one example, the buffering control unit 120 of the data receiving circuit provided in the embodiment of the present disclosure may generate buffering control signals according to one or more second clock signals to control the operating state of the corresponding second buffering units 220, for example, if each data unit for buffering of the second buffering unit 220 includes s-bit data, the corresponding second clock signals are s, that is, s samplers 3110 share one second buffering unit 220 (for example, s ═ n ÷ m), in this case, the buffering control unit 120 may generate m buffering control signals according to timing sequence, in one of the buffering control signals (which may also be another number, for example, in one possible implementation, the number may be k, and when the k buffering control signals are in an active state, m-k control signals are in an inactive state, where k < m and k is a positive integer) when the buffering control signals are active (high level), the remaining m-1 buffer control signals are inactive (low), that is, the active buffer control signals control the corresponding second buffer units 220 to be in an active state, the corresponding s samplers 3110 may sample the second buffered data of the second buffer units 220 that are in normal operation, and the other second buffer units 220 are turned off.

An exemplary description follows.

Referring to fig. 2, fig. 2 is a timing diagram according to an embodiment of the disclosure.

In one example, as shown in fig. 2, if s is 3, each second buffer unit 220 in the embodiment of the present disclosure may buffer 3 bits (bits) of data, that is, three samplers 3110 share one second buffer unit 220.

In one example, as shown in FIG. 2, the respective second clock signals CLK [1] -CLK [ m ] have different phases, each second clock signal corresponding to a respective DATA bit, e.g., CLK [1] corresponds to a first bit of DATA to be Displayed (DATA).

In one example, as shown in fig. 2, each buffer control signal (DATA _ en [ m ]) has a different phase, and when the buffer control signal (DATA _ en [1]) is active (high level), the corresponding three samplers 3110 may sample the buffer DATA (i.e., the 1 st bit to 3 rd bit of the DATA to be displayed) in the second buffer unit 220, in which case the buffer control signal (DATA _ en [2]) to the buffer control signal (DATA _ en [ m ]) is inactive (low level), and each second buffer unit 220 corresponding to the buffer control signal (DATA _ en [2]) to the buffer control signal (DATA _ en [ m ]) is turned off.

For example, by the above design, for the sampler 3110 samplers [ n: n/m-1], DATA other than DATA [ n ] to DATA [ n/m-1] are invalid DATA, as shown in fig. 2, taking n to 3m as an example, 3 samplers share one second buffer unit 220, and the present disclosure turns on the corresponding second buffer unit 220DATA buffer only when the DATA is valid by using the buffer control signal DATA _ en [ m:1], so as to reduce the peak current of the buffer.

The embodiment of the present disclosure controls the working states of the m second buffer units 220 to dynamically enable and disable each second buffer unit 220, so as to effectively reduce power bounce of the first buffer unit 210 of the data receiving circuit, thereby eliminating jitter of output display data of the data receiving circuit. Illustratively, the embodiment of the disclosure provides a first buffer unit 210(Data buffer1) and m second buffer units 220Data buffers 2[ m:1], where m second buffer units 220Data buffers 2[ m:1] are shared by n/m component samplers 3110, and buffer control signals Data _ en [ m:1] generated by using a multi-phase clock, i.e., a plurality of second clock signals CLK [ n:1], may dynamically turn off each second buffer unit 220Data _ buffer2[ m:1] to reduce the peak current of the Data buffers, which may be 1/m.

Referring to fig. 3, fig. 3 is a block diagram of a data receiving circuit according to an embodiment of the disclosure.

In one possible implementation, as shown in fig. 3, each sampling unit 310 includes at least one sampler 3110, and each sampler 3110 corresponds to each bit data of the second buffered data and each second clock signal.

In one possible implementation, each data unit comprises n/m bit data and each sampling unit 310 comprises n/m samplers 3110.

Illustratively, taking n-40 and m-4 as an example, the number of the second buffer units 220 may be 4(Data buffers 2[4:1]), wherein each of the second buffer units 220 is shared by 10 samplers 3110, in which case, the buffer control signals Data _ en [4:1] generated using the multi-phase clock, i.e., the plurality of second clock signals CLK [40:1], may dynamically turn off each of the second buffer units 220Data _ buffers 2[4:1], and the peak current buffered theoretically may be reduced to 1/4.

Of course, the values of n and m are not limited in the embodiments of the present disclosure, and can be set by those skilled in the art as needed.

Table 1 shows data of peak current and average current of buffers of the data receiving circuit of the embodiment of the present disclosure and the data receiving circuit of the related art in different test modes.

TABLE 1

As can be seen from the data in table 1, compared to the data receiving circuit in the related art, under the display data Pattern of the CT, the peak current of the first buffer unit 210 (main buffer) of the data receiving circuit in the embodiment of the disclosure is reduced by 21.6%. On the other hand, under the ISI display data Pattern, the peak current of the first buffer unit 210 (main buffer) of the data receiving circuit of the embodiment of the present disclosure is reduced by 14.5%, and the average current is also reduced by 5.4%.

In a possible implementation, as shown in fig. 3, the clock generation module 10 may further include:

an output clock generating unit 130, connected to the multiphase clock generating unit 110, for generating an output clock signal according to the n second clock signals.

The embodiment of the present disclosure does not limit the specific implementation manner of the output clock generation unit 130, and those skilled in the art can implement the embodiment according to the related art.

In a possible implementation manner, the sampling module 30 is further configured to combine a plurality of sampling data, and obtain and output the data to be displayed.

In one possible implementation, as shown in fig. 3, the circuit may further include:

and the driving module 40 is connected to the sampling module 30 and the clock generating module 10, and is configured to drive the display panel to display according to the output clock signal and the data to be displayed.

The embodiment of the present disclosure does not limit the specific implementation manner of the driving module 40, and for example, the driving module 40 may be implemented by a display driving chip.

It is understood that the above-mentioned method embodiments of the present disclosure can be combined with each other to form a combined embodiment without departing from the logic of the principle, which is limited by the space, and the detailed description of the present disclosure is omitted. Those skilled in the art will appreciate that in the above methods of the specific embodiments, the specific order of execution of the steps should be determined by their function and possibly their inherent logic.

Having described embodiments of the present disclosure, the foregoing description is intended to be exemplary, not exhaustive, and not limited to the disclosed embodiments. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The terminology used herein is chosen in order to best explain the principles of the embodiments, the practical application, or improvements made to the technology in the marketplace, or to enable others of ordinary skill in the art to understand the embodiments disclosed herein.

Claims

1. A data receiving circuit, applied to a display panel, for receiving data to be displayed and a first clock signal output from a timing controller, the circuit comprising:

a clock generation module comprising:

a buffer module, comprising:

2. The circuit of claim 1, wherein each sampling unit comprises at least one sampler, each sampler corresponding to each bit of data of the second buffered data and each second clock signal, respectively.

3. The circuit of claim 2 wherein each data cell comprises n/m bits of data and each sample cell comprises n/m samplers.

4. The circuit of claim 1, wherein m-k control signals are inactive when k buffered control signals are active, wherein k < m and k is a positive integer.

5. The circuit of claim 1, wherein the clock generation module further comprises:

6. The circuit of claim 5, wherein the sampling module is further configured to combine a plurality of sampling data to obtain and output the data to be displayed.

7. The circuit of claim 6, further comprising:

8. The circuit of claim 1, wherein the display panel comprises at least one of a liquid crystal display panel, an organic light emitting diode display panel, a quantum dot light emitting diode display panel, a mini light emitting diode display panel, and a micro light emitting diode display panel.

9. A display driver chip, characterized in that the display driver chip comprises the data receiving circuit of any one of claims 1 to 8.

10. An electronic device characterized in that it comprises a display driver chip according to claim 9.

11. The electronic device of claim 10, wherein the electronic device comprises a display, a smartphone, or a portable device.