JP2008102797A - Semiconductor device, semiconductor integrated circuit device and allowable phase difference measurement circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device that can effectively reduce a current peak at low cost. <P>SOLUTION: Clocks for a first module 21 and a second module 22 are synchronized in Step ST1 before the first module 21 transfers data to the second module 22 in Step ST2. The clock phase difference between the clock CLKA for the first module 21 and the clock CLKB for the second module 22 is set to a predetermined value in Step ST3 before the first module 21 and second module 22 execute respective predetermined operations independently in Step ST4. The clock CLKA for the first module 21 and a clock CLKP for a CPU 25 are synchronized in Step ST5 before the CPU 25 reads the operation result of the first module 21 in Step ST6. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a semiconductor device (concept including a semiconductor integrated circuit) having clock supply means for supplying a clock to a plurality of modules, and more particularly, to contents of clock skew (phase) adjustment by the clock supply means.

  Conventionally, the clock phase of each module is fixed for each chip, and the clock phase difference between modules is made as small as possible. In order to reduce the clock skew inside the LSI, there are techniques such as H-Tree, a clock tree using equal-length wiring, and a clock wiring with a mesh structure, which are being studied daily.

  As a CAD tool, a technique for inserting a clock circuit so as to bring the clock skew closer to “0” by a CTS (Clock tree synthesis) tool or the like has been studied.

  Many LSI internal circuits such as microcomputers are designed with clock synchronization, and many circuits operate in accordance with clock edges. In particular, an LSI using the most advanced fine process has a large variation due to the ambient conditions and manufacturing of the LSI, and it is necessary to have a margin for such fluctuations. Therefore, in general operation of LSI internal circuits, most of the circuits operate in the time zone immediately after the edge of the clock, but most circuits do not operate when a relatively long time elapses immediately after the edge and approaches the next edge. The tendency is strong.

  Accordingly, since most of the power consumed by the LSI is consumed immediately after the clock edge, the peak value of the power supply current becomes considerably larger than the average current.

  When the current peak is large, there is a problem that a voltage drop occurs due to the resistance of the power supply wiring inside the LSI, causing malfunction of the circuit and a decrease in the operation speed. In addition, when the current peak is large, EMI (Electromagnetic Interference) noise increases, and there is a concern about the influence on the outside of the LSI.

  As a general method for solving the above problem, there is a method for preventing a voltage drop even at a current peak by using a low impedance power supply wiring. However, this method has a problem that the die area (chip area) of the LSI becomes large because the power supply wiring needs to be thick. Moreover, EMI cannot be solved with a low-impedance power supply wiring.

  As another general method for solving the above problem, there is a method using a bypass capacitor. There is a method of making a capacitor with a gate oxide film inside an LSI. However, when an LSI built-in bypass capacitor is inserted, there is a problem that the LSI die area is increased accordingly. In addition, since it is made of a limited material such as a gate oxide film, it is difficult to cope with various frequency components, and the effect is not so high in practice.

  As a technique for solving the above-described problem, a phase shift type clock driver that supplies a clock whose phase is shifted for each module to a plurality of modules each performing a predetermined operation in synchronization with the clock is disclosed in Patent Document 1, for example. Is disclosed. With the above-described clock supply of the phase shift type clock driver, the peak of the switching current is dispersed and the power supply noise is reduced. Patent Document 1 also mentions a circuit that absorbs the phase shift of each module output when the phase is shifted.

JP 2002-14742 A

  When the phase (skew) is changed for each module, it is necessary to absorb the phase difference somewhere. Otherwise, if the signal transfer between the modules is shorter than the clock phase difference, the circuit will malfunction due to racing (hold error). In order to prevent malfunction due to racing, it is necessary to insert a delay buffer so that the signal transfer between modules must have a delay equal to or greater than the clock skew between the modules. There was a problem that increased.

  In Patent Document 1, the phase absorption macro is provided to absorb the clock phase difference. However, the increase in the circuit due to the provision of the phase absorption macro causes a problem that the area and power increase.

  In addition, since it is necessary to perform signal transfer at a time interval shorter than the actual clock period by the clock phase difference, if the inter-module transfer is a critical path, the operating frequency will be lowered and the performance will deteriorate. There was also a problem.

  Thus, current peak countermeasures by reducing the impedance of bypass capacitors and power supply wiring have a problem of increasing the area and increasing the cost, and the phase shift type clock driver disclosed in Patent Document 1 is fixed for each module. Even when the phase difference is added, there is a problem that the cost is increased due to an increase in circuits and the performance is deteriorated due to a decrease in operating frequency.

  The present invention has been made to solve the above problems, and an object of the present invention is to provide a semiconductor device having a clock supply means that can effectively suppress a current peak at low cost. Another object of the present invention is to provide a semiconductor device having a clock supply means that can effectively suppress malfunction while effectively suppressing current peaks.

  An LSI according to an embodiment of the present invention includes a clock supply unit that supplies a plurality of clocks and a plurality of modules that are arranged on a substrate and operate in synchronization with the plurality of clocks.

  The clock supply means matches the phases of the clocks when data is transferred between modules to be transferred, and provides a phase difference between the clocks when data is not transferred.

  With the above configuration, the LSI according to the embodiment effectively suppresses the current peak at a low cost, and no malfunction occurs during data transfer.

<Basic configuration>
(First LSI)
FIG. 1 is an explanatory diagram showing a basic configuration of a first LSI for realizing an LSI which is a semiconductor device of the present invention.

  As shown in the figure, the first LSI includes a PLL circuit 20 that supplies a clock CLK20, a module A21, a module B22, and a CPU 25. The module A21 receives the clock CLKA obtained by the clock CLK20 via the variable delay circuit 31, and operates in synchronization with the clock CLKA. The module B22 receives the clock CLKB obtained from the clock CLK20 via the variable delay circuit 32, and operates in synchronization with the clock CLKB. The CPU 25 receives the clock CLKP obtained from the clock CLK20 via the variable delay circuit 33, and operates in synchronization with the clock CLKP. The modules such as the module A21 and the module B22 mean all circuits that operate in synchronization with a clock.

  The CPU 25 individually controls the delay times of the variable delay circuits 31 to 33 by control signals SCT1 to SCT3 given to the variable delay circuits 31 to 33. Thus, by controlling the delay time of the variable delay circuits 31 to 33 by the CPU 25, the phase between the clock CLKA, the clock CLKB and the clock CLKP supplied to the module A21, the module B22 and the CPU 25 can be variably controlled. .

  As described above, the clock supply means (PLL circuit 20, CPU 25, variable delay circuits 31 to 33) of the first LSI controls the delay time of each of the variable delay circuits 31 to 33 from the PLL circuit 20. A plurality of clocks (clock CLKA, clock CLKB, and clock CLKP) having different phases can be obtained from a generated reference clock CLK22 with a relatively simple circuit configuration.

(Variable delay circuit)
FIG. 2 is a circuit diagram showing a first example of the internal configuration of the variable delay circuit 31 (32, 33). As shown in the figure, a signal line 56 that receives an input signal IN of the variable delay circuit 31 is connected to one input of n multiplexers MX1 to MXn. Delay buffers DB1 to DBn receive the output signals of multiplexers MX1 to MXn at their input parts, and the outputs of delay buffers DB1 to DB (n-1) are connected to the other inputs of multiplexers MX2 to MXn. The output signal of the delay buffer DBn becomes the output signal OUT of the variable delay circuit 31.

  The multiplexers MX1 to MXn output one signal as an output signal among the signals obtained from one input and the other input according to the control signals CT1 to CTn, respectively. The control signals CT1 to CTn correspond to the control signals SCT1 to SCT3 given to the variable delay circuits 31 to 33 from the CPU 25 in the first LSI shown in FIG.

  The first example of the variable delay circuit 31 having such a configuration is variable by appropriately selecting one stage (delay buffer DBn) to n stage (delay buffers DB1 to DBn) based on the control signals CT1 to CTn. The delay time by the delay circuit 31 can be variably controlled.

  FIG. 3 is a circuit diagram showing a second example of the internal configuration of the variable delay circuit 31 (32, 33). As shown in the figure, n delay buffers BF1 to BFn are connected in series, and the input signal IN of the variable delay circuit 31 is received at the input of the first-stage delay buffer BF1. The outputs of the delay buffers BF1 to BFn are input to the multiplexer 34. The multiplexer 34 receives the control signal CTL, selects an output signal obtained from any one of the delay buffers BF1 to BFn according to the control signal CTL, and outputs the output signal OUT as an output signal OUT. The control signal CTL corresponds to each of the control signals SCT1 to SCT3 given from the CPU 25 to the variable delay circuits 31 to 33 in the first LSI shown in FIG.

  Thus, in the second example of the variable delay circuit 31, the variable delay circuit 31 is appropriately selected from one stage (delay buffer DB1) to n stage (delay buffers DB1 to DBn) based on the control signal CTL. The delay time due to can be variably controlled.

  FIG. 4 is a circuit diagram showing a third example of the internal configuration of the variable delay circuit 31 (32, 33). As shown in the figure, the buffer 35 receives an input signal IN at its input section, its output section is electrically connected to the input section of the buffer 36 via a signal line 57, and the output signal of the buffer 36 is the output signal OUT. It becomes.

  The drains of n N-type selection transistors SQ1 to SQn are electrically connected to a signal line 57 between the buffer 35 and the buffer 36, and the sources of the selection transistors SQ1 to SQn are connected via capacitors CP1 to CPn. In addition to being grounded, the gates receive control signals CT1 to CTn. These control signals CT1 to CTn correspond to the control signals SCT1 to SCT3 applied to the variable delay circuits 31 to 33 from the CPU 25 in the first LSI shown in FIG.

  As described above, the third example of the variable delay circuit 31 is configured to selectively turn on k selection transistors SQ1 to SQn for k (k = 1 to n) based on the control signals CT1 to CTn. By giving the load capacitance due to CP to the signal line 57, the delay time by the variable delay circuit 31 can be variably controlled.

  The first and second examples (FIGS. 2 and 3) of the variable delay circuit 31 have the following advantages over the third example (FIG. 4). In the third example, since the selection transistors SQ1 to SQn are provided corresponding to the capacitors CP1 to CPn, and the load capacitance is adjusted using each single transistor, a cell library that has been often used in recent years is used. The design method cannot be used. For this reason, as in the case of analog circuits, circuit verification is very time-consuming and requires special techniques such as special library form when incorporated into an LSI.

  On the other hand, in the first and second examples, a plurality of delay elements (delay buffers DB1 to DBn, delay buffers BF1 to BFn) that can be variably controlled in the number of delay stages are used. Since it can be configured, a design method using a cell library can be applied, and the design can be easily performed.

(System configuration example)
FIG. 5 is a block diagram showing a first system configuration example including the connection status of the first LSI shown in FIG. 1 on the bus. As shown in the figure, the module A 21, the CPU 25 and the phase control register 24 are connected to the bus 40 so as to be able to send and receive signals, and the module B 22 is not connected to the bus 40. Note that the data transfer between the module A21 and the module B22 is directly performed without going through the bus 40.

  The phase control register 24 stores control information for determining the phases of the clock CLKA, the clock CLKB, and the clock CLKP of the module A21, the module B22, and the CPU 25. The CPU 25 outputs a control signal SCT (SCT1 to SCT3) to be given to the variable delay circuits 31 to 33 shown in FIG. 1 based on control information obtained by accessing the phase control register 24 via the bus 40. The phase control register 24 itself stores control information for determining the phase difference of the clock CLK24 that is given to the phase control register 24, and the CPU 25 controls the delay time of a variable delay circuit (not shown) for the clock CLK24. Configuration is also conceivable.

  FIG. 6 is a block diagram showing a second system configuration example including the connection status of the first LSI shown in FIG. 1 on the bus. As shown in the figure, the module A 21 and the CPU 25 are connected to the bus 40 so as to be able to send and receive signals, and the module B 22 is not connected to the bus 40. A phase control register 26 is provided in the CPU 25. Note that the data transfer between the module A21 and the module B22 is directly performed without going through the bus 40.

  The phase control register 26 stores control information for determining the clock CLKA, the clock CLKB, and the clock CLKP of the module A21, the module B22, and the CPU 25. Based on the control information obtained from the internal phase control register 26, the CPU 25 outputs a control signal SCT to be provided to the variable delay circuits 31 to 33 shown in FIG.

(Phase control register)
FIG. 7 is an explanatory diagram showing a memory map viewed from the CPU 25 of the phase control register 24 (26). As shown in the figure, addresses 0000 — 1000 to address 0000 — 1FFC are assigned as addresses of the phase control register 24, addresses 0000 — 1000 (-1003) are assigned for the module A21, and addresses 0000 — 1004 (˜1007) are assigned for the module B22. Address 0000_1100 (˜1103) is assigned for the CPU 25. Since 8 bits of information can be stored per address, 32 bits of information for 4 addresses are mapped so as to be stored as control information for the modules A21, B22 and CPU25.

  FIG. 8 is an explanatory diagram showing an example of the internal configuration of the phase control register 24 (26). As shown in the figure, the phase control register 24 can store control information of 32 bits (b0 to b31), and in the example shown in the figure, bits b16 to b31 are stored as control information bits.

  FIG. 9 is an explanatory diagram showing the relationship between the contents stored in the phase control register 24 shown in FIG. 8 and the control information in a table format. As shown in the figure, bits b16 to b31 are recognized as control information. Depending on the place where “1” is set in bits b16 to b31, there is a delay from “no delay” to a delay of 15 delay lines. Time is determined. In the example of FIG. 8, bits b16 to b31 are “1100_0000_0000_0000”, and it can be recognized from FIG. 9 that “no delay” is the control information.

  As described above, the CPU 25 recognizes the control information in the phase control register 24 (26), and gives the control signals SCT1 to SCT3 to the variable delay circuits 31 to 33, whereby the delay times of the variable delay circuits 31 to 33 are variable. Can be controlled.

  In the control information shown in FIG. 9, the maximum two places among the bits b16 to b31 are “1” in order to indicate the number of stages of the delay line (delay buffer DB) as the specification of the variable delay circuit 31 shown in FIG. It is a specification to make. However, even if this specification is not used, for example, when 16 delay times are set, a specification in which 0 to 15 is specified by a 4-bit register and the control signal SCT is generated by the CPU 25 can be considered.

  Further, since the variable delay circuit 31 having the configuration shown in FIGS. 3 and 4 has optimum bit assignments different from each other, the specifications may be adapted to each. In order to make it easy for the user to use, for example, in the case of 16 stages, it may be a specification that specifies 0 to 15 with a 4-bit register. In the example of FIG. 9, the delay time of 16 steps can be adjusted, but the number of adjustment steps may be more or less than 16. What is necessary is just to give the optimal adjustment width to LSI to mount.

  Therefore, for the first LSI described above, the user describes the write contents (control information) in the phase control register 24 (26) in the program, and each module is optimally suited to the usage status at that time. By setting the phase difference, it is possible to reduce power supply noise and EMI.

  The following effects can be expected from the first LSI. By providing phase differences in a plurality of clocks, local voltage drop is mitigated by reducing power source peak noise. As a result, the margin for the voltage drop expected at the time of circuit design is reduced, so that the circuit scale / gate size can be reduced accordingly, and the cost and power consumption can be reduced.

  By reducing the EMI, the risk of malfunction in the system is reduced, and the cost for EMI countermeasures can be reduced.

(Second LSI)
FIG. 10 is an explanatory diagram showing a configuration example of the second LSI for realizing the LSI of the present invention.

  As shown in the figure, the second LSI includes a PLL circuit 27 that supplies a clock CLK, a module A21, a module B22, and a CPU. The module A21 receives the clock CLKA obtained via the selection circuit 41 and operates in synchronization with the clock CLKA. The module B22 receives the clock CLKB obtained via the selection circuit 42, and performs a predetermined operation in synchronization with the clock CLKB. The CPU 28 receives the clock CLKP obtained via the selection circuit 43 and operates in synchronization with the clock CLKP.

  FIG. 11 is a timing chart showing waveforms of clocks CLK21 and CLK22 generated by the PLL circuit 27. As shown in the figure, there is a phase difference ΔT between the clock CLK21 and the clock CLK22.

  FIG. 12 is an explanatory diagram showing the configuration of the oscillator unit 29 in the first configuration example of the PLL circuit 27. Note that the entire configuration of the PLL circuit 27 is a configuration of a normal PLL circuit.

  As shown in the figure, the oscillator unit 29 is configured by a loop connection of five stages of inverters, and the output of the fourth stage inverter is set to the clock CLK21, and the output of the final stage is set to the clock CLK22. Is provided with a phase difference corresponding to one stage of the inverter. The frequency control input fin is a voltage signal for controlling the oscillation frequency of the oscillator unit 29.

  FIG. 13 is a block diagram showing a second configuration example of the PLL circuit 27. As shown in the figure, the dividing cycle 27b receives the reference clock CLK20 from the PLL circuit 27 and divides the clock CLK20 from the PLL circuit 27 to obtain the clock CLK21.

  The D flip-flop 27c receives the clock CLK21 at the D input and the clock CLK20 at the CLK input. A signal obtained from the Q output of the D flip-flop 27c is output as the clock CLK22.

  In such a configuration, when the clock CLK21 is generated in synchronization with the rising edge of the clock CLK20, and the D input is latched in the D flip-flop 27c in synchronization with the rising edge of the clock CLK20, between the clocks CLK21 and CLK22, A phase difference based on the processing time of the minute period 27b and the processing time of the D flip-flop 27c can be provided.

  Returning to FIG. 10, as described above, the PLL circuit 27 generates two types of clocks CLK <b> 21 and CLK <b> 22 having different phases and applies them to the selection circuits 41 to 43, respectively. The CPU 28 gives control signals SCT11 to SCT13 to the selection circuits 41 to 43, and the selection circuits 41 to 43 output one of the clocks CLK21 and CLK22 as the clock CLKA, the clock CLKB, and the clock CLKP based on the control signals SCT11 to SCT13. .

  As described above, the CPU 28 individually controls the selection contents of the selection circuits 41 to 43 by the control signals SCT11 to SCT13, thereby the clock CLKA, the clock CLKB, and the clock CLKP supplied to the module A21, the module B22, and the CPU 28. Can be variably controlled.

  In the second LSI shown in FIG. 10, an example is shown in which one of the two types of clocks CLK21 and CLK22 is selected. However, the second LSI can be extended to a configuration in which three clocks or clocks with different phases are selected. Of course it is also possible.

  Further, the contents of the control signals SCT11 to SCT13 can be determined based on the control information stored in the phase control register 24 as in the first LSI.

  In the second LSI having such a configuration, similarly to the first LSI, the user assigns an optimum phase difference according to the use state at the time for each module from the program, thereby reducing power supply noise and EMI. Reduction can be performed.

  As described above, in the second LSI, the local voltage drop is reduced by reducing the power supply peak noise. As a result, the margin for the voltage drop expected at the time of circuit design is reduced, so that the circuit scale / gate size can be reduced accordingly, and the effects of cost reduction and power consumption reduction can be achieved.

  In addition, by reducing EMI, the risk of malfunction in the system is reduced, and it is possible to reduce the cost for EMI countermeasures.

(Third LSI)
FIG. 14 is an explanatory diagram showing the basic configuration of a third LSI for realizing the LSI of the present invention.

  As shown in the figure, the LSI includes a PLL circuit 20 that supplies a clock CLK20, a module A21, a module B22, a CPU 30, and a clock control circuit 37. The module A21 receives the clock CLKA obtained by the clock CLK20 via the variable delay circuit 31, and operates in synchronization with the clock CLKA. The module B22 operates in synchronization with the clock CLKB when the clock CLK20 is received through the variable delay circuit 32 and the clock CLKB is obtained. The CPU 30 receives the clock CLKP obtained from the clock CLK20 via the variable delay circuit 33, and operates in synchronization with the clock CLKP. The clock control circuit 37 is provided separately from the CPU 30 and operates in synchronization with the clock CLKX obtained by the clock CLK20 via the delay circuit 38.

  The clock control circuit 37 individually controls the delay times of the variable delay circuits 31 to 33 by outputting control signals SCT21 to SCT23 given to the variable delay circuits 31 to 33, respectively. Thus, by controlling the delay time of the variable delay circuits 31 to 33 by the clock control circuit 37 provided independently of the CPU 30, the clock CLKA and the clock CLKB supplied to the module A21, the module B22 and the CPU 30 are controlled. And the phase between the clocks CLKP can be variably controlled.

  The activation / inactivation of the clock control circuit 37 can be controlled from the CPU 30. It is also conceivable that the user can control the clock control circuit 37 from the program by forcibly controlling the clock control circuit 37 from the CPU 30 like the first and second LSIs.

  It is also conceivable that the delay circuit 38 that generates the clock CLKX supplied to the clock control circuit 37 is variably configured, and the clock control circuit 37 itself performs the variable control. In addition, a method in which another circuit such as the CPU 30 controls the delay circuit 38 to change the phase of the clock CLKX is also conceivable. It is also conceivable to configure the clock control circuit 37 so that the phase of the clock CLKX cannot be controlled.

  In the third LSI having such a configuration, the clock control circuit 37 can reduce the power supply noise and the EMI by giving each module an optimum phase difference according to the use state at that time. .

  As described above, the third LSI, like the first and second LSIs, reduces the margin of the voltage drop expected during circuit design by reducing the local voltage drop by reducing the power supply peak noise. Therefore, the circuit scale / gate size can be reduced correspondingly, and there is an effect that cost and power consumption can be reduced.

  Furthermore, the risk of malfunction in the system is reduced by reducing the EMI, and it is possible to reduce the cost for EMI countermeasures.

<Embodiment 1>
In the first to third LSIs described above, clock supply means for supplying a plurality of clocks having different phases (in the first LSI shown in FIG. 1, the PLL circuit 20, the CPU 25, and the variable delay circuits 31 to 33 correspond, 10 is equivalent to the PLL circuit 27, the CPU 28, and the selection circuits 41 to 43, and the third LSI shown in FIG. 14 is equivalent to the PLL circuit 20, the clock control circuit 37, and the variable delay circuits 31 to 33). The circuit configuration was described.

  Since the clock supply means of the first to third LSIs supply a plurality of clocks so that their phases are different from each other, the clock supply means basically has an effect of effectively suppressing a current peak at a low cost. Yes.

  However, since the clock phase of each module is changed by the clock supply means, signal transfer between modules is performed at intervals shorter than the clock phase difference in data transfer between modules supplied with clocks of different phases. Otherwise, the circuit may malfunction due to racing (hold error). Therefore, the clock skew adjusting method in the clock supply means of the LSI according to the first embodiment is designed to prevent malfunction.

  FIG. 15 is an explanatory diagram conceptually showing the physical layout of the LSI according to the first embodiment. As shown in the figure, a module A11, a module B12, a module C13, and a CPU 1 are arranged on a substrate 58 so as to be able to exchange signals with the bus 16. The module A11, the module B12, the module C13, and the CPU 1 operate in synchronization with the clock CLKA, the clock CLKB, the clock CLKC, and the clock CLKP. These clocks CLKA, CLKB, CLKC, and CLKP are the first to third LSIs described above. Thus, the phase is variably controlled.

  As shown in the figure, in the layout configuration on the substrate 58, the module A11 and the module B12 (first module pair) are physically close in distance (d12 (first distance)). The module C13 and the module A11 (second module pair) are arranged so that the distance (d13 (first distance)> d12) is relatively far in the layout configuration. Therefore, the delay time (t12) when transferring data from the module A11 to the module B12 is longer than the delay time (t13> t12) when transferring data from the module A11 to the module C13. If the delay time is short, the risk of malfunction due to the above-mentioned racing increases, so that module B12 has a high risk of malfunction due to phase control, and module C13 has a low risk of malfunction.

  Considering the above-described malfunction due to the length of the distance between the modules, the clock phase difference between the module A11 and the module B12 that are physically close to each other in the layout configuration is set to “0” or a relatively small phase difference (Δ12). The clock skew adjustment method by the clock supply means in the LSI according to the first embodiment controls the clock phase difference so that the clock phase difference (Δ13> Δ12) with C13 is relatively large.

  Also, in general, there is a strong tendency to place modules that are closely related to each other physically close, so the number of (signal) wires between modules that are relatively close to each other is larger than between modules that are relatively far away. There are many. Therefore, in the case of the LSI layout configuration of the first embodiment, the number of wires between the module A11 and the module B12 tends to be larger than the number of wires between the module A11 and the module C13.

  When the clock phase difference between modules is set to be longer than the data transfer time, it is necessary to insert a buffer or the like on the data transfer path between modules in order to delay the data transfer time.

  However, in the clock skew adjustment method of the first embodiment, the number of insertion buffers for data transfer time delay is minimized by setting the clock phase difference between the physically close modules A11 and B12 to be small in advance. be able to. Therefore, a large number of wires between the module A11 and the module B12 does not cause a large increase in the number of insertion buffers.

(effect)
Since the clock supply means in the LSI of the first embodiment supplies a plurality of clocks so that their phases are different from each other, current peaks can be effectively suppressed at low cost.

  Furthermore, the clock supply means of the first exemplary embodiment is such that the clock phase difference between the first module pair arranged on the substrate 58 at a relatively short first distance is longer than the first distance. A plurality of clocks are supplied so as to be smaller than the phase difference of the clock signals between the second module pairs arranged at a distance of two. In FIG. 15, module A11 and module B12 correspond to the first module pair, module A11 and module C13 correspond to the second module pair, and clock CLKA, clock CLKB, and clock CLKC are the plurality of clocks. Equivalent to.

  As described above, the clock supply means in the LSI of the first embodiment increases the clock phase difference between the module pairs as the inter-module distance having a positive correlation in the signal transfer time between the modules increases. There is an effect that it is possible to effectively suppress malfunctions that may occur when the signal transfer time between them is performed at intervals shorter than the clock phase difference.

  In addition, in the clock skew adjustment method of the first embodiment, the number of insertion buffers for setting the delay time can be reduced by controlling the clock phase difference in consideration of the physical position between modules. With the addition of a small number of gates, the current peak and EMI can be reduced.

  Therefore, the local voltage drop is mitigated by the power supply peak noise reduction. As a result, the margin for the voltage drop expected at the time of circuit design is reduced, so that the circuit scale / gate size can be reduced accordingly, and the cost and power consumption can be reduced.

  In addition, by reducing EMI, the risk of malfunction in the system is reduced, and the cost for EMI countermeasures can be reduced.

<Embodiment 2>
FIG. 16 is a flowchart showing a clock skew adjustment method by the LSI clock supply means according to the second embodiment of the present invention. The flow shown in FIG. 16 is executed, for example, in the system configuration shown in FIG. 5 or 6 in the first LSI described above.

  Referring to FIG. 16, after the clock phases of module A21 and module B22 are matched in step ST1, data is transferred from module A21 to module B22 in step ST2.

  Thus, at the time of data transfer in step ST2, since the phases of the clock CLKA and the clock CLKB for the module A21 and the module B22 coincide with each other, the data transfer between the module A21 and the module B22 can be performed without malfunction. As a method of recognizing the end timing of the data transfer between the module A21 and the module B22, (1) grasping on the CPU 25 side, (2) grasping on the transfer source or transfer destination module (module A21 or module B22), 3) It may be possible to grasp with another circuit such as a bus arbitration circuit or DMA controller. In the case of (1), the CPU 25 recognizes the end report from the module and the end report from the bus arbitration circuit or the DMA controller.

  Thereafter, in step ST3, the clock phase difference between the clock CLKA of the module A21 and the clock CLKB of the module B22 is set to a predetermined magnitude, and then in step ST4, the module A21 and the module B22 are each independently subjected to predetermined arithmetic processing. I do.

  As described above, when step ST4 is executed, a predetermined phase difference is set between the clock CLKA and the clock CLKB for the module A21 and the module B22. Therefore, a current peak generated when the module B12 and the module B22 are fully operated. Noise and EMI noise can be reduced. In step ST4, the module A21 and the module B22 do not communicate with other modules, the outside of the CPU, etc., so that there is no problem of malfunction even if there is a clock phase difference between the clock CLKA and the clock CLKB.

  In step ST5, the phases of the clock CLKA of the module A21 and the clock CLKP of the CPU 25 are matched, and then the calculation result of the module A21 is read by the CPU 25 in step ST6.

  Thus, at the time of data transfer in step ST6, the phases of the clock CLKA and the clock CLKP for the module A21 and the CPU 25 are the same, so that the data transfer between the module A21 and the CPU 25 can be performed without malfunction.

(effect)
The clock supply means in the LSI according to the second embodiment supplies a plurality of clocks in principle so that their phases are different from each other when data transfer is not performed, so that the current peak can be effectively suppressed at low cost.

  Further, the clock skew adjustment method performed by the clock supply means of the LSI according to the first embodiment is to make the clock phases coincide with each other when transferring data between modules, and to provide a predetermined phase difference between the clocks when not transferring data. In addition, data transfer between modules can be performed without malfunction while suppressing current peaks.

  Thus, in the clock skew adjustment method of the second embodiment, the current peak and EMI can be reduced more effectively by dynamically controlling the clock phase according to the program contents.

  And local voltage drop is relieved by power supply peak noise reduction. As a result, the margin for the voltage drop expected at the time of circuit design is reduced, so that the circuit scale / gate size can be reduced accordingly, and the effects of cost reduction and power consumption reduction can be achieved.

  Furthermore, the risk of malfunction in the system is reduced by reducing the EMI, and it is possible to reduce the cost for EMI countermeasures.

<Embodiment 3>
FIG. 17 is an explanatory diagram showing a layout configuration centered on a bus in the LSI according to the third embodiment. As shown in the figure, a module A11, a module B12, a module C13, and the CPU 1 are connected to the bus 16 so as to be able to exchange signals. The module A11, the module B12, the module C13, and the CPU 1 operate in synchronization with the clock CLKA, the clock CLKB, the clock CLKC, and the clock CLKP. These clocks CLKA, CLKB, CLKC, and CLKP are the first to third LSIs described above. Thus, the phase is variably controlled.

  As shown in FIG. 17, when the modules 11 to 13 are commonly connected to the bus 16, power consumption increases because the load on the bus 16 is large. Therefore, as much as possible, it is desirable to make the phase of the clock of each of the modules 11 to 13 different from the phase of the clock of the bus 16.

  Therefore, the clock skew adjusting method executed by the clock supply means of the third embodiment is such that when the modules 11 to 13 access the bus 16 respectively, the phase is matched with the bus clock, and when the bus access is completed, the bus clock is adjusted again. And a phase difference. The bus clock means a clock required for each of the modules 11 to 13 and the CPU 1 at the time of bus access, and may be hereinafter referred to as “bus clock CKBS”.

  FIG. 18 is a flowchart showing a clock skew adjustment method in the LSI clock supply means according to the third embodiment of the present invention. Hereinafter, the processing procedure of the third embodiment will be described with reference to FIG. Note that, as an initial state, the clock CLKA, the clock CLKB, the clock CLKC, and the clock CLKP are set to phases different from each other.

  First, in step ST11, the phases of the clock clock CLKA and the clock CLKB of the module A11 and the module B12 are matched with the bus clock CKBS, and then in step ST12, data transfer is performed from the module A11 to the module B12 via the bus 16.

  As described above, at the time of data transfer in step ST12, the phases of the clock CLKA and the clock CLKB for the module A11 and the module B12 coincide with the bus clock CKBS, so that the malfunction does not occur via the bus 16 between the module A11 and the module B12. Data transfer can be performed.

  Thereafter, in step ST13, the clock CLKA and the clock CLKB are returned to the initial state, and a phase difference is set between the clock CLKA and the clock CLKB and the bus clock CKBS. Thereafter, in step ST14, the module A11, the module B12, and the CPU 1 perform independent arithmetic processing that does not use the bus 16.

  Thus, when step ST14 is executed, a predetermined phase difference is set between the clocks CLKA and CLKB for the modules A11 and B12 and the bus clock CKBS, so that the modules B12 and B12 are fully loaded. Current peak noise and EMI noise on the bus 16 generated by the operation can be reduced. In step ST14, the module A11 and the module B12 do not perform the data transfer operation via the bus 16, so that there is no problem of malfunction even if there is a clock phase difference between the clock CLKA and the clock CLKB and the bus clock CKBS. .

  In step ST15, the phases of the clock CLKA and the clock CLKP of the module A11 and the CPU 1 are matched with the bus clock CKBS, and then the calculation result of the module A11 is transferred to the CPU 1 via the bus 16 in step ST16.

  Thus, at the time of data transfer in step ST16, since the phases of the clock CLKA and the clock CLKP for the module A11 and the CPU1 coincide with the bus clock CKBS, data transfer between the module A11 and the CPU1 can be performed without malfunction. Although not shown in FIG. 18, after the execution of step ST16, the clock CLKA and the clock CLKP are returned to the initial state, and a predetermined clock phase difference is set between them.

(effect)
The clock supply means in the LSI according to the third embodiment supplies a plurality of clocks so that their phases are different from each other except at the time of data transfer via the bus, so that the current peak can be effectively suppressed at low cost. it can.

  Furthermore, the clock supply means in the LSI of the third embodiment adjusts the clock of the module to be transferred to the phase of the basque clock at the time of data transfer, and provides a predetermined phase difference in the clock between modules when data is not transferred. Thus, data transfer between modules via the bus can be performed without malfunction while suppressing current peaks on the bus.

  Thus, in the clock skew adjustment method of the third embodiment, the current peak and EMI can be reduced more effectively by dynamically controlling the clock phase according to the program contents.

  And local voltage drop is relieved by power supply peak noise reduction. As a result, the margin for the voltage drop expected at the time of circuit design is reduced, so that the circuit scale / gate size can be reduced accordingly, and the effects of cost reduction and power consumption reduction can be achieved.

  Furthermore, the risk of malfunction in the system is reduced by reducing the EMI, and it is possible to reduce the cost for EMI countermeasures.

<Embodiment 4>
FIG. 19 is an explanatory diagram showing a layout configuration centered on an LSI bus in the LSI of the fourth embodiment. As shown in the figure, the CPUs 1 to 3 and the secondary cache 6 are connected to a bus 59 so as to be able to exchange signals. The CPUs 1 to 3 operate in synchronization with the clocks CLKP1 to CLKP3, and the secondary cache 6 operates in synchronization with the clock CLK6. The phases of the clocks CLKP1 to CLKP3 and the clock CLK6 are variably controlled by exhibiting a circuit configuration like the first to third LSIs described above.

  As shown in FIG. 19, the LSI according to the fourth embodiment that constitutes a multiprocessor system including three CPUs 1 to 3 includes a cache (primary cache (not shown)) in each of the LSIs, and CPUs 1 to 3. The secondary cache 6 connected to the bus 59 shared between them also has a configuration that can be used as a cache.

  As described above, when the CPUs 1 to 3 are connected to the bus 59 in common, it is possible to reduce current peak noise and EMI noise on the bus 59 by providing a phase difference between the clocks CLKP1 to CLKP3 in the CPUs 1 to 3. .

  However, when the CPUs 1 to 3 miss the access to the internal primary cache and access the secondary cache 6, the clock CLK6 of the secondary cache 6 and the clock of the CPU accessing the secondary cache 6 It is desirable to match the phases.

  FIG. 20 is a flowchart showing a clock skew adjustment method in the LSI clock supply means according to the fourth embodiment of the present invention. The processing procedure of the clock skew adjustment method according to the fourth embodiment will be described below with reference to FIG.

  First, in step ST21, the clocks CLKP1 to CLKP3 of the CPUs 1 to 3 are initialized so that a predetermined phase difference is provided between them. At this time, it is desirable that the clocks CLKP1 to CLKP3 are also provided with a phase difference from the clock CLK6 of the secondary cache 6.

  If the CPU 1 causes a cache miss in the internal primary cache at step ST22, the phase of the clock CLKP1 of the CPU 1 is changed to match the phase of the clock CLK6 of the secondary cache 6 at step ST23, and then at step ST24. The CPU 1 accesses the secondary cache 6 via the bus 59.

  In this way, when accessing the secondary cache 6 in step ST24, the phase of the clock CLKP1 of the CPU 1 and the phase of the clock CLK6 of the secondary cache 6 match, so the CPU 1 accesses the secondary cache 6 without malfunction. can do.

  Thereafter, in step S25, the clock CLKP1 of the CPU 1 is returned to the initial phase set in step ST1.

  As described above, since the clock CLKP1 of the CPU 1 is returned to the initial state when the step ST25 is executed, the current peak noise and the EMI noise on the bus 59 caused by the full operation of the CPUs 1 to 3 can be reduced. Further, during the execution of step ST25, the CPUs 1 to 32 do not access the secondary cache 6 via the bus 59, so that the problem of malfunction does not occur.

  In the example shown in FIG. 20, the phase of the clock CLKP1 of the CPU 1 is changed to match the phase of the clock CLK6. However, the phase of the clock CLK6 of the secondary cache 6 is changed to match the phase of the clock CLKP1. You may let them. In this case, the process of step ST23 in FIG. 20 is “the phase of the clock CLK6 of the secondary cache 6 is changed to match the phase of the clock CLKP1 of the CPU 1”, and the process of step S25 is “the clock CLK6 of the secondary cache 6”. To the original phase ”.

  In this specification, a CPU having a specific function is represented by a unique name, and a general logic circuit other than the CPU is represented by a module A, a module B, or the like for convenience. However, since the CPU and the like share the module A and the like in that they operate in synchronization with the clock, they are included in the module in a broad sense. Therefore, the CPUs 1 to 3 and the secondary cache 6 in the fourth embodiment are also included in the module in a broad sense.

(effect)
The clock supply means in the LSI of the fourth embodiment supplies a plurality of clocks so that their phases are different from each other except when accessing the secondary cache 6, thereby effectively suppressing current peaks at low cost. Can do.

  Further, the clock supply means in the LSI of the fourth embodiment is configured such that the clock (any one of the clocks CLKP1 to CLKP3) of the CPU (any one of the CPUs 1 to 3) and the secondary desired to be accessed only when the secondary cache 6 is accessed. Since the phase of the clock CLK6 of the cache 6 is matched, a plurality of CPUs can access the secondary cache without malfunction while suppressing current peaks.

  As described above, in the clock skew adjustment method by the clock supply unit according to the fourth embodiment, the clock phase is dynamically controlled before and after the access to the secondary cache 6 connected to the shared bus, so that the current can be more effectively generated. Peaks and EMI can be reduced.

  And local voltage drop is relieved by power supply peak noise reduction. As a result, the margin for the voltage drop expected at the time of circuit design is reduced, so that the circuit scale / gate size can be reduced accordingly, and the effects of cost reduction and power consumption reduction can be achieved.

  Furthermore, the risk of malfunction in the system is reduced by reducing the EMI, and it is possible to reduce the cost for EMI countermeasures.

<Embodiment 5>
FIG. 21 is an explanatory diagram showing a layout configuration centered on a bus in the LSI of the fifth embodiment. As shown in the figure, the module A11, the module B12, the module C13, and the CPU 1 are connected to the clock reference bus 17 so as to be able to exchange signals. The module A11, the module B12, the module C13, and the CPU 1 operate in synchronization with the clock CLKA, the clock CLKB, the clock CLKC, and the clock CLKP. These clocks CLKA, CLKB, CLKC, and CLKP are the first to third LSIs described above. Thus, the phase is variably controlled.

  In the clock skew adjustment method of the fifth embodiment, the phase control of these clocks CLKA, CLKB, CLKC and CLKP is performed with reference to the bus clock CKBS of the clock reference bus 17 in the configuration shown in FIG.

  In other words, the bus clock CKBS is fixed as a reference, and the other clocks are determined to have a phase of x degrees (or xns) relative to the reference bus clock CKBS.

  In the configuration shown in FIG. 21, among the modules (11 to 13, 1), it is highly desirable to set a high-speed operation to have a small phase difference from the bus clock CKBS that is the reference clock.

  For example, when the module A11 is operating at a higher speed than the modules B12 and C13, the data transfer through the clock reference bus 17 is frequently performed, and high-speed data transfer can occur. A smaller phase difference from CKBS is desirable. This is because if the clock phase difference between the clock CLKA and the bus clock CKBS is large, the time required for data transfer is shortened by the phase difference and a malfunction due to a setup error is likely to occur.

  Further, when the clock CLKB of the module B12 is also high speed, the phase difference between the clock CLKA and the clock CLKB is also reduced because the phase difference from the bus clock CKBS is set to be small as in the case of the clock CLKA of the module A11. . Therefore, no malfunction occurs during the transfer between the module A11 and the module B12. Further, when the module C13 operates at a low speed, the phase difference between the clock CLKB and the bus clock CKBS increases. However, since the operation is originally performed at a low speed, the phase difference from the bus clock CKBS or the clock of another high-speed operation module increases. However, it will not be a problem.

  As described above, in the clock skew adjustment method by the clock supply unit of the fifth embodiment, the clock phase is dynamically controlled based on the operation speed of the module with the bus clock CKBS of the clock reference bus 17 as a reference, so that it is more effective. In addition, current peaks and EMI can be reduced.

  Here, the operation speed of the module can be considered as a clock frequency. In that case, the phase difference may be calculated as a function of the clock frequency.

(effect)
Since the clock supply means in the LSI of the fifth embodiment supplies a plurality of clocks so that their phases are different from each other, current peaks can be effectively suppressed at low cost.

  Further, the clock supply means in the LSI of the fifth embodiment changes the phase of the plurality of clocks to the phase of the bus clock CKBS that is the reference clock as the operation state becomes higher-speed operation based on the operation state of each of the plurality of modules. A plurality of clocks are supplied so as to approach each other. For this reason, it is possible to set the phase difference relatively close to each other by bringing the phase of the clock between the modules in the high-speed operation state where the possibility of malfunction is relatively high close to the phase of the reference clock.

  As a result, it is possible to effectively suppress malfunction during data transfer between modules in a high-speed operation state while suppressing a current peak on the clock reference bus 17.

  As described above, in the clock skew adjusting method of the clock supply means of the fifth embodiment, the bus clock CKBS of the clock reference bus 17 is used as a reference, and the phase difference between the clock clock CKBS and the bus clock CKBS is reduced depending on the module operating speed. By performing dynamic clock phase control that determines the magnitude, current peaks and EMI can be reduced more effectively without causing malfunction.

  And local voltage drop is relieved by power supply peak noise reduction. As a result, the margin for the voltage drop expected at the time of circuit design is reduced, so that the circuit scale / gate size can be reduced accordingly, and the effects of cost reduction and power consumption reduction can be achieved.

  Furthermore, the risk of malfunction in the system is reduced by reducing the EMI, and it is possible to reduce the cost for EMI countermeasures.

<Embodiment 6>
This embodiment shows a phase matching method in the case where the clock phase is dynamically controlled as in the clock supply means clock skew adjustment method shown in the second to fifth embodiments.

  When dynamically controlling the clock phase, the phases of the two clocks will be moved closer or away from each other. However, when considering which clock phase should be changed, the phases should be matched. Of the two required modules, it is desirable to change the direction of low-speed operation without changing the phase for high-speed operation. This is because the clock pulse expands and contracts slightly when the phase is changed. This is because the clock contraction affects the critical path setup that determines the upper limit of the operating frequency. The above-mentioned modules mean a broad concept including the CPUs 1 to 3 and the secondary cache 6 shown in FIG. 19 as well as the modules A11, B12 and C13.

  Whether the operation of each module is high speed or low speed can be recognized by, for example, a clock frequency. That is, it can be considered that a module having a higher clock frequency operates at a high speed.

  FIG. 22 is a flowchart showing a clock phase matching method which is a part of the clock skew adjustment method by the LSI clock supply means according to the sixth embodiment of the present invention. Note that the flow shown in FIG. 22 is the flow from module A11 to module B12 when a predetermined phase difference is provided in the phase between module A11 and module B12 in the system configuration of the second embodiment shown in FIG. The flow in the situation where the need for data transfer occurs is shown.

  Referring to FIG. 22, when it is necessary to transfer data from module A11 to module B12 in step ST31, in step ST32, clock frequency f (A) of clock CLKA of module A11 and clock CLKB of module B12 are clocked. The frequency f (B) is to be compared.

  In step ST33, the clock frequency f (A) is compared with the clock frequency f (B). If “f (A)> f (B)”, the process proceeds to steps ST34 to ST36. When (A) <f (B) ”, the process proceeds to steps ST37 to ST39. If “f (A) = f (B)”, either process may be performed.

  In step ST34 executed when “f (A)> f (B)” in step ST33, the phase of the clock CLKB of the module B12 is changed to match the phase of the clock CLKA of the module A11.

  Thereafter, in step ST35, data is transferred from the module A11 to the module B12, and in step ST36, the phase of the clock CLKB of the module B12 is changed to return to the original state, and the process is ended.

  On the other hand, in step ST37, which is executed when “f (A) <f (B)” in step ST33, the phase of the clock CLKA of the module A11 is changed to match the phase of the clock CLKB of the module B12.

  Thereafter, in step ST38, data is transferred from the module A11 to the module B12. In step ST39, the phase of the clock CLKA of the module A11 is changed to return to the original state, and the process is terminated.

  In the flow shown in FIG. 22, the high / low speed of the module operation is determined by comparing the clock frequencies. However, when the module functions are different, it may not be measured simply by the clock frequency. In that case, consider the frequency margin at the time of design, determine the data processing amount per unit time (throughput), determine the calculation amount per unit time, or compare the clock frequency It is possible to compare various parameters.

(effect)
As described above, in the clock skew adjustment method using the LSI clock supply means of the sixth embodiment, when the clock phase is dynamically controlled by the program, the phase of the module operating at a relatively high speed is not changed, and the relative By changing the clock phase of modules that operate at a low speed, the clock phases of the modules that are subject to phase matching are matched.

  As a result, the current peak and EMI can be reduced more effectively by dynamically controlling the clock phase by the program while eliminating the possibility of malfunction due to the clock phase change of the module operating at higher speed. .

  And local voltage drop is relieved by power supply peak noise reduction. As a result, the margin for the voltage drop expected at the time of circuit design is reduced, so that the circuit scale / gate size can be reduced accordingly, and the effects of cost reduction and power consumption reduction can be achieved.

  Furthermore, the risk of malfunction in the system is reduced by reducing the EMI, and it is possible to reduce the cost for EMI countermeasures.

<Embodiment 7>
In recent large-scale LSIs, a test facilitating circuit called a scan test circuit is incorporated. In the scan test, all state elements such as flip-flops are controlled by the same clock. The scan data is transferred directly without a logic circuit between the flip-flops. In this case, if the clock phase is shifted, a hold error due to clock and data racing occurs, resulting in malfunction.

  In the scan test, since flip-flops are connected regardless of the module boundary in some cases, it is difficult to control the phase of each module, and it is highly likely that it does not make sense.

  FIG. 23 is an explanatory diagram showing the structure of the LSI according to the seventh embodiment of the present invention. As shown in the figure, in addition to the configuration of the third LSI shown in FIG. 14, a delay content selection circuit 18 which is a clock phase setting circuit is further provided.

  The delay content selection circuit 18 includes AND gates G1 to G3, and the AND gates G1 to G3 commonly receive the scan enable inversion signal bar SCAN at their one inputs. The AND gate G1 receives a control signal SC21 for controlling the variable delay circuit 31 from the clock control circuit 39 at the other input, and the AND gate G2 receives a control signal SC22 for controlling the variable delay circuit 32 from the clock control circuit 39 at the other input. The AND gate G3 receives the control signal SC23 for controlling the variable delay circuit 33 from the clock control circuit 39 at the other input. The output signals of the AND gates G1 to G3 are given as control signals for the variable delay circuits 31 to 33. Other configurations are the same as those of the third LSI shown in FIG.

  In such a configuration, during normal operation (except during the scan test), the scan enable inversion signal bar SCAN is “H”, so that the LSI of the seventh embodiment performs an operation equivalent to the third LSI.

  On the other hand, since the scan enable inversion signal SCAN becomes “L” during the scan test, the outputs of the AND gates G1 to G3 are forcibly set to the same fixed value (“0”). It is possible to forcibly set the delay times of 33 to the same (minimum delay time “0”).

  As described above, in the LSI according to the seventh embodiment, the delay content selection circuit 18 forcibly matches the phases of the clock CLKA, the clock CLKB, and the clock CLKP of all the modules (including the CPU 30) during the scan test. Thus, it is possible to provide an operating environment suitable for the scan test operation, in particular, the data transfer of the scan data to the scan FF.

  In the configuration shown in FIG. 23, the clock control circuit 39 is provided with the control function of the clock supply means. However, like the first LSI shown in FIG. Of course, the same configuration can be realized by providing a circuit corresponding to the delay content selection circuit 18 between the control signal SCT from the CPU 25 and the variable delay circuits 31 to 33.

(effect)
As described above, the LSI according to the seventh embodiment provides an operation or environment suitable for the scan test operation by including the delay content selection circuit 18 that forcibly matches the phases of all clocks during the scan test. There is an effect that can.

  Furthermore, since the operation equivalent to that of the third LSI is possible in normal times, the clock supply means supplies a plurality of clocks so that their phases are different from each other, thereby effectively suppressing the current peak at a low cost. In addition, local voltage drop is mitigated by reducing power source peak noise.

  As a result, the margin for the voltage drop expected at the time of circuit design is reduced, so that the circuit scale / gate size can be reduced accordingly, and the effect of reducing cost and power consumption can be achieved.

  Moreover, the risk of malfunctioning in the system is reduced by reducing the EMI, and the effect of reducing the cost for EMI countermeasures can be achieved.

<Eighth embodiment>
As described in the seventh embodiment, it is desirable that the clock data is transferred between the modules in the scan test, but the data is actually supplied to the test target circuit (module A21, etc.). In the capture operation, which is a cycle of operating and capturing the operation result, measurement is often performed with a clock having an upper limit of the operation frequency.

  If the clock phase difference between the modules is set small during the capture operation, it may pass during the scan test, but may actually malfunction if a clock phase difference is actually provided between the modules. This is because if the clock phase difference is increased, the data transfer time between clocks having different phases is shortened, and as a result, there is a risk that the operation is not performed at the design operating frequency. This situation is the worst and can lead to a bad market after shipping, which can lead to significant monetary losses and loss of credit.

  The LSI according to the eighth embodiment takes into consideration the operation at the time of capturing the scan test. FIG. 24 is an explanatory diagram showing the structure of an LSI having a clock control function according to the eighth embodiment of the present invention.

  As shown in the figure, in addition to the configuration of the third LSI shown in FIG. 14, a delay content selection circuit 19 which is a clock phase setting circuit is further provided. The delay content selection circuit 19 includes AND gates G1 and G2 and an OR gate G4. The capture enable signal bar SCCP is commonly received at one input of the AND gates G1 and G2, and the capture enable signal bar SCCP is received at one input of the OR gate G4. The inverted signal is received. The AND gate G1 receives a control signal SC21 for controlling the variable delay circuit 31 from the clock control circuit 39 at the other input, and the AND gate G2 receives a control signal SC22 for controlling the variable delay circuit 32 from the clock control circuit 39 at the other input. The OR gate G4 receives a control signal SC23 for controlling the variable delay circuit 33 from the clock control circuit 39 at the other input. The output signals of the AND gates G1 and G2 and the OR gate G4 are given as control signals for the variable delay circuits 31 to 33.

  The CPU 30 performs data transfer to each of the module A21 and the module B22. Note that the capture enable signal bar SCCP is a signal that becomes “L” during capture in the scan test. The other configuration is the same as that of the third LSI shown in FIG.

  In such a configuration, during the normal operation (except during the capture operation), the capture enable signal bar SCCP is “H”, so the LSI of the eighth embodiment performs an operation equivalent to the third LSI.

  On the other hand, since the capture enable signal SCCP is “L” during the capture operation, the output of the OR gate G4 is forcibly set to a fixed value (“1”) indicating the maximum delay, so that the variable delay circuit 33 The delay time can be set to the maximum delay time. On the other hand, the delay time of each of the variable delay circuits 31 and 32 can be set to the minimum delay time by forcibly setting the outputs of the AND gates G1 and G2 to a fixed value (“0”) instructing the minimum delay. .

  As a result, the clock phase difference between the clock CLKP of the CPU 25 and the clocks CLKA and CLKB of the modules A21 and B22 can be set to the maximum during the capture operation. That is, the phase difference between the CPU 25 and the module A21 or the module B22 that is a data transfer target is forcibly set to the maximum value.

  As described above, the LSI according to the eighth embodiment operates when the influence of the clock phase difference is worst by setting the phase difference between the clock CLKA, the clock CLKB, and the clock CLKP to the maximum during the capture operation in the scan test. A frequency test is possible, and a scan test can be performed in a severe operating environment.

  Also, since most modules operate at the highest speed during the capture operation, peak currents that cannot be actually used are generated, but during the capture operation, the clock phases between the modules are not matched and the same as during normal operation. Because of shifting, it is possible to solve the above-mentioned problem relating to the peak current generation.

  In the configuration shown in FIG. 24, the configuration in which the clock control circuit 39 is provided with the control function of the clock supply means is shown. However, like the first LSI shown in FIG. Of course, it is possible to achieve the same configuration by providing a circuit corresponding to the delay content selection circuit 19 between the control signal SCT from the CPU 25 and the variable delay circuits 31 to 33.

  Further, the delay content selection circuit 19 is expanded so that the data transfer operation to the scan FF other than the capture operation at the time of the scan test has the phases of the clock CLKA, the clock CLKB, and the clock CLKP as in the seventh embodiment. It is also possible to make them coincide.

(effect)
As described above, the LSI of the eighth embodiment forcibly maximizes the phase difference of the clock supplied to the test target module (between CPU 30 and module A21 or between CPU 30 and module B22) during the capture operation in the scan test. By providing the delay content selection circuit 19 to be performed, a highly accurate capture operation can be executed under a severe operating environment where there is a possibility of the most malfunction. Further, during normal operation, local voltage drop is mitigated by reducing power source peak noise.

  As a result, the margin for the voltage drop expected at the time of circuit design is reduced, so that the circuit scale / gate size can be reduced accordingly, and the effect of reducing cost and power consumption can be achieved.

  Moreover, the risk of malfunctioning in the system is reduced by reducing the EMI, and the effect of reducing the cost for EMI countermeasures can be achieved.

<Embodiment 9>
In the first to eighth embodiments, when the clock phase is changed, there is a risk of malfunction due to a setup error or a hold error between clocks having different phases. To what extent the phase difference can be normally operated varies depending on the manufacturing variation of the corresponding LSI and ambient conditions such as voltage and temperature.

  FIG. 25 is an explanatory diagram showing a first configuration of the allowable phase difference measuring circuit according to the ninth embodiment of the present invention. As shown in the figure, a delay element 53 is provided between the output part of the two flip-flops 51 and the input part of the flip-flop 52. The flip-flop 51 operates in synchronization with the clock CLK1, and the flip-flop 52 Synchronize with CLK2.

  The flip-flops 51 and 52 can perform a data transfer operation equivalent to the module used in the LSI of the first to eighth embodiments. The delay element 53 is provided on the data transfer path between the flip-flops 51 and 52, and the data transfer delay time between the flip-flops 51 and 52 can be variably controlled.

  In such a configuration, the LSI operation is checked by checking whether the data transfer between the flip-flops 51 and 52 can be performed correctly, that is, whether the stored value of the preceding flip-flop 51 can be correctly latched by the subsequent flip-flop 52. The state can be grasped, and it can be indirectly checked to what extent the phase difference is normally operated.

  There are two specific methods. In the first determination method, the delay time of the delay element 53 is set to the data transfer delay time between the flip-flops 51 and 52 in actual operation, the phase difference is variably measured between the clock CLK1 and the clock CLK2, and the flip-flop It is checked whether data transfer between the groups 51 and 52 can be performed correctly. If the data transfer can be performed correctly, it is determined that the normal operation is possible based on the phase difference between the set clocks CLK1 and CLK2, and if the data transfer is not performed correctly, it is determined that the data transfer is impossible.

  The second determination method is a method of changing the delay amount of the delay element 53 without providing a phase difference between the clocks CLK1 and CLK2. As in the first determination method, the second determination method can measure a delay time in which normal operation is possible depending on whether or not data transfer between the flip-flops 51 and 52 is possible.

  As described above, the first or second determination method is executed, and based on the measurement result, it is possible to measure in advance how much phase difference (delay amount) the normal operation is possible.

  FIG. 26 is an explanatory diagram showing a second configuration of the allowable phase difference measuring circuit according to the ninth embodiment of the present invention. As shown in the figure, a replica circuit 54 is provided between the output part of the two flip-flops 51 and the input part of the flip-flop 52. The flip-flop 51 operates in synchronization with the clock CLK1, and the flip-flop 52 Operates in synchronization with CLK2.

  The replica circuit 54 is a model of a circuit having the same structure as a critical path in a circuit that actually operates, and is configured so as to be able to generate a timing signal that reflects changes in power supply voltage and device characteristics due to temperature fluctuations. It means a circuit that can operate stably over a wide power supply voltage range and temperature range.

  In such a configuration, as in the first configuration, the operation state of the LSI is determined by examining whether data transfer between the flip-flops 51 and 52 can be performed correctly while appropriately changing the phase difference between the clocks CLK1 and CLK2. It can be grasped and it can be indirectly checked to what extent the phase difference is normally operated.

  In the second configuration of the ninth embodiment, by using the replica circuit 54, the measurement result becomes the phase difference allowable range of the actual circuit as it is, and the allowable phase difference can be obtained more accurately because there is no calculation error. . However, the second configuration has a restriction that the critical path needs to be known in advance.

(effect)
As described above, the first configuration of the allowable phase difference measurement circuit according to the ninth embodiment is capable of performing the data transfer operation equivalent to the LSI module that actually operates in synchronization with the clocks CLK1 and CLK2. Are provided on the data transfer path of the flip-flops 51 and 52, and a test delay unit capable of setting a predetermined delay time for data transfer between the flip-flops 51 and 52. A delay element 53 is provided.

  Therefore, the delay time of the delay element 53 is set to the data transfer delay time between the flip-flops 51 and 52 in actual operation, and the phase between the flip-flops 51 and 52 is changed as appropriate, so that the actual LSI modules can be changed. It is possible to measure the phase difference between clocks that can normally transfer data.

  Furthermore, in the second configuration of the allowable phase difference measurement circuit of the ninth embodiment, since the critical circuit delay time is provided between the flip-flops 51 and 52 by the replica circuit 54, the measurement result is directly used between the actual LSI modules. There exists an effect which can be used as a phase difference allowable range.

  As described above, since the allowable phase difference measurement circuit according to the ninth embodiment can obtain the allowable range of the clock phase difference that allows normal data transfer by measurement in advance, the allowable phase difference measurement circuit according to the ninth embodiment can be obtained. By setting the clock phase difference between modules based on the measurement results used, current peaks and EMI can be reduced without risk of malfunction.

  As a result, the margin for the voltage drop expected at the time of circuit design is reduced, so that the circuit scale / gate size can be reduced accordingly, and the effects of cost reduction and power consumption reduction can be achieved.

  Moreover, the risk of malfunctioning in the system is reduced by reducing the EMI, and the effect of reducing the cost for EMI countermeasures can be achieved.

<Embodiment 10>
In the LSIs according to the first to eighth embodiments, when the clock phase is changed between a plurality of modules, there is a risk of causing a malfunction due to a setup error or a hold error between clocks having different phases. Since setup errors only lower the upper limit of the operating frequency, there is no particular problem if there is an operating margin. However, since a hold error malfunctions regardless of the operating frequency, it is difficult to cope with it.

  For example, in the system configuration of the second embodiment shown in FIG. 17, when data is transferred from the module A11 to the module B12, as shown in FIG. 27, the clock CLKB is delayed by the phase difference ΔT1 from the clock CLKA. Suppose. In this case, the output data OUTA of the module A11 changes from the data DT1 to the data DT2 after a time t1, which is the rising edge of the clock CLKA (after the elapse of the inter-module transfer time sufficiently shorter than the phase difference ΔT1).

  Accordingly, since the output data OUTA changes to the data DT2 at the time t2 when the clock CLKB rises, the module B12 that originally needed to input the data DT1 erroneously takes in the data DT2 that is data of the next cycle. Hold error will occur.

  Thus, when the phase of the clock CLKB with respect to the clock CLK1 is delayed more than the timing at which the output of the module A11 reaches the module B12, the module B12 samples the state of the next cycle and malfunctions (hold error). For this reason, a delay time greater than the clock phase difference (phase difference ΔT1) is inserted between the modules A11 and B12, or the phase difference ΔT1 so as to be within the phase difference within the inter-module transfer time from the module A11 to the module B12. It can only cope with setting.

  FIG. 28 is an explanatory diagram showing a first system configuration of the LSI according to the tenth embodiment of the present invention. As shown in the figure, a CPU 30, a module A11, a module B12, and a module C13 are connected to a bus 40 so as to be able to exchange signals. Specifically, the inputs of the CPU 30, the module A11, the module B12, and the module C13 are directly connected to the bus 40, and the outputs of the CPU 30, the module A11, the module B12, and the module C13 are input to the bus 40 via the latches 60 to 63. Connected.

  The CPU 30, the module A11, the module B12, and the module C13 operate in synchronization with the rising edges of the clock CLKP, the clock CLKA, the clock CLKB, and the clock CLKC, and these clocks are the same as those of the first to third LSIs described above. By exhibiting such a circuit configuration, the phase is variably controlled. The latches 60 to 63 operate in synchronization with the falling edges of the clock CLKP, the clock CLKA, the clock CLKB, and the clock CLKC. Specifically, the latches 60 to 63 are in a data through (unlatched) state when the corresponding clock is “L”, and are in a latch state when the corresponding clock is “H”.

  FIG. 29 is a timing chart showing a data transfer operation between the module A11 and the module B12 in the LSI according to the tenth embodiment. As in the case shown in FIG. 27, a phase difference ΔT1 is generated between the clock CLKA and the clock CLKB. Yes.

  As shown in the figure, since the clock CLKB is delayed by the phase difference ΔT1 from the clock CLKA, the output data OUTA of the module A11 changes from the data DT1 to the data DT2 at a timing earlier than the time t2.

  However, since latch 61 uses the falling edge of clock CLKA as a trigger, it does not react to the rising edge of clock CLKA at time t1, and latch 61 continues to store data DT1. In this state, the clock CLKB rises at time t2, so that the module B12 can accurately latch the data DT1 that should be stored from the latch 61.

  Thereafter, with the falling edge of the clock CLKA as a trigger, the latch 61 latches the output data OUTA, so that the data DT2 appears on the bus 40 for the first time at time t3 which is delayed by the time difference ΔT2 from time t2.

  As described above, the timing at which the output data OUTA of the module A11 is output to the bus 40 can be delayed by a half cycle of the clock CLKA due to the presence of the latch 61. Therefore, the original data to be surely taken in at the rising time t2 of the clock CLKB. It can be held on the bus 16. Therefore, the module B12 does not erroneously sample the data DT2 of the next cycle.

  FIG. 30 is an explanatory diagram showing a second system configuration which is an LSI according to the tenth embodiment of the present invention. As shown in the figure, a CPU 30, a module A11, a module B12, and a module C13 are connected to a bus 40 so as to be able to exchange signals. Specifically, the outputs of the CPU 30, the module A11, the module B12, and the module C13 are directly connected to the bus 40, and the inputs of the CPU 30, the module A11, the module B12, and the module C13 are input to the bus 40 via the latches 70 to 73. Connected. The latches 70 to 73 perform the same latch operation as the latches 60 to 63.

  The CPU 30, the module A11, the module B12, and the module C13 operate in synchronization with the rising edges of the clock CLKP, the clock CLKA, the clock CLKB, and the clock CLKC, and these clocks are the same as those of the first to third LSIs described above. By exhibiting such a circuit configuration, the phase is variably controlled. The latches 70 to 73 operate in synchronization with the falling edges of the clock CLKP, the clock CLKA, the clock CLKB, and the clock CLKC.

  In such a second system configuration, for example, assuming a data transfer operation between the module A11 and the module B12, the timing at which the output data OUTA of the module A11 appears at the input of the module B12 depends on the presence of the latch 72. Can be delayed more than half a cycle. For this reason, even at the rising time of the clock CLKB, the original data that should be reliably captured can be held in the input section of the module B12 (the output section of the latch 72). Therefore, the module B12 does not erroneously sample the data of the next cycle.

  FIG. 31 is an explanatory diagram showing a third system configuration which is an LSI according to the tenth embodiment of the present invention. As shown in the figure, the module A11 and the module B12 are directly connected to the bus 40 so as to be able to exchange signals. However, the module A11 and the module B12 are configured to be accessible to each other without going through the bus 40. Specifically, the output of the module A11 is given to the input of the module B12 via the latch 64, and the output of the module B12 is given to the input of the module A11 via the latch 65. The latches 64 and 65 perform the same latching operation as the latches 60 to 63.

  The module A11 and the module B12 operate in synchronization with the rising edges of the clock CLKA and the clock CLKB, and these clocks have a circuit configuration like the above-described first to third LSIs, so that the phase is variably controlled. Is done. The latches 64 and 65 operate in synchronization with the falling edges of the clock CLKA and the clock CLKB.

  In such a third system configuration, for example, assuming a data transfer operation between the module A11 and the module B12, the timing at which the output data OUTA of the module A11 appears at the input of the module B12 depends on the presence of the latch 64. Can be delayed more than half a cycle. For this reason, the original data to be surely taken in even at the rising time of the clock CLKB can be held in the input part of the module B12 (the output part of the latch 64). Therefore, the module B12 does not erroneously sample the data of the next cycle.

  In the first to third system configurations described above, a flip-flop synchronized with the falling edge of the clock may be used instead of the latch that is “L” through.

  As described above, when a latch is used for hold correction, the presence of a falling edge synchronized latch or flip-flop may interfere with the normal operation of the scan test. Therefore, it is desirable to add the following improvements.

  FIG. 32 is an explanatory diagram showing a first improved example of the second system configuration shown in FIG. As shown in the figure, an OR gate G5 having a clock CLKA as one input and a scan enable signal SCAN as the other input is provided, and the output of the OR gate G5 is given to the clock input of the latch 71.

  In such a configuration, since the scan enable signal SCAN is “L” during normal operation (except during the scan test), the circuit is equivalent to the second system configuration shown in FIG. On the other hand, since the scan enable signal SCAN is “H” during the scan test, the latch 71 is always in the data through state. As a result, during the scan test, the scan test can be normally performed using the latch 71 as a simple signal delay means.

  FIG. 33 is an explanatory diagram showing a second improved example of the second system configuration shown in FIG. As shown in the figure, a flip-flop 67 corresponding to the latch 71 receives a clock CLKA as a clock input, and a data input unit is connected to the bus 40. The selection circuit 68 uses the output of the flip-flop 67 as the first input and the signal directly obtained from the bus 40 as the second input. When the scan enable signal SCAN is “L”, the output of the flip-flop 67 is selected and the scan enable signal is selected. When SCAN is “H”, the signal on the bus 40 is selected and applied to the input of the module A11.

  In such a configuration, the scan enable signal SCAN is set to “L” during normal operation (except during the scan test), and the output of the flip-flop 67 is selected by the selection circuit 68. Therefore, the second system shown in FIG. The circuit is equivalent to the configuration. On the other hand, at the time of the scan test, the scan enable signal SCAN becomes “H”, and the signal on the bus 40 is input to the module A11 without passing through the flip-flop 67. As a result, during the scan test, the scan test can be normally performed using the selection circuit 68 as a simple signal delay means.

(effect)
As described above, in the LSI of the tenth embodiment, clocks with different phases are used, and the falling edge synchronization latch or flip-flop of the corresponding module clock is inserted on the signal propagation path between the rising edge synchronization modules. By doing so, there is an effect that current peaks and EMI can be reduced without causing malfunction due to a hold error.

  In other words, the LSI according to the tenth embodiment includes a delay unit that delays the data transfer operation between modules by a delay time determined by a clock input to the module, thereby ensuring a malfunction in the data transfer operation between modules. Can be avoided.

  As a result, the margin for the voltage drop expected at the time of circuit design is reduced, so that the circuit scale / gate size can be reduced accordingly, and the effects of cost reduction and power consumption reduction can be achieved.

  Moreover, the risk of malfunctioning in the system is reduced by reducing the EMI, and the effect of reducing the cost for EMI countermeasures can be achieved.

  Furthermore, since the LSI of the tenth embodiment has a delay invalid function (OR gate G5 (FIG. 32), selection circuit 68 (FIG. 33)) for forcibly invalidating the delay function of the delay means at the time of a scan test, During the scan test, the scan test operation can be performed normally without causing a delay in the data transfer operation by the delay means.

<Embodiment 11>
In recent years, MCM (Multi Chip Package) and SIP (System In Package) that seal a plurality of LSIs in the same package have attracted attention. The LSI according to the eleventh embodiment applies the semiconductor integrated circuit device which is MCM / SIP to the present invention.

  34 is an explanatory diagram showing a first chip configuration of the semiconductor integrated circuit device according to the eleventh embodiment of the present invention. As shown in the figure, a chip A7, a chip B8, and a chip C9 are provided in the SIP 4. Hereinafter, the circuit in the chip C9 will be described.

  As shown in the figure, the chip C9 includes a PLL circuit 20 that supplies a clock CLK20, a module C23, a clock control circuit 37, a delay circuit 38, and variable delay circuits 44 to 46. The module C23 operates in synchronization with the clock CLKC, and the clock control circuit 37 operates in synchronization with the clock CLKX.

  The clock control circuit 37 individually controls the delay times of the variable delay circuits 44 to 46 by control signals SCT21 to SCT23 given to the variable delay circuits 31 to 33, respectively. The variable delay circuits 44 to 46 delay the clock CLK20 from the PLL circuit 20 with a delay time determined based on the control signals SCT21 to SCT23, thereby obtaining the clock CLKA, the clock CLKB, and the clock CLKC having different phases. Further, the delay circuit 38 delays the clock CLK20 to obtain the clock CLKX.

  A circuit (not shown) in the chip A7 outside the chip C9 operates in synchronization with the clock CLKA, and a circuit (not shown) in the chip B8 operates in synchronization with the clock CLKB.

  Thus, in the first chip configuration, the chip C9 in the SIP 4 can have a mechanism for controlling the phase of the clock supplied to the chip A7 and the chip B8 other than the chip C9. In the first chip configuration shown in FIG. 34, the clock phase control is performed by the dedicated clock control circuit 37 as in the third LSI shown in FIG. 17, but the configuration shown in FIG. Similar to the first LSI, it can also be realized by a configuration in which the clock phase is controlled by the CPU. In addition, a method for generating a clock having a phase difference also includes a plurality of phases having different phases as in the second LSI shown in FIG. 10 without having a variable delay circuit as in the first and third LSIs. It can be realized by a configuration for selecting a kind of clock.

  FIG. 35 is an explanatory diagram showing a second chip configuration of the semiconductor integrated circuit device according to the eleventh embodiment of the present invention. As shown in the figure, a chip A 7, a chip C 9 and a chip B 10 are provided in the SIP (or MCM) 5. Since the circuit configuration in the chip C9 is the same as that of the chip C9 having the first chip configuration shown in FIG.

  A circuit (not shown) in the chip A7 outside the chip C9 operates in synchronization with the clock CLKA, and the clock CLKB is input as a reference clock in the chip B10.

  As shown in FIG. 35, the chip B10 includes a module α14, a module β15, and a CPU 55. The module α14 receives the clock CLKα obtained by the clock CLKB via the variable delay circuit 48, and operates in synchronization with the clock CLKα. The module β15 receives the clock CLKβ obtained from the clock CLKB via the variable delay circuit 32, and operates in synchronization with the clock CLKβ. The CPU 55 receives the clock CLKP obtained from the clock CLKB via the variable delay circuit 50, and operates in synchronization with the clock CLKP.

  The CPU 55 individually controls the delay times of the variable delay circuits 48 to 50 by the control signals SCT1 to SCT3 given to the variable delay circuits 48 to 50. Thus, by controlling the delay time of the variable delay circuits 48 to 50 by the CPU 55, the phase between the clock CLKα, the clock CLKβ and the clock CLKP supplied to the module A21, the module B22 and the CPU 55 can be variably controlled. .

  As described above, in the second chip configuration, the chip C9 in the SIP 5 is provided with a mechanism for controlling the phase of the clock supplied to the chip A7 and the chip B10 other than the chip C9, and the internal clock is also provided in the chip B10. It has a mechanism to control the phase.

  Also in the second chip configuration shown in FIG. 35, the clock generation method having a phase difference is the same as that shown in FIG. 10 without having a variable delay circuit like the first and third LSIs. As in the case of LSI 2, it is possible to realize a configuration in which a plurality of types of clocks having different phases are selected.

  In addition to the clock phase control as in the second chip configuration shown in FIG. 35, for example, a method in which a dedicated clock control circuit controls the clock phase in units of modules in each chip is also conceivable. In this case, it can be managed centrally, and if the skew is adjusted appropriately, it can be expected that a very good effect can be obtained in the entire SIP.

  In addition to the clock phase control as in the second chip configuration shown in FIG. 35, for example, a method in which the CPU in one chip controls the clock phase of each module in each chip is conceivable. As another method, a method of controlling the clock phase supplied to each chip in the SIP or MCM by the CPU of one chip and controlling the clock phase individually in each chip other than the above one chip is also conceivable. .

  Of the various methods described above, an optimum method may be selected according to the scale of LSI, the scale of software to be controlled, and development resources.

  In the second chip configuration, a configuration in which the clock phase of the module α14, the module β15, etc. in the chip B10 is controlled in the chip C9 is also conceivable. In this case, the clock control circuit 37 in the chip C9 is included in the chip B10. It is necessary to have the information of the internal circuit (how many modules are there etc.). For this reason, there are disadvantages such as loss of versatility of the clock control circuit 37 in the chip C9 and an increase in signal lines between the chip C9 and the chip B8.

  On the other hand, in the second chip configuration example shown in FIG. 35, since the clock phase control in the chip B10 is performed in the chip B10, the above-described disadvantages do not occur. In addition, since it is relatively easy to change the phase of the clock supplied in units of chips, such as the supply of the clock CLKA to the chip A7, it is possible to apply the clock CLKB to the chip B10 as in the second configuration. It is relatively easy.

(effect)
In the LSI of the eleventh embodiment, a clock supply means for supplying a clock for another chip (chip A7, chip B8) is provided in one chip (chip C9) among the plurality of chips in the SIP or MCM. As a result, a plurality of clocks to be supplied to a plurality of chips can be supplied so that their phases are different from each other, so that a current peak can be effectively suppressed at a low cost even in SIP 4 composed of a plurality of chips.

  Local voltage drop is mitigated by power supply peak noise reduction. As a result, the margin for the voltage drop expected at the time of circuit design is reduced, so that the circuit scale / gate size can be reduced accordingly, and the effects of cost reduction and power consumption reduction can be achieved.

  Moreover, the risk of malfunctioning in the system is reduced by reducing the EMI, and the effect of reducing the cost for EMI countermeasures can be achieved.

  Further, as in the second chip configuration example shown in FIG. 35, in the chip B10 that receives the clock CLKB from the chip C9 as a reference clock, each of the clocks CLKB is delayed to delay a plurality of clocks (CLKα, CLKβ, CLKP). And a CPU 55 which is a delay time control means for controlling the delay time of each of the plurality of delay means. With the above configuration, a plurality of clocks (CLKα, CLKβ, CLKP) supplied between a plurality of modules (14, 15, 55) in the chip B10 can be supplied so as to have different phases. In addition, the current peak can be effectively suppressed at a low cost.

It is explanatory drawing which shows the basic composition of the 1st LSI for implement | achieving LSI of this invention. It is a circuit diagram which shows the 1st example of the internal structure of a variable delay circuit. It is a circuit diagram which shows the 2nd example of an internal structure of a variable delay circuit. It is a circuit diagram which shows the 3rd example of an internal structure of a variable delay circuit. FIG. 2 is a block diagram illustrating a first system configuration example of a first LSI illustrated in FIG. 1. FIG. 3 is a block diagram illustrating a second system configuration example of the first LSI illustrated in FIG. 1. It is explanatory drawing which shows the memory map seen from CPU of the phase control register. It is explanatory drawing which shows the internal structural example of a phase control register. It is explanatory drawing which shows the relationship between the storage content of the phase control register shown in FIG. 8, and control information in a table format. It is explanatory drawing which shows the structural example of the 2nd LSI for implement | achieving LSI of this invention. FIG. 11 is a timing diagram illustrating a waveform of a clock generated from the PLL circuit illustrated in FIG. 10. FIG. 11 is an explanatory diagram illustrating a configuration of an oscillator unit in the first configuration example of the PLL circuit illustrated in FIG. 10. FIG. 11 is an explanatory diagram illustrating a second configuration example of the PLL circuit illustrated in FIG. 10. It is explanatory drawing which shows the basic composition of the 3rd LSI for implement | achieving LSI of this invention. FIG. 3 is an explanatory diagram conceptually showing a physical layout of the LSI according to the first embodiment. It is a flowchart which shows the clock skew adjustment method in LSI which is Embodiment 2 of this invention. FIG. 10 is an explanatory diagram showing a layout configuration centered on a bus in an LSI according to a third embodiment; It is a flowchart which shows the clock skew adjustment method in LSI which is Embodiment 3 of this invention. FIG. 20 is an explanatory diagram showing a layout configuration centered on a bus in an LSI according to the fourth embodiment; It is a flowchart which shows the clock skew adjustment method of LSI which is Embodiment 4 of this invention. FIG. 17 is an explanatory diagram showing a layout configuration centered on a bus in an LSI according to the fifth embodiment; It is a flowchart which shows the phase matching method in the clock skew adjustment method of LSI which is Embodiment 6 of this invention. It is explanatory drawing which shows the structure of LSI which has a clock control function which is Embodiment 7 of this invention. It is explanatory drawing which shows the structure of LSI which has a clock control function which is Embodiment 8 of this invention. It is explanatory drawing which shows the 1st structure of the allowable phase difference measuring circuit which is Embodiment 9 of this invention. It is explanatory drawing which shows the 2nd structure of the allowable phase difference measuring circuit which is Embodiment 9 of this invention. It is a timing diagram shown about the example of a hold error resulting from a clock phase difference. It is explanatory drawing which shows the 1st system configuration which is Embodiment 10 of this invention. FIG. 38 is a timing chart showing a data transfer operation between modules in the LSI according to the tenth embodiment. It is explanatory drawing which shows the 2nd system configuration which is Embodiment 10 of this invention. It is explanatory drawing which shows the 3rd system configuration which is Embodiment 10 of this invention. FIG. 31 is an explanatory diagram showing a first improvement example of the second system configuration shown in FIG. 30. FIG. 31 is an explanatory diagram illustrating a second improvement example of the second system configuration illustrated in FIG. 30. It is explanatory drawing which shows the 1st chip | tip structure of LSI which is Embodiment 11 of this invention. It is explanatory drawing which shows the 2nd chip structure of LSI which is Embodiment 11 of this invention.

Explanation of symbols

  1-3, 25, 28, 30, 55 CPU, 4, 5 SIP, 6 Secondary cache, 7 Chip A, 8, 10 Chip B, 9 Chip C, 11, 21 Module A, 12, 22 Module B, 13 , 23 module C, 14 module α, 15 module β, 16, 40, 59 bus, 17 clock reference bus, 18, 19 delay content selection circuit, 20, 27 PLL circuit, 24, 26 phase control register, 31-33 44-50 variable delay circuit, 37, 39 clock control circuit, 41-43, 68 selection circuit, 51, 52, 67 flip-flop, 53 delay element, 54 replica circuit, 60-65, 70-73 latch, G5 OR gate .

Claims (15)

A plurality of modules arranged on a substrate and operating in synchronization with a plurality of clocks;
Clock supply means for supplying the plurality of clocks to the plurality of modules, and the plurality of clocks are supplied so that their phases are different from each other;
The plurality of modules are arranged on a first module pair arranged on the substrate at a first distance and a second module arranged on the substrate at a second distance longer than the first distance. Including module pairs,
The clock supply means supplies the plurality of clocks so that the phase difference of the clock between the first module pair is smaller than the phase difference of the clock signal between the second module pair. ,
Semiconductor device. A plurality of modules arranged on a substrate and operating in synchronization with a plurality of clocks;
Clock supply means for supplying the plurality of clocks to the plurality of modules;
The plurality of modules include first and second modules to be subjected to data transfer, and the plurality of clocks include first and second clocks supplied to the first and second modules,
The clock supply means makes the phases of the first and second clocks coincide when transferring data between the first and second modules, and is predetermined between the first and second clocks when not transferring data. It is characterized by providing a phase difference of
Semiconductor device. A plurality of modules arranged on a substrate and operating in synchronization with a plurality of clocks;
Clock supply means for supplying the plurality of clocks to the plurality of modules;
The plurality of modules include first and second modules that transfer data to each other via a commonly connected bus, and the plurality of clocks are supplied to the first and second modules. A bus clock that is a clock at the time of data transfer via the bus is set in advance,
The clock supply means makes the first and second clocks coincide with the phase of the basque clock when transferring data between the first and second modules, and the first and second clocks when not transferring data. Providing a predetermined phase difference between clocks,
Semiconductor device. A plurality of CPUs arranged on a substrate and operating in synchronization with a plurality of clocks;
Clock supply means for supplying the plurality of clocks to the plurality of CPUs;
The plurality of CPUs each have a primary cache inside, and access a commonly connected secondary cache;
The clock supply means sets a plurality of clocks supplied to the plurality of CPUs to different phase differences from each other, and a clock of a CPU that desires access to the secondary cache only when accessing the secondary cache, and the clock It is characterized by matching the phase with the clock of the secondary cache,
Semiconductor device. A plurality of modules arranged on a substrate and operating in synchronization with a plurality of clocks;
Clock supply means for supplying the plurality of clocks to the plurality of modules, and the plurality of clocks are supplied so that their phases are different from each other;
A reference clock serving as a reference between the plurality of clocks is preset,
The clock supply means supplies the plurality of clocks based on the operation state of each of the plurality of modules so that the phase of the plurality of clocks approaches the phase of the reference clock as the operation state becomes higher speed operation. It is characterized by
Semiconductor device. The semiconductor device according to claim 2,
When the clock supply means matches the phase of the first and second clocks during data transfer between the first and second modules, the clock of the module in the low-speed operation state among the first and second modules. Characterized by changing the phase of
Semiconductor device. A semiconductor device according to any one of claims 1 to 6,
A phase setting circuit for forcibly matching the phases of the plurality of clocks during a scan test;
Semiconductor device. A semiconductor device according to any one of claims 1 to 6,
The plurality of modules are scan test targets, and include first and second test target modules that perform data transfer during the scan test,
Phase setting circuit for forcibly maximizing a phase difference between clocks supplied to the first and second test target modules at the time of capture in which the plurality of modules are actually operated in the scan test and the operation results are captured. Further comprising
Semiconductor device. A plurality of modules arranged on a substrate and operating in synchronization with a plurality of clocks;
Clock supply means for supplying the plurality of clocks to the plurality of modules, and the plurality of clocks are supplied so that their phases are different from each other;
The plurality of modules include first and second modules to be subjected to data transfer, and the plurality of clocks include first and second clocks supplied to the first and second modules,
The clock supply means provides a predetermined phase difference between the first and second clocks;
The semiconductor device includes:
Delay means provided between the first and second modules and further delaying a data transfer operation between the first and second modules by a delay time determined by the first or second clock. ,
Semiconductor device. The semiconductor device according to claim 9,
The delay means has a delay invalid function in which the delay function is forcibly invalidated during a scan test.
Semiconductor device. A semiconductor device according to any one of claims 1 to 10,
The clock supply means includes
A plurality of delay means each for delaying a reference clock to obtain the plurality of clocks;
A delay time control means for controlling the delay time of each of the plurality of delay means,
Each of the plurality of delay means includes a plurality of delay elements in which the number of delay stages can be variably controlled.
Semiconductor device. A first chip having a circuit equivalent to the clock supply means of the semiconductor device according to any one of claims 1 to 11,
A second chip different from the first chip, wherein the second chip uses one of a plurality of clocks supplied by the clock supply means of the first chip as a second chip clock. receive,
Semiconductor integrated circuit device. A semiconductor integrated circuit device according to claim 12, wherein
A plurality of delay means each for delaying the second chip clock to obtain a plurality of clocks;
A delay time control means for controlling the delay time of each of the plurality of delay means,
Semiconductor integrated circuit device. An allowable phase difference measurement circuit for a semiconductor device having clock supply means for supplying a plurality of clocks to a plurality of modules arranged on a substrate, wherein the plurality of modules are first and second modules to be data transferred. The plurality of clocks include first and second clocks supplied to the first and second modules, and the clock supply means provides a predetermined phase difference between the first and second clocks. ,
The allowable phase difference measurement circuit includes:
First and second test circuits capable of performing a data transfer operation equivalent to the first and second modules in synchronization with the first and second test clocks;
A test delay unit provided on a data transfer path of the first and second test circuits and capable of setting a predetermined delay time for data transfer between the first and second test circuits;
Allowable phase difference measurement circuit. The allowable phase difference measuring circuit according to claim 14,
The predetermined delay time includes a delay time of a critical path of the semiconductor device;
Allowable phase difference measurement circuit.

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