CN105718401A - Multiplexing method and system for converting multi-path SMII signal to one-path MII signal - Google Patents
Multiplexing method and system for converting multi-path SMII signal to one-path MII signal Download PDFInfo
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Abstract
The present invention relates to a multiplexing method for converting a multi-path SMII signal to a one-path MII signal. The method comprises the following steps: 1) an FPGA receives a multi-path SMII signal, converts the multi-path SMII signal into a parallel signal in each path by means of a serial-to-parallel converter, and writes the parallel signal into two buffers of a receiving process module; 2) the FPGA reads the parallel signal in the buffer of the receiving process module in each path; and 3) sending the parallel signal that is read in each path by means of a logic sending circuit of an MII signal interface. Compared with the prior art, the method and system provided by the present invention have the advantages of powerful functions, wide applicability and strong portability and the like.
Description
Technical field
The present invention relates to the communications field, especially relate to a kind of multichannel SMII signal to the multiplexing method of a road MII signal and system.
Background technology
MII, i.e. GMII, be the Ethernet industry standard of IEEE-802.3 definition, be connected with various types of PHY for FastEthernetMAC-block.It includes a data-interface and the management interface between MAC and PHY, and data-interface includes two independent channels being respectively used to transmitters and receivers.Every channel has the data of oneself, clock and control signal, and management interface is a dual signal interface, and one is clock signal, and another is data signal, and by management interface, upper strata can monitor and control PHY.
SMII is a kind of media interface proposed by Cisco, and it has the line number signal more less than RMII, S to represent the meaning of serial.Because it only transmits with a holding wire and sends data, a piece holding wire transmission receives data, so on clock demand in order to meet 100, its clock frequency is significantly high, reach 125,000,000, why with 125,000,000, be because inside data wire and can transmit some control information, mono-port of SMII only completes the transmission of 100 signals with 4 holding wires, has almost lacked again the holding wire of a times compared with RMII.SMII is significantly high in the supporting dynamics of industrial quarters, in like manner, and the 125M clock of all public same outside of the data transmit-receive of all of the port.
The road SMII signal serioparallel exchange to a road MII signal is only achieved when prior art, and under the various application occasions such as SDH, need the conversion realizing multichannel SMII signal with MII signal, technically need the serioparallel exchange repeatedly using a road SMII signal to a road MII signal, thus causing the waste of ample resources.
Summary of the invention
Defect that the purpose of the present invention is contemplated to overcome above-mentioned prior art to exist and provide a kind of powerful, the suitability wide, portable strong multichannel SMII signal is to the multiplexing method of a road MII signal and system.
The purpose of the present invention can be achieved through the following technical solutions:
A kind of multichannel SMII signal, to the multiplexing method of a road MII signal, in order to receive multichannel SMII signal, serioparallel exchange in FPGA and to be sent as a road MII signal, comprises the following steps:
1) FPGA receives multichannel SMII signal, is converted to parallel signal respectively through deserializer, and is written in two relief areas of receiving processing module in each road；
2) FPGA reads the parallel signal in the relief area of each road receiving processing module respectively；
3) parallel signal read in each road is sent by the logic transtation mission circuit of MII signaling interface.
Described step 1) comprise the following steps:
11) FPGA powers on, it is judged that whether reset signal R is 1, if R is 1, then register information initializes, and returns step 11), if R is not 1, then carry out step 12)；
12) judge whether clock signal S is rising edge, if so, then enter step 13), if it is not, then return step 12)；
13) judging whether synchronizing signal C is 1, if so, then digit counter W resets, and carries out step 14), if it is not, then carry out step 16)
14) starting to receive data, it is judged that when digit counter W data value is 2, whether the status signal D received is 1, if, the signal then received is information, carries out step 15), if not, the signal then received is state, abandons the signal received, and returns step 13)；
15) judging whether buffer flag F is 1, if so, then write information to relief area 0, address pointer P0, from adding 1, returns step 11), if it is not, then write information to relief area 1, address pointer P1, from adding 1, returns step 11)；
16) whether the value judging digit counter W is 0, if so, then starts to receive a SMII serial data, carries out step 17), if it is not, then the value of digit counter W is from adding 1, carry out step 18)；
17) judge whether the value detecting signal B is 1, if so, then continue to the IP frame of SMII serial data, and the value arranging reception status signal D is 1, returns step 11), if it is not, then the IP frame reception of SMII serial data terminates, carry out step 19)；
18) when receiving status signal D and being 1, SMII data signal is received；
19) arranging the value receiving status signal D is 0, and judges whether buffer flag F is 1, is if so, then written to by address pointer P1 in frame length depositor L1, simultaneously P1 clear 0, and buffer flag F sets to 0；If it is not, then address pointer P0 is written in frame length depositor L0, P0 clear 0 simultaneously, buffer flag F puts 1, and output enable puts 1, returns step 11).
Described step 2) comprise the following steps:
21) FPGA powers on, it is judged that whether reset signal R is 1, if R is 1, then register information initializes, and returns step 21), if R is not 1, then carry out step 22)；
22) judge whether clock signal S is rising edge, if so, then enter step 23), if it is not, then return step 22)；
23) judging that output enables whether signal e is 1, the information if so, then enabled in relief area is readable, carries out step 24), if it is not, the information then enabled in relief area is unreadable, reads address pointer P and reset, return step 21)；
24) judge whether buffer flag F is 1, if so, then read the information of relief area 0, carry out step 25), if it is not, then read the information of relief area 1, carry out step 27)；
25) judge whether read clock signal H is 1, if so, then export high 4 bit data under current pointer, read address pointer P from adding 1, if it is not, low 4 bit data then exported under current pointer, carry out step 26)；
26) whether equal with frame length L judging to read address pointer P, if so, then the information of current IP frame has read, and reads address and refers to P pin clear 0, and buffer flag F puts 1, and output enables e and puts 1, and returns step 21), if it is not, then return step 25)；
27) judge whether read clock signal H is 1, if so, then export high 4 bit data under current pointer, read address pointer P from adding 1, if it is not, low 4 bit data then exported under current pointer, carry out step 28)；
28) whether equal with frame length L judging to read address pointer P, if so, then the information of current IP frame has read, and reads address and refers to P pin clear 0, and buffer flag F sets to 0, and output enables e and puts 1, and returns step 21), if it is not, then return step 25).
Described step 3) comprise the following steps:
31) judging whether g signal is 1, if so, then N system Counter A starts counting up when the trailing edge of clock signal H, exports s1-sn, carries out step 32), if it is not, return to step 31)；
32) judge that output enables whether signal f is 1, if so, close N system Counter A, export by N system decoder B and K decoding the data selecting respective channel relief area, start 24 preset down counter J, carry out step 33), return to step 31 if not)；
33) judging whether preset down counter is reduced to is 0, if so, opens N system Counter A, returns to step 31), if it is not, return to step 33).
A kind of multichannel SMII signal is to a road MII signal multiplexing system, in order to receive multichannel SMII signal, serioparallel exchange and to be sent as a road MII signal, including the SMII interface, receiving processing module and the sending module that are sequentially connected with, described SMII interface and receiving processing module are multichannel.
Described receiving processing module includes external clock, state information memory, frequency divider and the deserializer being sequentially connected with, IP frame buffer, writing controller, relief area and Read Controller, and described external clock is connected with deserializer, IP frame buffer, writing controller, relief area and frequency divider respectively；Described frequency divider is connected with Read Controller.
Described relief area is provided with two, and the capacity of each relief area is all higher than or equal to two IP frames, the length of IP frame is with the agreement change used, and IPv4 length is 32, and IPv6 length is 128.
Described sending module includes logic transtation mission circuit, described logic transtation mission circuit includes enumerator, decoder or door, MUX, preset down counter, the first status signal memorizer and the second status signal memorizer, described enumerator is connected with frequency divider, decoder, MUX, the first status signal memorizer and the second status signal memorizer respectively, described or door respectively with receiving processing module, decoder, preset down counter, the first status signal memorizer and the second status signal memorizer.
The system of described enumerator is consistent with SMII signaling interface number.
Compared with prior art, the invention have the advantages that
One, powerful, present invention achieves the serioparallel exchange not only achieving signal, and also achieve multichannel SMII signal multiplexing to 1 road MII signal, improve communication speed.
Two, the suitability is wide, and in the present invention, multiplex channel number can freely configure, it is possible to reply multichannel SMII signal.
Three, portable strong, present configuration is simple, is suitable for major part FPGA development platform.
Accompanying drawing explanation
Fig. 1 is the flow chart receiving SMII signal in the present invention.
Fig. 2 is the flow chart reading parallel signal in the present invention.
Fig. 3 is the system structure schematic diagram of the present invention.
Fig. 4 is the structural representation of receiving processing module.
Wherein: 1, SMII interface, 2, receiving processing module, 21, deserializer, 22, IP frame buffer, 23, writing controller, 24, relief area, 25, Read Controller, 26, state information memory, 27, frequency divider, 31, enumerator, 32, decoder, 33 or door, 34, MUX, 35, preset down counter, the 36, first status signal memorizer, the 37, second status signal memorizer.
Detailed description of the invention
Below in conjunction with the drawings and specific embodiments, the present invention is described in detail.
Embodiment:
A kind of multichannel SMII signal, to the multiplexing method of a road MII signal, comprises the following steps:
1) FPGA receives multichannel SMII signal, is converted to parallel signal respectively through deserializer, and is written in two relief areas of receiving processing module in each road；
Signal receiving part divides and is made up of multiple receiving processing modules, and each receiving processing module distributes two and receives relief area, and time occupied when a relief area is because of transmission data, another relief area available receives data.The data that each SMII interface receives must in units of ethernet frame buffer memory, and each relief area at least can two IP frames of buffer memory, the length of IP frame with use agreement change, IPv4 length is 32, and IPv6 length is 128.On each SMII interface two receive relief area and have two kinds of control authorities, when relief area is empty, are controlled by SMII, and SMII can be written to the IP data received in this relief area；After having received an IP frame, control authority transfers MII interface to；
2) FPGA reads the parallel signal in the relief area of each road receiving processing module respectively；
Which of two relief areas be signal-obtaining part selected to read by reading buffer flag, determines, by " base address, relief area+address pointer ", the position reading data, and address pointer is to read the rising edge of clock from adding 1；The byte read is converted to nibble through alternative multiplexer；The control end of alternative multiplexer is the two divided-frequency of MII interface clock；When " base address, relief area+address pointer " is equal with ethernet frame length in this relief area, illustrate that in this relief area, content has read, read buffer flag simultaneously and point to another relief area, read address pointer clear 0；
3) parallel signal read in each road is sent by the logic transtation mission circuit of MII signaling interface.
Signal transmission unit is divided into what a complete ethernet frame data of buffer memory could be sent after obtaining control by MII interface by MII interface, and every time must the complete IP frame of disposable transmission.After transmission terminates, this relief area is set to dummy status, and control switches back into again SMII interface.MII interface has a buffer management state machine, each SMII buffer state of circular test, and relief area is for, time full, sending buffer contents.As long as configuring SMII number of channels according to SMII and MII interface rate just to meet data in each passage not result in data overstocked, it is achieved low speed SMII signal converts high speed MII signal to.
As it is shown in figure 1, receive information process for a road SMII, when there is N road SMII and receive simultaneously, being independent of each other in the SMII information reception process of each road, principle is similar, step 1) comprise the following steps:
11) FPGA powers on, it is judged that whether reset signal R is 1, if R is 1, then register information initializes, and returns step 11), if R is not 1, then carry out step 12)；
12) judge whether clock signal S is rising edge, if so, then enter step 13), if it is not, then return step 12)；
13) judging whether synchronizing signal C is 1, if so, then digit counter W resets, and carries out step 14), if it is not, then carry out step 16)；
14) starting to receive data, it is judged that when digit counter W data value is 2, whether the status signal D received is 1, if, the signal then received is information, carries out step 15), if not, the signal then received is state, abandons the signal received, and returns step 13)；
15) judging whether buffer flag F is 1, if so, then write information to relief area 0, address pointer P0, from adding 1, returns step 11), if it is not, then write information to relief area 1, address pointer P1, from adding 1, returns step 11)；
16) whether the value judging digit counter W is 0, if so, then starts to receive a SMII serial data, carries out step 17), if it is not, then the value of digit counter W is from adding 1, carry out step 18)；
17) judge whether the value detecting signal B is 1, if so, then continue to the IP frame of SMII serial data, and the value arranging reception status signal D is 1, returns step 11), if it is not, then the IP frame reception of SMII serial data terminates, carry out step 19)；
18) when receiving status signal D and being 1, SMII data signal is received；
19) arranging the value receiving status signal D is 0, and judges whether buffer flag F is 1, is if so, then written to by address pointer P1 in frame length depositor L1, simultaneously P1 clear 0, and buffer flag F sets to 0；If it is not, then address pointer P0 is written in frame length depositor L0, P0 clear 0 simultaneously, buffer flag F puts 1, and output enable puts 1, returns step 11).
As in figure 2 it is shown, receive information process for a road SMII, when there is N road SMII and receive simultaneously, being independent of each other in the SMII information reception process of each road, principle is similar, step 2) comprise the following steps:
21) FPGA powers on, it is judged that whether reset signal R is 1, if R is 1, then register information initializes, and returns step 21), if R is not 1, then carry out step 22)；
22) judge whether clock signal S is rising edge, if so, then enter step 23), if it is not, then return step 22)；
23) judging that output enables whether signal e is 1, the information if so, then enabled in relief area is readable, carries out step 24), if it is not, the information then enabled in relief area is unreadable, reads address pointer P and reset, return step 21)；
24) judge whether buffer flag F is 1, if so, then read the information of relief area 0, carry out step 25), if it is not, then read the information of relief area 1, carry out step 27)；
25) judge whether read clock signal H is 1, if so, then export high 4 bit data under current pointer, read address pointer P from adding 1, if it is not, low 4 bit data then exported under current pointer, carry out step 26)；
26) whether equal with frame length L judging to read address pointer P, if so, then the information of current IP frame has read, and reads address and refers to P pin clear 0, and buffer flag F puts 1, and output enables e and puts 1, and returns step 21), if it is not, then return step 25)；
27) judge whether read clock signal H is 1, if so, then export high 4 bit data under current pointer, read address pointer P from adding 1, if it is not, low 4 bit data then exported under current pointer, carry out step 28)；
28) whether equal with frame length L judging to read address pointer P, if so, then the information of current IP frame has read, and reads address and refers to P pin clear 0, and buffer flag F sets to 0, and output enables e and puts 1, and returns step 21), if it is not, then return step 25)；
Step 3) comprise the following steps:
31) judging whether g signal is 1, if so, then N system Counter A starts counting up when the trailing edge of clock signal H, exports s1-sn, carries out step 32), if it is not, return to step 31),
32) judge that output enables whether signal f is 1, if so, close N system Counter A, export by N system decoder B and K decoding the data selecting respective channel relief area, start 24 preset down counter J, carry out step 33), return to step 31 if not)；
33) judging whether preset down counter is reduced to is 0, if so, opens N system Counter A, returns to step 31), if it is not, return to step 33).
Send process for four road SMII information, under outside resources supplIes is abundant, N road SMII information can be expanded and send.
Quaternary enumerator, counting clock h is MII interface data clock, when g signal is high level, counts when clock signal h is trailing edge, the signal of output s1-s2 two.(when multichannel SMII interface is N road, corresponding enumerator is N system Counter, and the relation of output signal figure place n and N is that 2^n >=N and n are minimum positive integer).
Decoder, decodes the output signal s1-s2 of enumerator, and translating result significant level is that high level (works as s1-When s2 is " 00 ", translate result for " 0001 ").(when multichannel SMII interface is N road, decoder input is the n in (1), translates figure place N^ ' >=N).
Four or door, four or the input of door enable the signal of signal (e1-e4) Xiang Yuhou for decoder output result and four corresponding receiving processing modules outputs, if decoding result and corresponding enable logic phase and after be 1, then four or the output f of door be 1.Enumerator starts counting up from 0 to 4, count results through decoder, then with corresponding enable signal phase with, with result through four or door output f.Enumerator after decoder with enable signal phase with, it is achieved to each receiving processing module circular test.(when multichannel SMII interface is N road, corresponding N or door, n road input decoder translates in figure place N^ ' that only N number of result is effective, N number of enable signal of the corresponding N number of receiving processing module of this N number of result).
Four select a selector, the output result according to enumerator, and the signal of corresponding receiving processing module relief area is exported d, as when s1-s2 is " 01 ", selected the d2 of receiving processing module 2 as output, i.e. d=d2.(when multichannel SMII interface is N road, enumerator output figure place is n, and signal is s1-sn, exports signal s1-sn according to n position, selects to export a road of N number of receiving processing module).
Preset 24 down counters, when the output signal f of four or door is high, triggers unlatching four or door and turn off quaternary enumerator, only just open four or door when preset 24 down counters count down to 0.
As shown in Figure 3 and Figure 4, a kind of multichannel SMII signal is to the multiplex system of a road MII signal, in order at FPGA internal receipt multichannel SMII signal, serioparallel exchange and be sent as a road MII signal, it is characterized in that, it is multichannel including the SMII interface 1 being sequentially connected with, receiving processing module 2 and sending module, SMII interface 1 and receiving processing module 2.
Receiving processing module 2 includes external clock, state information memory 26, frequency divider 27 and the deserializer 21 being sequentially connected with, IP frame buffer 22, writing controller 23, relief area 24 and Read Controller 25, and external clock is connected with deserializer 21, IP frame buffer 22, writing controller 23, relief area 24 and frequency divider 27 respectively；Frequency divider 27 is connected with Read Controller 25, and relief area 24 is provided with two.
Sending module includes logic transtation mission circuit, logic transtation mission circuit includes enumerator 31, decoder 32 or door 33, MUX 34, preset down counter the 35, first status signal memorizer 36 and the second status signal memorizer 37, enumerator 31 is connected with frequency divider 27, decoder 32, MUX the 34, first status signal memorizer 36 and the second status signal memorizer 37 respectively, or door 33 respectively with receiving processing module 2, decoder 32, preset down counter the 35, first status signal memorizer 36 and the second status signal memorizer 37.
Claims (9)
1. multichannel SMII signal is to a multiplexing method for a road MII signal, in order to receive multichannel SMII signal, serioparallel exchange in FPGA and to be sent as a road MII signal, it is characterised in that comprise the following steps:
1) FPGA receives multichannel SMII signal, is converted to parallel signal respectively through deserializer, and is written in two relief areas of receiving processing module in each road；
2) FPGA reads the parallel signal in the relief area of each road receiving processing module respectively；
3) parallel signal read in each road is sent by the logic transtation mission circuit of MII signaling interface.
2. a kind of multichannel SMII signal according to claim 1 is to the multiplexing method of a road MII signal, it is characterised in that described step 1) comprise the following steps:
11) FPGA powers on, it is judged that whether reset signal R is 1, if R is 1, then register information initializes, and returns step 11), if R is not 1, then carry out step 12)；
12) judge whether clock signal S is rising edge, if so, then enter step 13), if it is not, then return step 12)；
13) judging whether synchronizing signal C is 1, if so, then digit counter W resets, and carries out step 14), if it is not, then carry out step 16)；
14) starting to receive data, it is judged that when digit counter W data value is 2, whether the status signal D received is 1, if, the signal then received is information, carries out step 15), if not, the signal then received is state, abandons the signal received, and returns step 13)；
15) judging whether buffer flag F is 1, if so, then write information to relief area 0, address pointer P0, from adding 1, returns step 11), if it is not, then write information to relief area 1, address pointer P1, from adding 1, returns step 11)；
16) whether the value judging digit counter W is 0, if so, then starts to receive a SMII serial data, carries out step 17), if it is not, then the value of digit counter W is from adding 1, carry out step 18)；
17) judge whether the value detecting signal B is 1, if so, then continue to the IP frame of SMII serial data, and the value arranging reception status signal D is 1, returns step 11), if it is not, then an IP frame reception of SMII serial data terminates, carry out step 19)；
18) when receiving status signal D and being 1, SMII data signal is received；
19) arranging the value receiving status signal D is 0, and judges whether buffer flag F is 1, is if so, then written to by address pointer P1 in frame length depositor L1, simultaneously P1 clear 0, and buffer flag F sets to 0；If it is not, then address pointer P0 is written in frame length depositor L0, P0 clear 0 simultaneously, buffer flag F puts 1, and output enable puts 1, returns step 11).
3. a kind of multichannel SMII signal according to claim 1 is to the multiplexing method of a road MII signal, it is characterised in that described step 2) comprise the following steps:
21) FPGA powers on, it is judged that whether reset signal R is 1, if R is 1, then register information initializes, and returns step 21), if R is not 1, then carry out step 22)；
22) judge whether clock signal S is rising edge, if so, then enter step 23), if it is not, then return step 22)；
23) judging that output enables whether signal e is 1, the information if so, then enabled in relief area is readable, carries out step 24), if it is not, the information then enabled in relief area is unreadable, reads address pointer P and reset, return step 21)；
24) judge whether buffer flag F is 1, if so, then read the information of relief area 0, carry out step 25), if it is not, then read the information of relief area 1, carry out step 27)；
25) judge whether read clock signal H is 1, if so, then export high 4 bit data under current pointer, read address pointer P from adding 1, if it is not, low 4 bit data then exported under current pointer, carry out step 26)；
26) whether equal with frame length L judging to read address pointer P, if so, then the information of current IP frame has read, and reads address and refers to P pin clear 0, and buffer flag F puts 1, and output enables e and puts 1, and returns step 21), if it is not, then return step 25)；
27) judge whether read clock signal H is 1, if so, then export high 4 bit data under current pointer, read address pointer P from adding 1, if it is not, low 4 bit data then exported under current pointer, carry out step 28)；
28) whether equal with frame length L judging to read address pointer P, if so, then the information of current IP frame has read, and reads address and refers to P pin clear 0, and buffer flag F sets to 0, and output enables e and puts 1, and returns step 21), if it is not, then return step 25).
4. a kind of multichannel SMII signal according to claim 1 is to the multiplexing method of a road MII signal, it is characterised in that described step 3) comprise the following steps:
31) judging whether g signal is 1, if so, then N system Counter A starts counting up when the trailing edge of clock signal H, exports s1-sn, carries out step 32), if it is not, return to step 31)；
32) judge that output enables whether signal f is 1, if so, close N system Counter A, export by N system decoder B and K decoding the data selecting respective channel relief area, start 24 preset down counter J, carry out step 33), return to step 31 if not)；
33) judging whether preset down counter is reduced to is 0, if so, opens N system Counter A, returns to step 31), if it is not, return to step 33).
5. a multichannel SMII signal is to the multiplex system of a road MII signal, in order to receive multichannel SMII signal, serioparallel exchange and to be sent as a road MII signal, it is characterized in that, including the SMII interface (1) being sequentially connected with, receiving processing module (2) and sending module, described SMII interface (1) and receiving processing module (2) are multichannel.
6. a kind of multichannel SMII signal according to claim 5 is to the multiplex system of a road MII signal, described receiving processing module (2) includes external clock, state information memory (26), frequency divider (27) and the deserializer (21) being sequentially connected with, IP frame buffer (22), writing controller (23), relief area (24) and Read Controller (25), described external clock respectively with deserializer (21), IP frame buffer (22), writing controller (23), relief area (24) and frequency divider (27) connect；Described frequency divider (27) is connected with Read Controller (25).
7. a kind of multichannel SMII signal according to claim 6 is to the multiplex system of a road MII signal, and described relief area (24) is provided with two, and the capacity of each relief area (24) is all higher than or is equal to two IP frames.
8. a kind of multichannel SMII signal according to claim 6 is to the multiplex system of a road MII signal, described sending module includes logic transtation mission circuit, described logic transtation mission circuit includes enumerator (31), decoder (32), or door (33), MUX (34), preset down counter (35), first status signal memorizer (36) and the second status signal memorizer (37), described enumerator (31) respectively with frequency divider (27), decoder (32), MUX (34), first status signal memorizer (36) and the second status signal memorizer (37) connect, described or door (33) respectively with receiving processing module (2), decoder (32), preset down counter (35), first status signal memorizer (36) and the second status signal memorizer (37).
9. a kind of multichannel SMII signal according to claim 8 is to the multiplex system of a road MII signal, and the system of described enumerator (31) is consistent with SMII signaling interface number.
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| CN110134630A (en) * | 2019-05-27 | 2019-08-16 | 西安电子工程研究所 | A kind of transmission cache controller design method of multiple input single output |
| CN111128245A (en) * | 2019-12-19 | 2020-05-08 | 珠海市一微半导体有限公司 | Voice framing processing circuit and method |
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| CN105718401B (en) | 2018-08-21 |
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